forked from len0rd/rockbox
S5L8702, S5L8720: Merge syscon_preinit() and miu_preinit() between SoC models
No difference in the produced binaries for ipodnano2g and ipod6g (normal and bootloader) This is a part of the large iPod Nano 3G and iPod Nano 4G support patch. Credit: Cástor Muñoz <cmvidal@gmail.com> Change-Id: Ia6a2d2b220d36a56f81fc7c8d05f7c025e2ee766
This commit is contained in:
Vencislav Atanasov
Solomon Peachy
parent
e9b14b3986
commit
ca5f12ae58
1 changed files with 62 additions and 72 deletions
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@ -317,26 +317,66 @@ void memory_init(void)
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#ifdef BOOTLOADER
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#include <stdbool.h>
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#if defined(IPOD_6G) || defined(IPOD_NANO3G)
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static void syscon_preinit(void)
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{
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/* after ROM boot, CG16_SYS is using PLL0 @108 MHz
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CClk = 108 MHz, HClk = 54 MHz, PClk = 27 MHz */
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#if CONFIG_CPU == S5L8702
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CLKCON0 &= ~CLKCON0_SDR_DISABLE_BIT;
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#elif CONFIG_CPU == S5L8720
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int sec_epoch = soc_get_sec_epoch();
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PWRCON(0) = 0x327e5;
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PWRCON(1) = 0xfe2bed6d;
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PWRCON(2) = 0x73;
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PWRCON(3) = 0xff;
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PWRCON(4) = 0xdcf779;
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if (sec_epoch)
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CLKCON0 &= ~CLKCON0_SDR_DISABLE_BIT;
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else
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CLKCON0 |= CLKCON0_SDR_DISABLE_BIT;
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#endif
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PLLMODE &= ~PLLMODE_OSCSEL_BIT; /* CG16_SEL_OSC = OSC0 */
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#if CONFIG_CPU == S5L8702
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cg16_config(&CG16_SYS, true, CG16_SEL_OSC, 1, 1);
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soc_set_system_divs(1, 1, 1);
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#elif CONFIG_CPU == S5L8720
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cg16_config(&CG16_SYS, true, CG16_SEL_OSC, 1, 1, 0x0);
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// soc_set_system_divs(1, 1, 1);
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CLKCON1 = 0;
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while (CLKCON1);
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#endif
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/* stop all PLLs */
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for (int pll = 0; pll < 3; pll++)
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pll_onoff(pll, false);
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#if CONFIG_CPU == S5L8702
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pll_config(2, PLLOP_DM, 1, 36, 1, 32400);
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pll_onoff(2, true);
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soc_set_system_divs(1, 2, 2 /*hprat*/);
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#elif CONFIG_CPU == S5L8720
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PLLUNK3C = 0;
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pll_config(0, PLLOP_DM, sec_epoch ? 6 : 3, 133, 1, 39900);
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pll_onoff(0, true);
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// soc_set_system_divs(1, 2, 1 /*hprat*/);
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// XXX: Without this, SDRAM does not work!
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uint32_t val = 0x404040;
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CLKCON1 = val;
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while (CLKCON1 != val);
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CLKCON0 |= CLKCON0_UNK30_BIT;
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#endif
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#if CONFIG_CPU == S5L8702
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cg16_config(&CG16_SYS, true, CG16_SEL_PLL2, 1, 1);
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cg16_config(&CG16_2L, false, CG16_SEL_OSC, 1, 1);
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cg16_config(&CG16_SVID, false, CG16_SEL_OSC, 1, 1);
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@ -345,17 +385,33 @@ static void syscon_preinit(void)
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cg16_config(&CG16_AUD2, false, CG16_SEL_OSC, 1, 1);
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cg16_config(&CG16_RTIME, true, CG16_SEL_OSC, 1, 1);
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cg16_config(&CG16_5L, false, CG16_SEL_OSC, 1, 1);
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#elif CONFIG_CPU == S5L8720
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cg16_config(&CG16_SYS, true, CG16_SEL_PLL0, 1, 1, 0x0);
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cg16_config(&CG16_LCD, false, CG16_SEL_OSC, 1, 1, 0x0);
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cg16_config(&CG16_SVID, false, CG16_SEL_OSC, 1, 1, 0x0);
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cg16_config(&CG16_AUD0, false, CG16_SEL_OSC, 1, 1, CG16_UNK14_BIT);
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cg16_config(&CG16_AUD1, false, CG16_SEL_OSC, 1, 1, CG16_UNK14_BIT);
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cg16_config(&CG16_AUD2, false, CG16_SEL_OSC, 1, 1, CG16_UNK14_BIT);
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// TODO: configure a 12 MHz ECLK for all targets, so the timer settings will be the same.
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// cg16_config(&CG16_RTIME, true, CG16_SEL_OSC, (S5L8720_OSC0_HZ / ECLK), 1, 0);
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cg16_config(&CG16_RTIME, true, CG16_SEL_OSC, 1, 1, 0x0);
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cg16_config(&CG16_5L, false, CG16_SEL_OSC, 1, 1, 0x0);
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cg16_config(&CG16_6L, false, CG16_SEL_OSC, 1, 1, 0x0);
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#endif
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soc_set_hsdiv(1);
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#if CONFIG_CPU == S5L8702
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PWRCON_AHB = ~((1 << CLOCKGATE_SMx) |
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(1 << CLOCKGATE_SM1));
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PWRCON_APB = ~((1 << (CLOCKGATE_TIMER - 32)) |
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(1 << (CLOCKGATE_GPIO - 32)));
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#endif
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}
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static void miu_preinit(bool selfrefreshing)
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{
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#if CONFIG_CPU == S5L8702
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if (selfrefreshing)
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MIUCON = 0x11; /* TBC: self-refresh -> IDLE */
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@ -428,74 +484,8 @@ static void miu_preinit(bool selfrefreshing)
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}
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MIUAREF |= 0x61000; /* Auto-refresh enabled */
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}
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#elif defined(IPOD_NANO4G)
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static void syscon_preinit(void)
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{
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int sec_epoch = soc_get_sec_epoch();
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PWRCON(0) = 0x327e5;
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PWRCON(1) = 0xfe2bed6d;
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PWRCON(2) = 0x73;
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PWRCON(3) = 0xff;
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PWRCON(4) = 0xdcf779;
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if (sec_epoch)
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CLKCON0 &= ~CLKCON0_SDR_DISABLE_BIT; // XXX: call this UNK31_BIT?
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else
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CLKCON0 |= CLKCON0_SDR_DISABLE_BIT;
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PLLMODE &= ~PLLMODE_OSCSEL_BIT; /* CG16_SEL_OSC = OSC0 */
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cg16_config(&CG16_SYS, true, CG16_SEL_OSC, 1, 1, 0x0);
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//soc_set_system_divs(1, 1, 1);
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CLKCON1 = 0;
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while (CLKCON1);
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/* stop all PLLs */
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for (int pll = 0; pll < 3; pll++)
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pll_onoff(pll, false);
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PLLUNK3C = 0;
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pll_config(0, PLLOP_DM, sec_epoch ? 6 : 3, 133, 1, 39900);
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pll_onoff(0, true);
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// soc_set_system_divs(1, 2, 1 /*hprat*/);
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// XXX: Without this, SDRAM does not work!
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uint32_t val = 0x404040;
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CLKCON1 = val;
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while (CLKCON1 != val);
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CLKCON0 |= CLKCON0_UNK30_BIT;
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cg16_config(&CG16_SYS, true, CG16_SEL_PLL0, 1, 1, 0x0);
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cg16_config(&CG16_LCD, false, CG16_SEL_OSC, 1, 1, 0x0);
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cg16_config(&CG16_SVID, false, CG16_SEL_OSC, 1, 1, 0x0);
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cg16_config(&CG16_AUD0, false, CG16_SEL_OSC, 1, 1, CG16_UNK14_BIT);
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cg16_config(&CG16_AUD1, false, CG16_SEL_OSC, 1, 1, CG16_UNK14_BIT);
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cg16_config(&CG16_AUD2, false, CG16_SEL_OSC, 1, 1, CG16_UNK14_BIT);
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// TODO: configure a 12 MHz ECLK for all targets, so the timer settings will be the same.
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// cg16_config(&CG16_RTIME, true, CG16_SEL_OSC, (S5L8720_OSC0_HZ / ECLK), 1, 0);
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cg16_config(&CG16_RTIME, true, CG16_SEL_OSC, 1, 1, 0x0);
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cg16_config(&CG16_5L, false, CG16_SEL_OSC, 1, 1, 0x0);
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cg16_config(&CG16_6L, false, CG16_SEL_OSC, 1, 1, 0x0);
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soc_set_hsdiv(1);
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// PWRCON(0) = 0x327e5;
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// PWRCON(1) = 0xfe2bed6d;
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// PWRCON(2) = 0x73;
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// PWRCON(3) = 0xff;
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// PWRCON(4) = 0xdcf779;
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}
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// TODO: There are things wrong, copying from spireader
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static void miu_preinit(bool selfrefreshing)
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{
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#elif CONFIG_CPU == S5L8720
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// TODO: There are things wrong, copying from spireader
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GPIOUNK384 = 0;
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MIU_REG(0) = 1;
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@ -563,14 +553,14 @@ static void miu_preinit(bool selfrefreshing)
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MIU_REG(0x8) = 0x1;
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UNK3E000008 = 0x1f;
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#endif
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}
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#endif /* IPOD_NANO4G */
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/* Preliminary HW initialization */
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void system_preinit(void)
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{
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bool hibernated; // TODO: hibernated -> resuming, or perhaps better warmboot
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#ifdef IPOD_NANO4G
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#if CONFIG_CPU == S5L8720
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uint32_t boot_config;
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/* Read boot configuration on PDAT3:
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@ -587,7 +577,7 @@ void system_preinit(void)
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gpio_preinit();
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i2c_preinit(0);
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#ifdef IPOD_NANO4G
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#if CONFIG_CPU == S5L8720
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/* TBC: store boot config into a PMU memory register */
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pmu_wr(0x7f, boot_config);
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#endif
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