forked from len0rd/rockbox
Give pcm-coldfire.c a much needed shakedown. Fixes FS#9378 - metronome freezes (works for me now on X5 and H120 after running it at 400bpm for an hour or so). The reason seems to have been DMA_INT in DCR should also be cleared when forcing a channel stop. Also fixes a dodgey keyclick without music playing that I was getting on H120.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19991 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
b411f5eee5
commit
ca5ca5b6ef
1 changed files with 159 additions and 161 deletions
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@ -8,6 +8,7 @@
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* $Id$
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*
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* Copyright (C) 2006 by Michael Sevakis
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* Copyright (C) 2005 by Linus Nielsen Feltzing
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -28,45 +29,30 @@
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#include "spdif.h"
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#endif
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#define IIS_PLAY_DEFPARM ( (freq_ent[FPARM_CLOCKSEL] << 12) | \
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(IIS_PLAY & (7 << 8)) | \
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(4 << 2) ) /* 64 bit clocks / word clock */
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#define IIS_FIFO_RESET (1 << 11)
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#define PDIR2_FIFO_RESET (1 << 9)
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#define IIS_PLAY_DEFPARM ( (freq_ent[FPARM_CLOCKSEL] << 12) | \
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(IIS_PLAY & (7 << 8)) | \
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(4 << 2) ) /* 64 bit clocks / word clock */
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#define IIS_FIFO_RESET (1 << 11)
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#define PDIR2_FIFO_RESET (1 << 9)
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#if defined(IAUDIO_X5) || defined(IAUDIO_M5) || defined(IAUDIO_M3)
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#define SET_IIS_PLAY(x) IIS1CONFIG = (x)
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#define IIS_PLAY IIS1CONFIG
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#define IIS_PLAY IIS1CONFIG
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#else
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#define SET_IIS_PLAY(x) IIS2CONFIG = (x)
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#define IIS_PLAY IIS2CONFIG
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#define IIS_PLAY IIS2CONFIG
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#endif
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struct dma_lock
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{
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int locked;
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unsigned long state;
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};
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static bool is_playback_monitoring(void)
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{
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return (IIS_PLAY & (7 << 8)) == (3 << 8);
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}
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static void iis_play_reset_if_playback(bool if_playback)
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{
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bool is_playback = is_playback_monitoring();
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if (is_playback != if_playback)
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return;
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or_l(IIS_FIFO_RESET, &IIS_PLAY);
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}
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#ifdef HAVE_SPDIF_OUT
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/* EBU TX auto sync, PDIR2 fifo auto sync, IIS1 fifo auto sync */
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#define AUDIOGLOB_DEFPARM ((1 << 10) | (1 << 8) | (1 << 7))
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#else
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/* PDIR2 fifo auto sync, IIS1 fifo auto sync */
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#define AUDIOGLOB_DEFPARM ((1 << 8) | (1 << 7))
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#endif
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/** Sample rates **/
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#define PLLCR_SET_AUDIO_BITS_DEFPARM \
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((freq_ent[FPARM_CLSEL] << 28) | (1 << 22))
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/** Sample rates **/
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#define FPARM_CLOCKSEL 0
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#define FPARM_CLSEL 1
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#if CONFIG_CPU == MCF5249 && defined(HAVE_UDA1380)
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@ -91,62 +77,62 @@ static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] =
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static const unsigned char *freq_ent;
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/* apply audio settings */
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static bool _pcm_dma_apply_settings(bool clear_reset)
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/* Lock status struct for playback and recording */
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struct dma_lock
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{
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bool did_reset = false;
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unsigned long iis_play_defparm;
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int locked;
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unsigned long state;
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};
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static void iis_play_reset(void)
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{
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or_l(IIS_FIFO_RESET, &IIS_PLAY);
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and_l(~IIS_FIFO_RESET, &IIS_PLAY);
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PDOR3 = 0;
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}
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static bool is_playback_monitoring(void)
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{
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return (IIS_PLAY & (7 << 8)) == (3 << 8);
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}
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static void iis_play_reset_if_playback(bool if_playback)
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{
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int level = set_irq_level(DMA_IRQ_LEVEL);
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/* remember table entry */
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freq_ent = pcm_freq_parms[pcm_fsel];
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iis_play_defparm = IIS_PLAY_DEFPARM;
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if (pcm_sampr != pcm_curr_sampr)
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{
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/* Reprogramming bits 15-12 requires FIFO to be in a reset
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condition - Users Manual 17-8, Note 11 */
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or_l(IIS_FIFO_RESET, &IIS_PLAY);
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/* Important for TLV320 - this must happen in the correct order
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or starting recording will sound absolutely awful once in
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awhile - audiohw_set_frequency then coldfire_set_pllcr_audio_bits
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*/
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SET_IIS_PLAY(IIS_PLAY_DEFPARM | IIS_FIFO_RESET);
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audiohw_set_frequency(pcm_fsel);
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coldfire_set_pllcr_audio_bits(PLLCR_SET_AUDIO_BITS_DEFPARM);
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did_reset = true;
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}
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/* If a reset was done because of a sample rate change, IIS_PLAY will have
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been set already, so only needs to be set again if the reset flag must
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be cleared. If the frequency didn't change, it was never altered and
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the reset flag can just be removed or no action taken. */
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if (clear_reset)
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SET_IIS_PLAY(IIS_PLAY_DEFPARM & ~IIS_FIFO_RESET);
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if (is_playback_monitoring() == if_playback)
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iis_play_reset();
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restore_irq(level);
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}
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#if 0
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logf("IISPLAY: %08X", IIS_PLAY);
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#endif
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return did_reset;
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} /* _pcm_dma_apply_settings */
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/* apply audio settings */
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/* This clears the reset bit to enable monitoring immediately if monitoring
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recording sources or always if playback is in progress - we might be
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switching samplerates on the fly */
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void pcm_dma_apply_settings(void)
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{
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int level = set_irq_level(DMA_IRQ_LEVEL);
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bool pbm = is_playback_monitoring();
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bool kick = (DCR0 & DMA_EEXT) != 0 && pbm;
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/* Clear reset if not playback monitoring or peripheral request is
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active and playback monitoring */
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if (_pcm_dma_apply_settings(!pbm || kick) && kick)
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/* remember table entry */
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freq_ent = pcm_freq_parms[pcm_fsel];
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/* Reprogramming bits 15-12 requires FIFO to be in a reset
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condition - Users Manual 17-8, Note 11 */
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or_l(IIS_FIFO_RESET, &IIS_PLAY);
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/* Important for TLV320 - this must happen in the correct order
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or starting recording will sound absolutely awful once in
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awhile - audiohw_set_frequency then coldfire_set_pllcr_audio_bits
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*/
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IIS_PLAY = IIS_PLAY_DEFPARM | IIS_FIFO_RESET;
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restore_irq(level);
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audiohw_set_frequency(pcm_fsel);
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coldfire_set_pllcr_audio_bits(PLLCR_SET_AUDIO_BITS_DEFPARM);
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level = set_irq_level(DMA_IRQ_LEVEL);
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IIS_PLAY = IIS_PLAY_DEFPARM;
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if ((DCR0 & DMA_EEXT) != 0 && is_playback_monitoring())
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PDOR3 = 0; /* Kick FIFO out of reset by writing to it */
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restore_irq(level);
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@ -156,24 +142,18 @@ void pcm_play_dma_init(void)
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{
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freq_ent = pcm_freq_parms[pcm_fsel];
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AUDIOGLOB = (1 << 8) /* IIS1 fifo auto sync */
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| (1 << 7) /* PDIR2 fifo auto sync */
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#ifdef HAVE_SPDIF_OUT
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| (1 << 10) /* EBU TX auto sync */
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#endif
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;
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DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */
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AUDIOGLOB = AUDIOGLOB_DEFPARM;
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DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */
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and_l(0xffffff00, &DMAROUTE);
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or_l(DMA0_REQ_AUDIO_1, &DMAROUTE);
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DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
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/* Call pcm_play_dma_stop to initialize everything. */
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pcm_play_dma_stop();
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DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
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BCR0 = 0; /* No bytes waiting */
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ICR6 = (6 << 2); /* Enable interrupt at level 6, priority 0 */
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/* Setup Coldfire I2S before initializing hardware or changing
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other settings. */
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or_l(IIS_FIFO_RESET, &IIS_PLAY);
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SET_IIS_PLAY(IIS_PLAY_DEFPARM | IIS_FIFO_RESET);
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IIS_PLAY = IIS_PLAY_DEFPARM | IIS_FIFO_RESET;
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audio_set_output_source(AUDIO_SRC_PLAYBACK);
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/* Initialize default register values. */
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@ -187,13 +167,12 @@ void pcm_play_dma_init(void)
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#if defined(HAVE_SPDIF_REC) || defined(HAVE_SPDIF_OUT)
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spdif_init();
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#endif
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/* Enable interrupt at level 6, priority 0 */
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ICR6 = (6 << 2);
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} /* pcm_play_dma_init */
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void pcm_postinit(void)
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{
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audiohw_postinit();
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iis_play_reset();
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}
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/** DMA **/
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@ -225,22 +204,22 @@ void pcm_play_unlock(void)
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/* Set up the DMA transfer that kicks in when the audio FIFO gets empty */
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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logf("pcm_play_dma_start");
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/* Stop any DMA in progress */
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pcm_play_dma_stop();
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/* stop any DMA in progress */
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DSR0 = 1;
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DCR0 = 0;
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addr = (void *)(((long)addr + 3) & ~3);
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size &= ~3;
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if (size <= 0)
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return;
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/* Set up DMA transfer */
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SAR0 = (unsigned long)addr; /* Source address */
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DAR0 = (unsigned long)&PDOR3; /* Destination address */
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BCR0 = (unsigned long)size; /* Bytes to transfer */
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/* Enable the FIFO and force one write to it */
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_pcm_dma_apply_settings(is_playback_monitoring());
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DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA |
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DMA_SINC | DMA_SSIZE(DMA_SIZE_LINE) | DMA_START;
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DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA | DMA_SINC |
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DMA_SSIZE(DMA_SIZE_LINE) | DMA_START;
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dma_play_lock.state = (1 << 14);
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} /* pcm_play_dma_start */
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@ -248,12 +227,10 @@ void pcm_play_dma_start(const void *addr, size_t size)
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/* Stops the DMA transfer and interrupt */
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void pcm_play_dma_stop(void)
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{
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DSR0 = 1;
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DCR0 = 0;
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BCR0 = 0;
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and_l(~(DMA_EEXT | DMA_INT), &DCR0); /* per request and int OFF */
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BCR0 = 0; /* No bytes remaining */
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DSR0 = 1; /* Clear interrupt, errors, stop transfer */
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/* Place TX FIFO in reset condition if playback monitoring is on.
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Recording monitoring something else should not be stopped. */
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iis_play_reset_if_playback(true);
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dma_play_lock.state = (0 << 14);
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@ -264,16 +241,16 @@ void pcm_play_dma_pause(bool pause)
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if (pause)
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{
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/* pause playback on current buffer */
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and_l(~DMA_EEXT, &DCR0);
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and_l(~(DMA_EEXT | DMA_INT), &DCR0); /* per request and int OFF */
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DSR0 = 1; /* stop channel */
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iis_play_reset_if_playback(true);
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dma_play_lock.state = (0 << 14);
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}
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else
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{
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/* restart playback on current buffer */
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/* Enable the FIFO and force one write to it */
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_pcm_dma_apply_settings(is_playback_monitoring());
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or_l(DMA_EEXT | DMA_START, &DCR0);
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iis_play_reset_if_playback(true);
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or_l(DMA_INT | DMA_EEXT | DMA_START, &DCR0); /* everything ON */
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dma_play_lock.state = (1 << 14);
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}
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} /* pcm_play_dma_pause */
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@ -288,38 +265,14 @@ size_t pcm_get_bytes_waiting(void)
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void DMA0(void) __attribute__ ((interrupt_handler, section(".icode")));
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void DMA0(void)
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{
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int res = DSR0;
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unsigned long res = DSR0;
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DSR0 = 1; /* Clear interrupt */
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and_l(~DMA_EEXT, &DCR0); /* Disable peripheral request */
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/* Stop on error */
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if ((res & 0x70) == 0)
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{
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pcm_more_callback_type get_more = pcm_callback_for_more;
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unsigned char *next_start;
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size_t next_size = 0;
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if (get_more)
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get_more(&next_start, &next_size);
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if (next_size > 0)
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{
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SAR0 = (unsigned long)next_start; /* Source address */
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BCR0 = next_size; /* Bytes to transfer */
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or_l(DMA_EEXT, &DCR0); /* Enable peripheral request */
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return;
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}
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else
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{
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/* Finished playing */
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#if 0
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/* int. logfs can trash the display */
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logf("DMA0 No Data:0x%04x", res);
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#endif
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}
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}
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else
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and_l(~(DMA_EEXT | DMA_INT), &DCR0); /* per request and int OFF */
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DSR0 = 1; /* Clear interrupt and errors */
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if (res & 0x70)
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{
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/* Stop on error */
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logf("DMA0 err: %02x", res);
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#if 0
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logf(" SAR0: %08x", SAR0);
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@ -328,6 +281,27 @@ void DMA0(void)
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logf(" DCR0: %08x", DCR0);
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#endif
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}
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else
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{
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pcm_more_callback_type get_more = pcm_callback_for_more;
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unsigned char *start;
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size_t size = 0;
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if (get_more)
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get_more(&start, &size);
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start = (unsigned char *)(((long)start + 3) & ~3);
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size &= ~3;
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if (size > 0)
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{
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SAR0 = (unsigned long)start; /* Source address */
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BCR0 = size; /* Bytes to transfer */
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or_l(DMA_EEXT | DMA_INT, &DCR0); /* per request and int ON */
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return;
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}
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/* Finished playing */
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}
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/* Stop interrupt and futher transfers */
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pcm_play_dma_stop();
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@ -337,8 +311,15 @@ void DMA0(void)
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const void * pcm_play_dma_get_peak_buffer(int *count)
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{
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unsigned long addr = SAR0;
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int cnt = BCR0;
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unsigned long addr, cnt;
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/* Make sure interrupt doesn't change the second value after we read the
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* first value. */
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int level = set_irq_level(DMA_IRQ_LEVEL);
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addr = SAR0;
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cnt = BCR0;
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restore_irq(level);
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*count = (cnt & 0xffffff) >> 2;
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return (void *)((addr + 2) & ~3);
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} /* pcm_play_dma_get_peak_buffer */
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@ -370,13 +351,15 @@ void pcm_rec_unlock(void)
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void pcm_rec_dma_start(void *addr, size_t size)
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{
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/* stop any DMA in progress */
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and_l(~DMA_EEXT, &DCR1);
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DSR1 = 1;
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pcm_rec_dma_stop();
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addr = (void *)(((long)addr + 3) & ~3);
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size &= ~3;
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if (size <= 0)
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return;
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and_l(~PDIR2_FIFO_RESET, &DATAINCONTROL);
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/* Clear TX FIFO reset bit if the source is not set to monitor playback
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otherwise maintain independence between playback and recording. */
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_pcm_dma_apply_settings(!is_playback_monitoring());
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/* Start the DMA transfer.. */
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#ifdef HAVE_SPDIF_REC
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@ -384,10 +367,10 @@ void pcm_rec_dma_start(void *addr, size_t size)
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INTERRUPTCLEAR = (1 << 25) | (1 << 24) | (1 << 23) | (1 << 22);
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#endif
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SAR1 = (unsigned long)&PDIR2; /* Source address */
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pcm_rec_peak_addr = (unsigned long *)addr; /* Start peaking at dest */
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DAR1 = (unsigned long)addr; /* Destination address */
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BCR1 = (unsigned long)size; /* Bytes to transfer */
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SAR1 = (unsigned long)&PDIR2; /* Source address */
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DAR1 = (unsigned long)addr; /* Destination address */
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BCR1 = (unsigned long)size; /* Bytes to transfer */
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DCR1 = DMA_INT | DMA_EEXT | DMA_CS | DMA_AA | DMA_DINC |
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DMA_DSIZE(DMA_SIZE_LINE) | DMA_START;
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@ -397,9 +380,10 @@ void pcm_rec_dma_start(void *addr, size_t size)
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void pcm_rec_dma_stop(void)
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{
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DSR1 = 1; /* Clear interrupt */
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DCR1 = 0;
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BCR1 = 0;
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and_l(~(DMA_EEXT | DMA_INT), &DCR1); /* per request and int OFF */
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DSR1 = 1; /* Clear interrupt, errors, stop transfer */
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BCR1 = 0; /* No bytes received */
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or_l(PDIR2_FIFO_RESET, &DATAINCONTROL);
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iis_play_reset_if_playback(false);
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@ -422,6 +406,8 @@ void pcm_rec_dma_init(void)
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void pcm_rec_dma_close(void)
|
||||
{
|
||||
pcm_rec_dma_stop();
|
||||
|
||||
and_l(0xffff00ff, &DMAROUTE);
|
||||
ICR7 = 0x00; /* Disable interrupt */
|
||||
dma_rec_lock.state = (0 << 15);
|
||||
|
|
@ -432,12 +418,12 @@ void pcm_rec_dma_close(void)
|
|||
void DMA1(void) __attribute__ ((interrupt_handler, section(".icode")));
|
||||
void DMA1(void)
|
||||
{
|
||||
int res = DSR1;
|
||||
unsigned long res = DSR1;
|
||||
int status = 0;
|
||||
pcm_more_callback_type2 more_ready;
|
||||
|
||||
DSR1 = 1; /* Clear interrupt */
|
||||
and_l(~DMA_EEXT, &DCR1); /* Disable peripheral request */
|
||||
and_l(~(DMA_EEXT | DMA_INT), &DCR1); /* per request and int OFF */
|
||||
DSR1 = 1; /* Clear interrupt and errors */
|
||||
|
||||
if (res & 0x70)
|
||||
{
|
||||
|
|
@ -468,10 +454,6 @@ void DMA1(void)
|
|||
if (more_ready != NULL && more_ready(status) >= 0)
|
||||
return;
|
||||
|
||||
#if 0
|
||||
/* int. logfs can trash the display */
|
||||
logf("DMA1 done:%04x %d", res, status);
|
||||
#endif
|
||||
/* Finished recording */
|
||||
pcm_rec_dma_stop();
|
||||
/* Inform PCM that we're done */
|
||||
|
|
@ -481,16 +463,32 @@ void DMA1(void)
|
|||
/* Continue transferring data in - call from interrupt callback */
|
||||
void pcm_record_more(void *start, size_t size)
|
||||
{
|
||||
start = (void *)(((long)start + 3) & ~3);
|
||||
size &= ~3;
|
||||
|
||||
if (size <= 0)
|
||||
{
|
||||
pcm_rec_dma_stop();
|
||||
return;
|
||||
}
|
||||
|
||||
pcm_rec_peak_addr = (unsigned long *)start; /* Start peaking at dest */
|
||||
DAR1 = (unsigned long)start; /* Destination address */
|
||||
BCR1 = (unsigned long)size; /* Bytes to transfer */
|
||||
or_l(DMA_EEXT, &DCR1); /* Enable peripheral request */
|
||||
DAR1 = (unsigned long)start; /* Destination address */
|
||||
BCR1 = (unsigned long)size; /* Bytes to transfer */
|
||||
or_l(DMA_EEXT | DMA_INT, &DCR1); /* per request and int ON */
|
||||
} /* pcm_record_more */
|
||||
|
||||
const void * pcm_rec_dma_get_peak_buffer(int *count)
|
||||
{
|
||||
unsigned long addr = (unsigned long)pcm_rec_peak_addr;
|
||||
unsigned long end = DAR1;
|
||||
unsigned long addr, end;
|
||||
|
||||
/* Make sure interrupt doesn't change the second value after we read the
|
||||
* first value. */
|
||||
int level = set_irq_level(DMA_IRQ_LEVEL);
|
||||
addr = (unsigned long)pcm_rec_peak_addr;
|
||||
end = DAR1;
|
||||
restore_irq(level);
|
||||
|
||||
addr >>= 2;
|
||||
*count = (end >> 2) - addr;
|
||||
return (void *)(addr << 2);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue