forked from len0rd/rockbox
usb-s3c6400: merge the 2 drivers
Player-specific code remaining: usb_drv_(init,exit)
The iPods lack a MMU, so:
- physical, virtual, and uncached addresses are identical
- since we can't access uncached memory we discard caches when receiving data
Still not quite reliable on nano2g
Change-Id: Iebb79df64818b9ae3b68eccb8be8975ebd6c21ea
This commit is contained in:
Rafaël Carré
parent
c1a71ab9ae
commit
c9c1349773
4 changed files with 185 additions and 398 deletions
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@ -239,7 +239,7 @@
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#define CONFIG_USBOTG USBOTG_S3C6400X
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#define USB_VENDOR_ID 0x05AC
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#define USB_PRODUCT_ID 0x1261
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#define USB_NUM_ENDPOINTS 5
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#define USB_NUM_ENDPOINTS 6
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#define USE_ROCKBOX_USB
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#define USB_DEVBSS_ATTR __attribute__((aligned(16)))
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@ -227,7 +227,7 @@
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#define CONFIG_USBOTG USBOTG_S3C6400X
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#define USB_VENDOR_ID 0x05AC
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#define USB_PRODUCT_ID 0x1260
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#define USB_NUM_ENDPOINTS 5
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#define USB_NUM_ENDPOINTS 6
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#define USE_ROCKBOX_USB
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#define USB_DEVBSS_ATTR __attribute__((aligned(16)))
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@ -57,7 +57,7 @@ void fiq_handler(void) __attribute__((interrupt ("FIQ")));
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default_interrupt(INT_WATCHDOG);
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default_interrupt(INT_TIMER1);
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default_interrupt(INT_TIMER2);
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default_interrupt(INT_USB);
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default_interrupt(INT_USB_FUNC);
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default_interrupt(INT_DMAC);
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default_interrupt(INT_NAND);
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default_interrupt(INT_IDE);
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@ -134,7 +134,7 @@ static const struct { int source; void (*isr) (void); } vec_int_srcs[] =
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#if (defined HAVE_MULTIDRIVE && CONFIG_CPU == AS3525)
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{ INT_SRC_MCI0, INT_MCI0 },
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#endif
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{ INT_SRC_USB, INT_USB, },
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{ INT_SRC_USB, INT_USB_FUNC, },
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{ INT_SRC_TIMER1, INT_TIMER1 },
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{ INT_SRC_TIMER2, INT_TIMER2 },
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{ INT_SRC_I2C_AUDIO, INT_I2C_AUDIO },
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@ -39,6 +39,16 @@
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//#define LOGF_ENABLE
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#include "logf.h"
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#if CONFIG_CPU == AS3525v2
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#define UNCACHED_ADDR AS3525_UNCACHED_ADDR
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#define PHYSICAL_ADDR AS3525_PHYSICAL_ADDR
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static inline void discard_dma_buffer_cache(void) {}
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#else
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#define UNCACHED_ADDR
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#define PHYSICAL_ADDR
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static inline void discard_dma_buffer_cache(void) { commit_discard_dcache(); }
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#endif
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/* store per endpoint, per direction, information */
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struct ep_type
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{
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@ -50,6 +60,46 @@ struct ep_type
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bool busy; /* true is a transfer is pending */
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};
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static const uint8_t in_ep_list[] = {0, 1, 3, 5};
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static const uint8_t out_ep_list[] = {0, 2, 4};
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/* state of EP0 (to correctly schedule setup packet enqueing) */
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enum ep0state
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{
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/* Setup packet is enqueud, waiting for actual data */
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EP0_WAIT_SETUP = 0,
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/* Waiting for ack (either IN or OUT) */
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EP0_WAIT_ACK = 1,
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/* Ack complete, waiting for data (either IN or OUT)
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* This state is necessary because if both ack and data complete in the
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* same interrupt, we might process data completion before ack completion
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* so we need this bizarre state */
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EP0_WAIT_DATA = 2,
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/* Setup packet complete, waiting for ack and data */
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EP0_WAIT_DATA_ACK = 3,
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};
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/* endpoints[ep_num][DIR_IN/DIR_OUT] */
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static struct ep_type endpoints[USB_NUM_ENDPOINTS][2];
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/* setup packet for EP0 */
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/* USB control requests may be up to 64 bytes in size.
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Even though we never use anything more than the 8 header bytes,
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we are required to accept request packets of up to 64 bytes size.
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Provide buffer space for these additional payload bytes so that
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e.g. write descriptor requests (which are rejected by us, but the
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payload is transferred anyway) do not cause memory corruption.
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Fixes FS#12310. -- Michael Sparmann (theseven) */
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static union {
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struct usb_ctrlrequest header; /* 8 bytes */
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unsigned char payload[64];
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} _ep0_setup_pkt USB_DEVBSS_ATTR;
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static struct usb_ctrlrequest *ep0_setup_pkt = UNCACHED_ADDR(&_ep0_setup_pkt.header);
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/* state of EP0 */
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static enum ep0state ep0_state;
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bool usb_drv_stalled(int endpoint, bool in)
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{
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return DEPCTL(endpoint, !in) & DEPCTL_stall;
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@ -72,7 +122,40 @@ void usb_drv_set_address(int address)
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into the USB core, which will then call this dummy function. */
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}
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static void ep_transfer(int ep, void *ptr, int length, bool out);
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static void ep_transfer(int ep, void *ptr, int len, bool out)
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{
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/* disable interrupts to avoid any race */
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int oldlevel = disable_irq_save();
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struct ep_type *endpoint = &endpoints[ep][out ? DIR_OUT : DIR_IN];
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endpoint->busy = true;
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endpoint->size = len;
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endpoint->status = -1;
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if (out)
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DEPCTL(ep, out) &= ~DEPCTL_stall;
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int mps = usb_drv_port_speed() ? 512 : 64;
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int nb_packets = (len + mps - 1) / mps;
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if (nb_packets == 0)
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nb_packets = 1;
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DEPDMA(ep, out) = len ? (void*)PHYSICAL_ADDR(ptr) : NULL;
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DEPTSIZ(ep, out) = (nb_packets << DEPTSIZ_pkcnt_bitp) | len;
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if(out)
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discard_dcache_range(ptr, len);
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else
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commit_dcache_range(ptr, len);
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logf("pkt=%d dma=%lx", nb_packets, DEPDMA(ep, out));
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// if (!out) while (((GNPTXSTS & 0xffff) << 2) < MIN(mps, length));
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DEPCTL(ep, out) |= DEPCTL_epena | DEPCTL_cnak;
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restore_irq(oldlevel);
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}
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int usb_drv_send_nonblocking(int endpoint, void *ptr, int length)
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{
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ep_transfer(EP_NUM(endpoint), ptr, length, false);
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@ -109,55 +192,15 @@ void usb_drv_set_test_mode(int mode)
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DCTL = (DCTL & ~bitm(DCTL, tstctl)) | (mode << DCTL_tstctl_bitp);
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}
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#if CONFIG_CPU == AS3525v2 /* FIXME FIXME FIXME */
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static const uint8_t in_ep_list[] = {0, 1, 3, 5};
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static const uint8_t out_ep_list[] = {0, 2, 4};
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/* state of EP0 (to correctly schedule setup packet enqueing) */
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enum ep0state
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{
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/* Setup packet is enqueud, waiting for actual data */
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EP0_WAIT_SETUP = 0,
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/* Waiting for ack (either IN or OUT) */
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EP0_WAIT_ACK = 1,
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/* Ack complete, waiting for data (either IN or OUT)
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* This state is necessary because if both ack and data complete in the
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* same interrupt, we might process data completion before ack completion
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* so we need this bizarre state */
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EP0_WAIT_DATA = 2,
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/* Setup packet complete, waiting for ack and data */
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EP0_WAIT_DATA_ACK = 3,
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};
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/* endpoints[ep_num][DIR_IN/DIR_OUT] */
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static struct ep_type endpoints[USB_NUM_ENDPOINTS][2];
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/* setup packet for EP0 */
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/* USB control requests may be up to 64 bytes in size.
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Even though we never use anything more than the 8 header bytes,
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we are required to accept request packets of up to 64 bytes size.
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Provide buffer space for these additional payload bytes so that
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e.g. write descriptor requests (which are rejected by us, but the
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payload is transferred anyway) do not cause memory corruption.
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Fixes FS#12310. -- Michael Sparmann (theseven) */
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static union {
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struct usb_ctrlrequest header; /* 8 bytes */
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unsigned char payload[64];
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} _ep0_setup_pkt USB_DEVBSS_ATTR;
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static struct usb_ctrlrequest *ep0_setup_pkt = AS3525_UNCACHED_ADDR(&_ep0_setup_pkt.header);
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/* state of EP0 */
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static enum ep0state ep0_state;
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void usb_attach(void)
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{
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usb_enable(true); // s5l only ?
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/* Nothing to do */
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}
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static void prepare_setup_ep0(void)
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{
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DEPDMA(0, true) = (void*)AS3525_PHYSICAL_ADDR(&_ep0_setup_pkt);
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DEPDMA(0, true) = (void*)PHYSICAL_ADDR(&_ep0_setup_pkt);
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DEPTSIZ(0, true) = (1 << DEPTSIZ0_supcnt_bitp)
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| (1 << DEPTSIZ0_pkcnt_bitp)
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| 8;
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@ -183,7 +226,7 @@ static void reset_endpoints(void)
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endpoint->active = false;
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endpoint->busy = false;
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endpoint->status = -1;
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endpoint->done = false;
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endpoint->done = true;
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semaphore_release(&endpoint->complete);
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if (i != 0)
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@ -222,6 +265,7 @@ static void cancel_all_transfers(bool cancel_ep0)
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restore_irq(flags);
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}
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#if CONFIG_CPU == AS3525v2
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void usb_drv_init(void)
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{
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for (int i = 0; i < USB_NUM_ENDPOINTS; i++)
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@ -311,10 +355,89 @@ void usb_drv_exit(void)
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CGU_USB = 0;
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bitclr32(&CGU_PERI, CGU_USB_CLOCK_ENABLE);
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}
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#elif CONFIG_CPU == S5L8701 || CONFIG_CPU == S5L8702
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static void usb_reset(void)
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{
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DCTL = DCTL_pwronprgdone | DCTL_sftdiscon;
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OPHYPWR = 0; /* PHY: Power up */
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udelay(10);
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OPHYUNK1 = 1;
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OPHYUNK2 = 0xE3F;
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ORSTCON = 1; /* PHY: Assert Software Reset */
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udelay(10);
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ORSTCON = 0; /* PHY: Deassert Software Reset */
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OPHYUNK3 = 0x600;
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OPHYCLK = SYNOPSYSOTG_CLOCK;
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udelay(400);
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GRSTCTL = GRSTCTL_csftrst; /* OTG: Assert Software Reset */
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while (GRSTCTL & GRSTCTL_csftrst); /* Wait for OTG to ack reset */
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while (!(GRSTCTL & GRSTCTL_ahbidle)); /* Wait for OTG AHB master idle */
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GRXFSIZ = 1024;
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GNPTXFSIZ = (256 << 16) | 1024;
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GAHBCFG = SYNOPSYSOTG_AHBCFG;
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GUSBCFG = (1 << 12) | (1 << 10) | GUSBCFG_phy_if; /* OTG: 16bit PHY and some reserved bits */
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DCFG = DCFG_nzstsouthshk; /* Address 0 */
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DCTL = DCTL_pwronprgdone; /* Soft Reconnect */
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DIEPMSK = DIEPINT_timeout | DEPINT_ahberr | DEPINT_xfercompl;
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DOEPMSK = DOEPINT_setup | DEPINT_ahberr | DEPINT_xfercompl;
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DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all endpoints */
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GINTMSK = GINTMSK_outepintr | GINTMSK_inepintr | GINTMSK_usbreset | GINTMSK_enumdone;
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reset_endpoints();
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}
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void usb_drv_init(void)
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{
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for (unsigned i = 0; i < sizeof(endpoints)/(2*sizeof(struct ep_type)); i++)
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for (unsigned dir = 0; dir < 2; dir++)
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semaphore_init(&endpoints[i][dir].complete, 1, 0);
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/* Enable USB clock */
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#if CONFIG_CPU==S5L8701
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PWRCON &= ~0x4000;
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PWRCONEXT &= ~0x800;
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INTMSK |= INTMSK_USB_OTG;
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#elif CONFIG_CPU==S5L8702
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PWRCON(0) &= ~0x4;
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PWRCON(1) &= ~0x8;
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VIC0INTENABLE |= 1 << 19;
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#endif
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PCGCCTL = 0;
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/* reset the beast */
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usb_reset();
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}
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void usb_drv_exit(void)
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{
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DCTL = DCTL_pwronprgdone | DCTL_sftdiscon;
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OPHYPWR = 0xF; /* PHY: Power down */
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udelay(10);
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ORSTCON = 7; /* Put the PHY into reset (needed to get current down) */
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udelay(10);
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PCGCCTL = 1; /* Shut down PHY clock */
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#if CONFIG_CPU==S5L8701
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PWRCON |= 0x4000;
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PWRCONEXT |= 0x800;
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#elif CONFIG_CPU==S5L8702
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PWRCON(0) |= 0x4;
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PWRCON(1) |= 0x8;
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#endif
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}
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#endif
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static void handle_ep_int(int ep, bool out)
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{
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unsigned long sts = DEPINT(ep, out);
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struct ep_type *endpoint = &endpoints[ep][out ? DIR_OUT : DIR_IN];
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logf("%s(%d %s): sts = 0x%lx", __func__, ep, out?"OUT":"IN", sts);
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if(sts & DEPINT_ahberr)
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@ -322,7 +445,7 @@ static void handle_ep_int(int ep, bool out)
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if(sts & DEPINT_xfercompl)
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{
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struct ep_type *endpoint = &endpoints[ep][out ? DIR_OUT : DIR_IN];
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discard_dma_buffer_cache();
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if(endpoint->busy)
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{
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endpoint->busy = false;
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@ -357,11 +480,19 @@ static void handle_ep_int(int ep, bool out)
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}
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}
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if(!out && (sts & DIEPINT_timeout))
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panicf("usb-drv: timeout on EP%d IN", ep);
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if(!out && (sts & DIEPINT_timeout)) {
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if (endpoint->busy)
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{
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endpoint->busy = false;
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endpoint->status = 1;
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endpoint->done = true;
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semaphore_release(&endpoint->complete);
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}
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}
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if(out && (sts & DOEPINT_setup))
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{
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discard_dma_buffer_cache();
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if(ep != 0)
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panicf("usb-drv: setup not on EP0, this is impossible");
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if((DEPTSIZ(ep, true) & DEPTSIZ_xfersize_bits) != 0)
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@ -390,7 +521,7 @@ static void handle_ep_int(int ep, bool out)
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DEPINT(ep, out) = sts;
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}
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void INT_USB(void)
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void INT_USB_FUNC(void)
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{
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/* some bits in GINTSTS can be set even though we didn't enable the interrupt source
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* so AND it with the actual mask */
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@ -461,6 +592,8 @@ int usb_drv_request_endpoint(int type, int dir)
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void usb_drv_release_endpoint(int ep)
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{
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if ((ep & 0x7f) == 0)
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return;
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endpoints[EP_NUM(ep)][EP_DIR(ep)].active = false;
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}
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@ -469,39 +602,6 @@ void usb_drv_cancel_all_transfers()
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cancel_all_transfers(false);
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}
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static void ep_transfer(int ep, void *ptr, int len, bool out)
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{
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/* disable interrupts to avoid any race */
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int oldlevel = disable_irq_save();
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struct ep_type *endpoint = &endpoints[ep][out ? DIR_OUT : DIR_IN];
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endpoint->busy = true;
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endpoint->size = len;
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endpoint->status = -1;
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if (out)
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DEPCTL(ep, out) &= ~DEPCTL_stall;
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int mps = usb_drv_port_speed() ? 512 : 64;
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int nb_packets = (len + mps - 1) / mps;
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if (nb_packets == 0)
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nb_packets = 1;
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DEPDMA(ep, out) = len ? (void*)AS3525_PHYSICAL_ADDR(ptr) : NULL;
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DEPTSIZ(ep, out) = (nb_packets << DEPTSIZ_pkcnt_bitp) | len;
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if(out)
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discard_dcache_range(ptr, len);
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else
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commit_dcache_range(ptr, len);
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logf("pkt=%d dma=%lx", nb_packets, DEPDMA(ep, out));
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// if (!out) while (((GNPTXSTS & 0xffff) << 2) < MIN(mps, length));
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DEPCTL(ep, out) |= DEPCTL_epena | DEPCTL_cnak;
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restore_irq(oldlevel);
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}
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int usb_drv_send(int ep, void *ptr, int len)
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{
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@ -513,316 +613,3 @@ int usb_drv_send(int ep, void *ptr, int len)
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semaphore_wait(&endpoint->complete, TIMEOUT_BLOCK);
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return endpoint->status;
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}
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#else
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static struct ep_type endpoints[USB_NUM_ENDPOINTS][2];
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/* USB control requests may be up to 64 bytes in size.
|
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Even though we never use anything more than the 8 header bytes,
|
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we are required to accept request packets of up to 64 bytes size.
|
||||
Provide buffer space for these additional payload bytes so that
|
||||
e.g. write descriptor requests (which are rejected by us, but the
|
||||
payload is transferred anyway) do not cause memory corruption.
|
||||
Fixes FS#12310. -- Michael Sparmann (theseven) */
|
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static union
|
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{
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struct usb_ctrlrequest header; /* 8 bytes */
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unsigned char payload[64];
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} ctrlreq USB_DEVBSS_ATTR;
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static volatile bool inflight = false;
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static volatile bool plugged = false;
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static void reset_endpoints(int reinit)
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{
|
||||
for (unsigned i = 0; i < sizeof(endpoints)/(2*sizeof(struct ep_type)); i++)
|
||||
for (unsigned dir = 0; dir < 2; dir++)
|
||||
{
|
||||
if (reinit) endpoints[i][dir].active = false;
|
||||
endpoints[i][dir].busy = false;
|
||||
endpoints[i][dir].status = -1;
|
||||
endpoints[i][dir].done = true;
|
||||
semaphore_release(&endpoints[i][dir].complete);
|
||||
}
|
||||
|
||||
DEPCTL(0, false) = DEPCTL_usbactep | (1 << DEPCTL_nextep_bitp);
|
||||
DEPCTL(0, true) = DEPCTL_usbactep;
|
||||
DEPTSIZ(0, true) = (1 << DEPTSIZ_pkcnt_bitp) | (1 << DEPTSIZ0_supcnt_bitp) | 64;
|
||||
|
||||
DEPDMA(0, true) = &ctrlreq;
|
||||
DEPCTL(0, true) |= DEPCTL_epena | DEPCTL_cnak;
|
||||
/* HACK: Enable all endpoints here, because we have no other chance to do it */
|
||||
if (reinit)
|
||||
{
|
||||
/* The size is getting set to zero, because we don't know
|
||||
whether we are Full Speed or High Speed at this stage */
|
||||
DEPCTL(1, false) = DEPCTL_usbactep | DEPCTL_setd0pid | (3 << DEPCTL_nextep_bitp);
|
||||
DEPCTL(2, true) = DEPCTL_usbactep | DEPCTL_setd0pid;
|
||||
DEPCTL(3, false) = DEPCTL_usbactep | DEPCTL_setd0pid | (0 << DEPCTL_nextep_bitp);
|
||||
DEPCTL(4, true) = DEPCTL_usbactep | DEPCTL_setd0pid;
|
||||
}
|
||||
else
|
||||
{
|
||||
DEPCTL(1, false) = DEPCTL(1, false) | DEPCTL_usbactep | DEPCTL_setd0pid;
|
||||
DEPCTL(2, true) = DEPCTL(2, true) | DEPCTL_usbactep | DEPCTL_setd0pid;
|
||||
DEPCTL(3, false) = DEPCTL(3, false) | DEPCTL_usbactep | DEPCTL_setd0pid;
|
||||
DEPCTL(4, true) = DEPCTL(4, true) | DEPCTL_usbactep | DEPCTL_setd0pid;
|
||||
}
|
||||
DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all EPs */
|
||||
inflight = false;
|
||||
}
|
||||
|
||||
int usb_drv_request_endpoint(int type, int dir)
|
||||
{
|
||||
bool out = dir == USB_DIR_OUT;
|
||||
for(size_t ep = out ? 2 : 1; ep < USB_NUM_ENDPOINTS; ep += 2) {
|
||||
if (!endpoints[ep][out ? DIR_OUT : DIR_IN].active)
|
||||
{
|
||||
endpoints[ep][out ? DIR_OUT : DIR_IN].active = true;
|
||||
DEPCTL(ep, out) = (DEPCTL(ep, out) & ~(DEPCTL_eptype_bits << DEPCTL_eptype_bitp)) |
|
||||
(type << DEPCTL_eptype_bitp);
|
||||
return ep | dir;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
void usb_drv_release_endpoint(int ep)
|
||||
{
|
||||
bool out = !(ep & USB_DIR_IN);
|
||||
ep = ep & 0x7f;
|
||||
|
||||
if (ep < 1 || ep > USB_NUM_ENDPOINTS)
|
||||
return;
|
||||
|
||||
endpoints[ep][out ? DIR_OUT : DIR_IN].active = false;
|
||||
}
|
||||
|
||||
static void usb_reset(void)
|
||||
{
|
||||
DCTL = DCTL_pwronprgdone | DCTL_sftdiscon;
|
||||
|
||||
OPHYPWR = 0; /* PHY: Power up */
|
||||
udelay(10);
|
||||
OPHYUNK1 = 1;
|
||||
OPHYUNK2 = 0xE3F;
|
||||
ORSTCON = 1; /* PHY: Assert Software Reset */
|
||||
udelay(10);
|
||||
ORSTCON = 0; /* PHY: Deassert Software Reset */
|
||||
OPHYUNK3 = 0x600;
|
||||
OPHYCLK = SYNOPSYSOTG_CLOCK;
|
||||
udelay(400);
|
||||
|
||||
GRSTCTL = GRSTCTL_csftrst; /* OTG: Assert Software Reset */
|
||||
while (GRSTCTL & GRSTCTL_csftrst); /* Wait for OTG to ack reset */
|
||||
while (!(GRSTCTL & GRSTCTL_ahbidle)); /* Wait for OTG AHB master idle */
|
||||
|
||||
GRXFSIZ = 1024;
|
||||
GNPTXFSIZ = (256 << 16) | 1024;
|
||||
|
||||
GAHBCFG = SYNOPSYSOTG_AHBCFG;
|
||||
GUSBCFG = (1 << 12) | (1 << 10) | GUSBCFG_phy_if; /* OTG: 16bit PHY and some reserved bits */
|
||||
|
||||
DCFG = DCFG_nzstsouthshk; /* Address 0 */
|
||||
DCTL = DCTL_pwronprgdone; /* Soft Reconnect */
|
||||
DIEPMSK = DIEPINT_timeout | DEPINT_ahberr | DEPINT_xfercompl;
|
||||
DOEPMSK = DOEPINT_setup | DEPINT_ahberr | DEPINT_xfercompl;
|
||||
DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all endpoints */
|
||||
GINTMSK = GINTMSK_outepintr | GINTMSK_inepintr | GINTMSK_usbreset | GINTMSK_enumdone;
|
||||
|
||||
reset_endpoints(1);
|
||||
}
|
||||
|
||||
static void handle_ep_int(bool out)
|
||||
{
|
||||
static const uint8_t eps[2][3] = { /* IN */ {0, 1, 3}, /* OUT */ {0, 2, 4}};
|
||||
for (int i = 0; i < 3; i++)
|
||||
{
|
||||
int ep = eps[!!out][i];
|
||||
uint32_t epints = DEPINT(ep, out);
|
||||
if (!epints)
|
||||
continue;
|
||||
|
||||
if (epints & DEPINT_xfercompl)
|
||||
{
|
||||
if (!out) inflight = false;
|
||||
commit_discard_dcache();
|
||||
int bytes = endpoints[ep][out ? DIR_OUT : DIR_IN].size - (DEPTSIZ(ep, out) & (DEPTSIZ_xfersize_bits < DEPTSIZ_xfersize_bitp));
|
||||
if (endpoints[ep][out ? DIR_OUT : DIR_IN].busy)
|
||||
{
|
||||
endpoints[ep][out ? DIR_OUT : DIR_IN].busy = false;
|
||||
endpoints[ep][out ? DIR_OUT : DIR_IN].status = 0;
|
||||
endpoints[ep][out ? DIR_OUT : DIR_IN].done = true;
|
||||
usb_core_transfer_complete(ep, out ? USB_DIR_OUT : USB_DIR_IN, 0, bytes);
|
||||
semaphore_release(&endpoints[ep][out ? DIR_OUT : DIR_IN].complete);
|
||||
}
|
||||
}
|
||||
|
||||
if (epints & DEPINT_ahberr)
|
||||
panicf("USB: AHB error on EP%d (dir %d)", ep, out);
|
||||
|
||||
if (!out && (epints & DIEPINT_timeout))
|
||||
{
|
||||
if (endpoints[ep][out ? DIR_OUT : DIR_IN].busy)
|
||||
{
|
||||
endpoints[ep][out ? DIR_OUT : DIR_IN].busy = false;
|
||||
endpoints[ep][out ? DIR_OUT : DIR_IN].status = 1;
|
||||
endpoints[ep][out ? DIR_OUT : DIR_IN].done = true;
|
||||
semaphore_release(&endpoints[ep][out ? DIR_OUT : DIR_IN].complete);
|
||||
}
|
||||
}
|
||||
|
||||
if (out && (epints & DOEPINT_setup))
|
||||
{
|
||||
commit_discard_dcache();
|
||||
if (ep != 0)
|
||||
panicf("USB: SETUP done on OUT EP%d!?", ep);
|
||||
|
||||
/* Set the new address here, before passing the packet to the core.
|
||||
See usb_drv_set_address() for details. */
|
||||
if (ctrlreq.header.bRequest == USB_REQ_SET_ADDRESS)
|
||||
DCFG = (DCFG & ~(DCFG_devadr_bits << DCFG_devadr_bitp))
|
||||
| (ctrlreq.header.wValue << DCFG_devadr_bitp);
|
||||
|
||||
usb_core_control_request(&ctrlreq.header);
|
||||
}
|
||||
|
||||
/* Make sure EP0 OUT is set up to accept the next request */
|
||||
if (out && ep == 0)
|
||||
{
|
||||
DEPTSIZ(0, true) = (1 << DEPTSIZ0_supcnt_bitp) | (1 << DEPTSIZ0_pkcnt_bitp) | 64;
|
||||
DEPDMA(0, true) = &ctrlreq;
|
||||
DEPCTL(0, true) |= DEPCTL_epena | DEPCTL_cnak;
|
||||
}
|
||||
DEPINT(ep, out) = epints;
|
||||
}
|
||||
}
|
||||
|
||||
/* IRQ handler */
|
||||
void INT_USB_FUNC(void)
|
||||
{
|
||||
uint32_t ints = GINTSTS;
|
||||
if (ints & GINTMSK_usbreset)
|
||||
{
|
||||
DCFG = DCFG_nzstsouthshk; /* Address 0 */
|
||||
reset_endpoints(1);
|
||||
usb_core_bus_reset();
|
||||
}
|
||||
|
||||
if (ints & GINTMSK_enumdone) /* enumeration done, we now know the speed */
|
||||
{
|
||||
/* Set up the maximum packet sizes accordingly */
|
||||
uint32_t maxpacket = (usb_drv_port_speed() ? 512 : 64) << DEPCTL_mps_bitp;
|
||||
DEPCTL(1, false) = (DEPCTL(1, false) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket;
|
||||
DEPCTL(2, true) = (DEPCTL(2, true) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket;
|
||||
DEPCTL(3, false) = (DEPCTL(3, false) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket;
|
||||
DEPCTL(4, true) = (DEPCTL(4, true) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket;
|
||||
}
|
||||
|
||||
if (ints & GINTMSK_inepintr)
|
||||
handle_ep_int(false);
|
||||
|
||||
if (ints & GINTMSK_outepintr)
|
||||
handle_ep_int(true);
|
||||
|
||||
GINTSTS = ints;
|
||||
}
|
||||
|
||||
static void ep_transfer(int ep, void *ptr, int len, bool out)
|
||||
{
|
||||
while (!out && inflight && plugged);
|
||||
if (!plugged) return;
|
||||
|
||||
/* disable interrupts to avoid any race */
|
||||
int oldlevel = disable_irq_save();
|
||||
if (!out) inflight = true;
|
||||
endpoints[ep][out ? DIR_OUT : DIR_IN].busy = true;
|
||||
endpoints[ep][out ? DIR_OUT : DIR_IN].size = len;
|
||||
|
||||
if (out) DEPCTL(ep, out) &= ~DEPCTL_stall;
|
||||
|
||||
|
||||
int mps = usb_drv_port_speed() ? 512 : 64;
|
||||
int nb_packets = (len + mps - 1) / mps;
|
||||
if (nb_packets == 0)
|
||||
nb_packets = 1;
|
||||
|
||||
DEPDMA(ep, out) = len ? ptr : NULL;
|
||||
DEPTSIZ(ep, out) = (nb_packets << DEPTSIZ_pkcnt_bitp) | len;
|
||||
|
||||
if(out) discard_dcache_range(ptr, len);
|
||||
else commit_dcache_range(ptr, len);
|
||||
|
||||
logf("pkt=%d dma=%lx", nb_packets, DEPDMA(ep, out));
|
||||
|
||||
DEPCTL(ep, out) |= DEPCTL_epena | DEPCTL_cnak;
|
||||
|
||||
restore_irq(oldlevel);
|
||||
}
|
||||
|
||||
int usb_drv_send(int endpoint, void *ptr, int length)
|
||||
{
|
||||
endpoint = EP_NUM(endpoint);
|
||||
endpoints[endpoint][1].done = false;
|
||||
ep_transfer(endpoint, ptr, length, false);
|
||||
while (!endpoints[endpoint][1].done && endpoints[endpoint][1].busy)
|
||||
semaphore_wait(&endpoints[endpoint][1].complete, TIMEOUT_BLOCK);
|
||||
return endpoints[endpoint][1].status;
|
||||
}
|
||||
|
||||
void usb_drv_cancel_all_transfers(void)
|
||||
{
|
||||
int flags = disable_irq_save();
|
||||
reset_endpoints(0);
|
||||
restore_irq(flags);
|
||||
}
|
||||
|
||||
void usb_drv_init(void)
|
||||
{
|
||||
for (unsigned i = 0; i < sizeof(endpoints)/(2*sizeof(struct ep_type)); i++)
|
||||
for (unsigned dir = 0; dir < 2; dir++)
|
||||
semaphore_init(&endpoints[i][dir].complete, 1, 0);
|
||||
|
||||
/* Enable USB clock */
|
||||
#if CONFIG_CPU==S5L8701
|
||||
PWRCON &= ~0x4000;
|
||||
PWRCONEXT &= ~0x800;
|
||||
INTMSK |= INTMSK_USB_OTG;
|
||||
#elif CONFIG_CPU==S5L8702
|
||||
PWRCON(0) &= ~0x4;
|
||||
PWRCON(1) &= ~0x8;
|
||||
VIC0INTENABLE |= 1 << 19;
|
||||
#endif
|
||||
PCGCCTL = 0;
|
||||
|
||||
/* reset the beast */
|
||||
plugged = true;
|
||||
usb_reset();
|
||||
}
|
||||
|
||||
void usb_drv_exit(void)
|
||||
{
|
||||
plugged = false;
|
||||
DCTL = DCTL_pwronprgdone | DCTL_sftdiscon;
|
||||
|
||||
OPHYPWR = 0xF; /* PHY: Power down */
|
||||
udelay(10);
|
||||
ORSTCON = 7; /* Put the PHY into reset (needed to get current down) */
|
||||
udelay(10);
|
||||
PCGCCTL = 1; /* Shut down PHY clock */
|
||||
|
||||
#if CONFIG_CPU==S5L8701
|
||||
PWRCON |= 0x4000;
|
||||
PWRCONEXT |= 0x800;
|
||||
#elif CONFIG_CPU==S5L8702
|
||||
PWRCON(0) |= 0x4;
|
||||
PWRCON(1) |= 0x8;
|
||||
#endif
|
||||
}
|
||||
|
||||
void usb_attach(void)
|
||||
{
|
||||
usb_enable(true);
|
||||
}
|
||||
#endif // CONFIG_CPU == AS3525v2 /* FIXME FIXME FIXME */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue