forked from len0rd/rockbox
atj213x: e100/150 lcd test binary
Change-Id: I3f9fa21dcb33d1cd3081d0c995adfb44e085dd7a
This commit is contained in:
Marcin Bukat
parent
fe519c7e4d
commit
c626fe7004
10 changed files with 6075 additions and 0 deletions
40
utils/atj2137/adfuload/test_binary/lcm/Makefile
Normal file
40
utils/atj2137/adfuload/test_binary/lcm/Makefile
Normal file
|
|
@ -0,0 +1,40 @@
|
||||||
|
|
||||||
|
TARGET = lcm
|
||||||
|
|
||||||
|
TOOLCHAIN = mipsel-elf-
|
||||||
|
|
||||||
|
CC = $(TOOLCHAIN)gcc
|
||||||
|
CPP = $(TOOLCHAIN)cpp
|
||||||
|
LD = $(TOOLCHAIN)gcc
|
||||||
|
AS = $(TOOLCHAIN)as
|
||||||
|
OBJCOPY = $(TOOLCHAIN)objcopy
|
||||||
|
OBJDUMP = $(TOOLCHAIN)objdump
|
||||||
|
|
||||||
|
CFLAGS = -Wundef -march=mips32r2 -nostdlib -Os -G0 -c
|
||||||
|
|
||||||
|
OBJS = crt0.o test_lcm.o system-atj213x.o irq_handler.o rockboxlogo.240x74x16.o
|
||||||
|
LDSCRIPT= test.lds
|
||||||
|
|
||||||
|
LDFLAGS = -Wundef -march=mips32r2 -T$(LDSCRIPT) -nostartfiles \
|
||||||
|
-nostdlib -Xlinker -Map=$(TARGET).map
|
||||||
|
|
||||||
|
all : $(TARGET).bin
|
||||||
|
ls -ls $(TARGET).bin
|
||||||
|
|
||||||
|
%.o : %.c
|
||||||
|
$(CC) $(CPPFLAGS) $(CFLAGS) $(INCDIRS) $< -o $@
|
||||||
|
|
||||||
|
%.o : %.S
|
||||||
|
$(CC) $(CFLAGS) $< -o $@
|
||||||
|
|
||||||
|
$(TARGET).elf : $(OBJS)
|
||||||
|
$(LD) $(LDFLAGS) $(OBJS) $(LIBDIRS) $(LIBS) -o $(TARGET).elf
|
||||||
|
|
||||||
|
$(TARGET).bin : $(TARGET).elf
|
||||||
|
$(OBJCOPY) -O binary $(TARGET).elf $(TARGET).bin
|
||||||
|
|
||||||
|
clean :
|
||||||
|
rm -f $(OBJS)
|
||||||
|
rm -f $(TARGET).elf
|
||||||
|
rm -f $(TARGET).bin
|
||||||
|
rm -f $(TARGET).map
|
||||||
383
utils/atj2137/adfuload/test_binary/lcm/atj213x.h
Normal file
383
utils/atj2137/adfuload/test_binary/lcm/atj213x.h
Normal file
|
|
@ -0,0 +1,383 @@
|
||||||
|
typedef unsigned int uint32_t;
|
||||||
|
|
||||||
|
#define PMU_BASE 0xB0000000
|
||||||
|
#define PMU_CTL (*(volatile uint32_t *)(PMU_BASE + 0x00))
|
||||||
|
#define PMU_CTL_BL_EN (1<<15)
|
||||||
|
#define PMU_LRADC (*(volatile uint32_t *)(PMU_BASE + 0x04))
|
||||||
|
#define PMU_CHG (*(volatile uint32_t *)(PMU_BASE + 0x08))
|
||||||
|
#define PMU_CHG_PBLS (1<<15)
|
||||||
|
#define PMU_CHG_PBLS_PWM (1<<15)
|
||||||
|
#define PMU_CHG_PBLS_BL_NDR (0<<15)
|
||||||
|
#define PMU_CHG_PPHS (1<<14)
|
||||||
|
#define PMU_CHG_PPHS_HIGH (1<<14)
|
||||||
|
#define PMU_CHG_PPHS_LOW (0<<14)
|
||||||
|
#define PMU_CHG_PDUT(x) (((x) & 0x1f) << 8)
|
||||||
|
#define PMU_CHG_PDOUT_MASK (0x1f << 8)
|
||||||
|
|
||||||
|
#define CMU_BASE 0xB0010000
|
||||||
|
#define CMU_COREPLL (*(volatile uint32_t *)(CMU_BASE + 0x00))
|
||||||
|
#define CMU_DSPPLL (*(volatile uint32_t *)(CMU_BASE + 0x04))
|
||||||
|
#define CMU_AUDIOPLL (*(volatile uint32_t *)(CMU_BASE + 0x08))
|
||||||
|
#define CMU_BUSCLK (*(volatile uint32_t *)(CMU_BASE + 0x0C))
|
||||||
|
#define CMU_SDRCLK (*(volatile uint32_t *)(CMU_BASE + 0x10))
|
||||||
|
#define CMU_ATACLK (*(volatile uint32_t *)(CMU_BASE + 0x04))
|
||||||
|
#define CMU_NANDCLK (*(volatile uint32_t *)(CMU_BASE + 0x18))
|
||||||
|
#define CMU_SDCLK (*(volatile uint32_t *)(CMU_BASE + 0x1C))
|
||||||
|
#define CMU_MHACLK (*(volatile uint32_t *)(CMU_BASE + 0x20))
|
||||||
|
#define CMU_BTCLK (*(volatile uint32_t *)(CMU_BASE + 0x24))
|
||||||
|
#define CMU_IRCLK (*(volatile uint32_t *)(CMU_BASE + 0x28))
|
||||||
|
#define CMU_UART2CLK (*(volatile uint32_t *)(CMU_BASE + 0x2C))
|
||||||
|
#define CMU_DMACLK (*(volatile uint32_t *)(CMU_BASE + 0x30))
|
||||||
|
#define CMU_FMCLK (*(volatile uint32_t *)(CMU_BASE + 0x34))
|
||||||
|
#define CMU_FMCLK_BCKE (1<<5)
|
||||||
|
#define CMI_FMCLK_BCKS (1<<4)
|
||||||
|
#define CMU_FMCLK_BCKS_32K (0<<4)
|
||||||
|
#define CMU_FMCLK_BCKS_3M (1<<4)
|
||||||
|
|
||||||
|
#define CMU_FMCLK_BCLK_MASK (CMI_FMCLK_BCKS | (3<<2))
|
||||||
|
#define CMU_FMCLK_BCLK_3M (CMU_FMCLK_BCKS_3M | (0<<2))
|
||||||
|
#define CMU_FMCLK_BCLK_1_5M (CMU_FMCLK_BCKS_3M | (1<<2))
|
||||||
|
#define CMU_FMCLK_BCLK_750K (CMU_FMCLK_BCKS_3M | (2<<2))
|
||||||
|
#define CMU_FMCLK_BCLK_375K (CMU_FMCLK_BCKS_3M | (3<<2))
|
||||||
|
|
||||||
|
#define CMU_FMCLK_BCLK_32K (0<<2)
|
||||||
|
#define CMU_FMCLK_BCLK_16K (1<<2)
|
||||||
|
#define CMU_FMCLK_BCLK_8K (2<<2)
|
||||||
|
#define CMU_FMCLK_BCLK_4K (3<<2)
|
||||||
|
|
||||||
|
#define CMU_MCACLK (*(volatile uint32_t *)(CMU_BASE + 0x38))
|
||||||
|
|
||||||
|
#define CMU_DEVCLKEN (*(volatile uint32_t *)(CMU_BASE + 0x80))
|
||||||
|
#define CMU_DEVRST (*(volatile uint32_t *)(CMU_BASE + 0x84))
|
||||||
|
|
||||||
|
#define RTC_BASE 0xB0018000
|
||||||
|
#define RTC_CTL (*(volatile uint32_t *)(RTC_BASE + 0x00))
|
||||||
|
#define RTC_DHMS (*(volatile uint32_t *)(RTC_BASE + 0x04))
|
||||||
|
#define RTC_YMD (*(volatile uint32_t *)(RTC_BASE + 0x08))
|
||||||
|
#define RTC_DHMSALM (*(volatile uint32_t *)(RTC_BASE + 0x0C))
|
||||||
|
#define RTC_YMDALM (*(volatile uint32_t *)(RTC_BASE + 0x10))
|
||||||
|
#define RTC_WDCTL (*(volatile uint32_t *)(RTC_BASE + 0x14))
|
||||||
|
#define RTC_WDCTL_CLR (1<<0)
|
||||||
|
|
||||||
|
#define RTC_T0CTL (*(volatile uint32_t *)(RTC_BASE + 0x18))
|
||||||
|
#define RTC_T0 (*(volatile uint32_t *)(RTC_BASE + 0x1C))
|
||||||
|
#define RTC_T1CTL (*(volatile uint32_t *)(RTC_BASE + 0x20))
|
||||||
|
#define RTC_T1 (*(volatile uint32_t *)(RTC_BASE + 0x24))
|
||||||
|
|
||||||
|
#define INTC_BASE 0xB0020000
|
||||||
|
#define INTC_PD (*(volatile uint32_t *)(INTC_BASE + 0x00))
|
||||||
|
#define INTC_MSK (*(volatile uint32_t *)(INTC_BASE + 0x04))
|
||||||
|
#define INTC_CFG0 (*(volatile uint32_t *)(INTC_BASE + 0x08))
|
||||||
|
#define INTC_CFG1 (*(volatile uint32_t *)(INTC_BASE + 0x0C))
|
||||||
|
#define INTC_CFG2 (*(volatile uint32_t *)(INTC_BASE + 0x10))
|
||||||
|
#define INTC_EXTCTL (*(volatile uint32_t *)(INTC_BASE + 0x14))
|
||||||
|
|
||||||
|
#define SRAMOC_BASE 0xB0030000
|
||||||
|
#define SRAMOC_CTL (*(volatile uint32_t *)(SRAMOC_BASE + 0x00))
|
||||||
|
#define SRAMOC_STAT (*(volatile uint32_t *)(SRAMOC_BASE + 0x04))
|
||||||
|
|
||||||
|
#define BOOT_BASE 0xB00380000
|
||||||
|
#define BOOT_NORCTL (*(volatile uint32_t *)(BOOT_BASE + 0x00))
|
||||||
|
#define BOOT_BROMCTL (*(volatile uint32_t *)(BOOT_BASE + 0x04))
|
||||||
|
#define BOOT_CHIPID (*(volatile uint32_t *)(BOOT_BASE + 0x08))
|
||||||
|
|
||||||
|
#define PCNT_BASE 0xB0040000
|
||||||
|
#define PCNT_CTL (*(volatile uint32_t *)(PCNT_BASE + 0x00))
|
||||||
|
#define PCNT_PC0 (*(volatile uint32_t *)(PCNT_BASE + 0x04))
|
||||||
|
#define PCNT_PC1 (*(volatile uint32_t *)(PCNT_BASE + 0x08))
|
||||||
|
|
||||||
|
#define DSP_BASE 0xB0050000
|
||||||
|
#define DSP_HDR0 (*(volatile uint32_t *)(DSP_BASE + 0x00))
|
||||||
|
#define DSP_HDR1 (*(volatile uint32_t *)(DSP_BASE + 0x04))
|
||||||
|
#define DSP_HDR2 (*(volatile uint32_t *)(DSP_BASE + 0x08))
|
||||||
|
#define DSP_HDR3 (*(volatile uint32_t *)(DSP_BASE + 0x0C))
|
||||||
|
#define DSP_HDR4 (*(volatile uint32_t *)(DSP_BASE + 0x10))
|
||||||
|
#define DSP_HDR5 (*(volatile uint32_t *)(DSP_BASE + 0x14))
|
||||||
|
#define DSP_HSR6 (*(volatile uint32_t *)(DSP_BASE + 0x18))
|
||||||
|
#define DSP_HSR7 (*(volatile uint32_t *)(DSP_BASE + 0x1C))
|
||||||
|
#define DSP_CTL (*(volatile uint32_t *)(DSP_BASE + 0x20))
|
||||||
|
|
||||||
|
#define DMAC_BASE(n) (0xB0060000 + (n<<5))
|
||||||
|
#define DMAC_CTL (*(volatile uint32_t *)(DMAC_BASE(0) + 0x00))
|
||||||
|
#define DMAC_IRQEN (*(volatile uint32_t *)(DMAC_BASE(0) + 0x04))
|
||||||
|
#define DMAC_IRQPD (*(volatile uint32_t *)(DMAC_BASE(0) + 0x08))
|
||||||
|
|
||||||
|
/* n in range 0-7 */
|
||||||
|
#define DMA_MODE(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x100))
|
||||||
|
#define DMA_SRC(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x104))
|
||||||
|
#define DMA_DST(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x108))
|
||||||
|
#define DMA_CNT(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x10C))
|
||||||
|
#define DMA_REM(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x110))
|
||||||
|
#define DMA_CMD(n) (*(volatile uint32_t *)(DMAC_BASE(n) + 0x114))
|
||||||
|
|
||||||
|
#define SDR_BASE 0xB0070000
|
||||||
|
#define SDR_CTL (*(volatile uint32_t *)(SDR_BASE + 0x00))
|
||||||
|
#define SDR_ADDRCFG (*(volatile uint32_t *)(SDR_BASE + 0x04))
|
||||||
|
#define SDR_EN (*(volatile uint32_t *)(SDR_BASE + 0x08))
|
||||||
|
#define SDR_CMD (*(volatile uint32_t *)(SDR_BASE + 0x0C))
|
||||||
|
#define SDR_STAT (*(volatile uint32_t *)(SDR_BASE + 0x10))
|
||||||
|
#define SDR_RFSH (*(volatile uint32_t *)(SDR_BASE + 0x14))
|
||||||
|
#define SDR_MODE (*(volatile uint32_t *)(SDR_BASE + 0x18))
|
||||||
|
#define SDR_MOBILE (*(volatile uint32_t *)(SDR_BASE + 0x1C))
|
||||||
|
|
||||||
|
#define MCA_BASE 0xB0080000
|
||||||
|
#define MCA_CTL (*(volatile uint32_t *)(MCA_BASE + 0x00))
|
||||||
|
|
||||||
|
#define ATA_BASE 0xB0090000
|
||||||
|
#define ATA_CONFIG (*(volatile uint32_t *)(ATA_BASE + 0x00))
|
||||||
|
#define ATA_UDMACTL (*(volatile uint32_t *)(ATA_BASE + 0x04))
|
||||||
|
#define ATA_DATA (*(volatile uint32_t *)(ATA_BASE + 0x08))
|
||||||
|
#define ATA_FEATURE (*(volatile uint32_t *)(ATA_BASE + 0x0C))
|
||||||
|
#define ATA_SECCNT (*(volatile uint32_t *)(ATA_BASE + 0x10))
|
||||||
|
#define ATA_SECNUM (*(volatile uint32_t *)(ATA_BASE + 0x14))
|
||||||
|
#define ATA_CLDLOW (*(volatile uint32_t *)(ATA_BASE + 0x18))
|
||||||
|
#define ATA_CLDHI (*(volatile uint32_t *)(ATA_BASE + 0x1C))
|
||||||
|
#define ATA_HEAD (*(volatile uint32_t *)(ATA_BASE + 0x20))
|
||||||
|
#define ATA_CMD (*(volatile uint32_t *)(ATA_BASE + 0x24))
|
||||||
|
#define ATA_BYTECNT (*(volatile uint32_t *)(ATA_BASE + 0x28))
|
||||||
|
#define ATA_FIFOCTL (*(volatile uint32_t *)(ATA_BASE + 0x2C))
|
||||||
|
#define ATA_FIFOCFG (*(volatile uint32_t *)(ATA_BASE + 0x30))
|
||||||
|
#define ATA_ADDRDEC (*(volatile uint32_t *)(ATA_BASE + 0x34))
|
||||||
|
#define ATA_IRQCTL (*(volatile uint32_t *)(ATA_BASE + 0x38))
|
||||||
|
|
||||||
|
#define NAND_BASE 0xB00A0000
|
||||||
|
#define NAND_CTL (*(volatile uint32_t *)(NAND_BASE + 0x00))
|
||||||
|
#define NAND_STATUS (*(volatile uint32_t *)(NAND_BASE + 0x04))
|
||||||
|
#define NAND_FIFOTIM (*(volatile uint32_t *)(NAND_BASE + 0x08))
|
||||||
|
#define NAND_CLKCTL (*(volatile uint32_t *)(NAND_BASE + 0x0C))
|
||||||
|
#define NAND_BYTECNT (*(volatile uint32_t *)(NAND_BASE + 0x10))
|
||||||
|
#define NAND_ADDRLO1234 (*(volatile uint32_t *)(NAND_BASE + 0x14))
|
||||||
|
#define NAND_ADDRLO56 (*(volatile uint32_t *)(NAND_BASE + 0x18))
|
||||||
|
#define NAND_ADDRHI1234 (*(volatile uint32_t *)(NAND_BASE + 0x1C))
|
||||||
|
#define NAND_ADDRHI56 (*(volatile uint32_t *)(NAND_BASE + 0x20))
|
||||||
|
#define NAND_BUF0 (*(volatile uint32_t *)(NAND_BASE + 0x24))
|
||||||
|
#define NAND_BUF1 (*(volatile uint32_t *)(NAND_BASE + 0x28))
|
||||||
|
#define NAND_CMD (*(volatile uint32_t *)(NAND_BASE + 0x2C))
|
||||||
|
#define NAND_ECCCTL (*(volatile uint32_t *)(NAND_BASE + 0x30))
|
||||||
|
#define NAND_HAMECC0 (*(volatile uint32_t *)(NAND_BASE + 0x34))
|
||||||
|
#define NAND_HAMECC1 (*(volatile uint32_t *)(NAND_BASE + 0x38))
|
||||||
|
#define NAND_HAMECC2 (*(volatile uint32_t *)(NAND_BASE + 0x3C))
|
||||||
|
#define NAND_HAMCEC (*(volatile uint32_t *)(NAND_BASE + 0x40))
|
||||||
|
#define NAND_RSE0 (*(volatile uint32_t *)(NAND_BASE + 0x44))
|
||||||
|
#define NAND_RSE1 (*(volatile uint32_t *)(NAND_BASE + 0x48))
|
||||||
|
#define NAND_RSE2 (*(volatile uint32_t *)(NAND_BASE + 0x4C))
|
||||||
|
#define NAND_RSE3 (*(volatile uint32_t *)(NAND_BASE + 0x50))
|
||||||
|
#define NAND_RSPS0 (*(volatile uint32_t *)(NAND_BASE + 0x54))
|
||||||
|
#define NAND_RSPS1 (*(volatile uint32_t *)(NAND_BASE + 0x58))
|
||||||
|
#define NAND_RSPS2 (*(volatile uint32_t *)(NAND_BASE + 0x5C))
|
||||||
|
#define NAND_FIFODATA (*(volatile uint32_t *)(NAND_BASE + 0x60))
|
||||||
|
#define NAND_DEBUG (*(volatile uint32_t *)(NAND_BASE + 0x70))
|
||||||
|
|
||||||
|
#define SD_BASE 0xB00B0000
|
||||||
|
#define SD_CTL (*(volatile uint32_t *)(SD_BASE + 0x00))
|
||||||
|
#define SD_CMDRSP (*(volatile uint32_t *)(SD_BASE + 0x04))
|
||||||
|
#define SD_RW (*(volatile uint32_t *)(SD_BASE + 0x08))
|
||||||
|
#define SD_FIFOCTL (*(volatile uint32_t *)(SD_BASE + 0x0C))
|
||||||
|
#define SD_CMD (*(volatile uint32_t *)(SD_BASE + 0x10))
|
||||||
|
#define SD_ARG (*(volatile uint32_t *)(SD_BASE + 0x14))
|
||||||
|
#define SD_CRC7 (*(volatile uint32_t *)(SD_BASE + 0x18))
|
||||||
|
#define SD_RSPBUF0 (*(volatile uint32_t *)(SD_BASE + 0x1C))
|
||||||
|
#define SD_RSPBUF1 (*(volatile uint32_t *)(SD_BASE + 0x20))
|
||||||
|
#define SD_RSPBUF2 (*(volatile uint32_t *)(SD_BASE + 0x24))
|
||||||
|
#define SD_RSPBUF3 (*(volatile uint32_t *)(SD_BASE + 0x28))
|
||||||
|
#define SD_RSPBUF4 (*(volatile uint32_t *)(SD_BASE + 0x2C))
|
||||||
|
#define SD_DAT (*(volatile uint32_t *)(SD_BASE + 0x30))
|
||||||
|
#define SD_CLK (*(volatile uint32_t *)(SD_BASE + 0x34))
|
||||||
|
#define SD_BYTECNT (*(volatile uint32_t *)(SD_BASE + 0x38))
|
||||||
|
|
||||||
|
#define MHA_BASE 0xB00C0000
|
||||||
|
#define MHA_CTL (*(volatile uint32_t *)(MHA_BASE + 0x00))
|
||||||
|
#define MHA_CFG (*(volatile uint32_t *)(MHA_BASE + 0x04))
|
||||||
|
#define MHA_DCSCL01 (*(volatile uint32_t *)(MHA_BASE + 0x10))
|
||||||
|
#define MHA_DCSCL23 (*(volatile uint32_t *)(MHA_BASE + 0x14))
|
||||||
|
#define MHA_DCSCL45 (*(volatile uint32_t *)(MHA_BASE + 0x18))
|
||||||
|
#define MHA_DCSCL67 (*(volatile uint32_t *)(MHA_BASE + 0x1C))
|
||||||
|
#define MHA_QSCL (*(volatile uint32_t *)(MHA_BASE + 0x20))
|
||||||
|
|
||||||
|
#define BT_BASE 0xB00D0000
|
||||||
|
#define BT_MODESEL (*(volatile uint32_t *)(BT_BASE + 0x00))
|
||||||
|
#define BT_FIFODAT (*(volatile uint32_t *)(BT_BASE + 0x04))
|
||||||
|
|
||||||
|
/* video Encoder */
|
||||||
|
#define BT_VEICTL (*(volatile uint32_t *)(BT_BASE + 0x08))
|
||||||
|
#define BT_VEIVSEPOF (*(volatile uint32_t *)(BT_BASE + 0x14))
|
||||||
|
#define BT_VEIVSEPEF (*(volatile uint32_t *)(BT_BASE + 0x18))
|
||||||
|
#define BT_VEIFTP (*(volatile uint32_t *)(BT_BASE + 0x24))
|
||||||
|
#define BT_VEIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30))
|
||||||
|
|
||||||
|
/* Video Decoder */
|
||||||
|
#define BT_VDICTL (*(volatile uint32_t *)(BT_BASE + 0x08))
|
||||||
|
#define BT_VDIHSPOS (*(volatile uint32_t *)(BT_BASE + 0x0C))
|
||||||
|
#define BT_VDIHEPOS (*(volatile uint32_t *)(BT_BASE + 0x10))
|
||||||
|
#define BT_VDIVSEPOF (*(volatile uint32_t *)(BT_BASE + 0x14))
|
||||||
|
#define BT_VDIVSEPEF (*(volatile uint32_t *)(BT_BASE + 0x18))
|
||||||
|
#define BT_VDIIRQSTA (*(volatile uint32_t *)(BT_BASE + 0x28))
|
||||||
|
#define BT_VDIXYDAT (*(volatile uint32_t *)(BT_BASE + 0x2C))
|
||||||
|
#define BT_VDIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30))
|
||||||
|
|
||||||
|
/* CMOS Sensor Interface */
|
||||||
|
#define BT_CSICTL (*(volatile uint32_t *)(BT_BASE + 0x08))
|
||||||
|
#define BT_CSIHSPOS (*(volatile uint32_t *)(BT_BASE + 0x0C))
|
||||||
|
#define BT_CSIHEPOS (*(volatile uint32_t *)(BT_BASE + 0x10))
|
||||||
|
#define BT_CSIVSPOS (*(volatile uint32_t *)(BT_BASE + 0x1C))
|
||||||
|
#define BT_CSIVEPOS (*(volatile uint32_t *)(BT_BASE + 0x20))
|
||||||
|
#define BT_CSIIRQSTA (*(volatile uint32_t *)(BT_BASE + 0x28))
|
||||||
|
#define BT_CSIXYDAT (*(volatile uint32_t *)(BT_BASE + 0x2C))
|
||||||
|
#define BT_CSIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30))
|
||||||
|
|
||||||
|
/* TS */
|
||||||
|
#define BT_TSICTL (*(volatile uint32_t *)(BT_BASE + 0x08))
|
||||||
|
#define BT_TSIFIFOCTL (*(volatile uint32_t *)(BT_BASE + 0x30))
|
||||||
|
|
||||||
|
/* Integrated Video Encoder */
|
||||||
|
#define BT_IVECTL (*(volatile uint32_t *)(BT_BASE + 0x34))
|
||||||
|
#define BT_IVEOUTCTL (*(volatile uint32_t *)(BT_BASE + 0x38))
|
||||||
|
#define BT_IVECOTCTL (*(volatile uint32_t *)(BT_BASE + 0x3C))
|
||||||
|
#define BT_IVEBRGCTL (*(volatile uint32_t *)(BT_BASE + 0x40))
|
||||||
|
#define BT_IVECSATCTL (*(volatile uint32_t *)(BT_BASE + 0x44))
|
||||||
|
#define BT_IVECBURCTL (*(volatile uint32_t *)(BT_BASE + 0x48))
|
||||||
|
#define BT_IVESYNCAMCTL (*(volatile uint32_t *)(BT_BASE + 0x4C))
|
||||||
|
|
||||||
|
#define OTG_BASE 0xB00E0000
|
||||||
|
#define OTG_OUT0BC (*(volatile uint8_t *)(OTG_BASE + 0x00)) // ok (byte count?)
|
||||||
|
#define OTG_IN0BC (*(volatile uint8_t *)(OTG_BASE + 0x01)) // ok (byte count?)
|
||||||
|
#define OTG_EP0CS (*(volatile uint8_t *)(OTG_BASE + 0x02)) // ok
|
||||||
|
#define EP_NAK (1<<1) // from rt source
|
||||||
|
#define EP0_IN_BUSY (1<<2)
|
||||||
|
#define EP0_OUT_BUSY (1<<3)
|
||||||
|
|
||||||
|
#define OTG_OUT1CON (*(volatile uint8_t *)(OTG_BASE + 0x0A)) // ok
|
||||||
|
#define OTG_OUT1CS (*(volatile uint8_t *)(OTG_BASE + 0x0B)) // missing in rt
|
||||||
|
|
||||||
|
#define OTG_OUT2CON (*(volatile uint8_t *)(OTG_BASE + 0x12)) // missing in sdk
|
||||||
|
#define OTG_OUT2CS (*(volatile uint8_t *)(OTG_BASE + 0x13)) // deduced
|
||||||
|
|
||||||
|
#define OTG_IN2BCL (*(volatile uint8_t *)(OTG_BASE + 0x14)) // missing in rt
|
||||||
|
#define OTG_IN2BCH (*(volatile uint8_t *)(OTG_BASE + 0x15)) // missing in rt
|
||||||
|
#define OTG_IN2CON (*(volatile uint8_t *)(OTG_BASE + 0x16)) // ok
|
||||||
|
#define OTG_IN2CS (*(volatile uint8_t *)(OTG_BASE + 0x17)) //
|
||||||
|
|
||||||
|
#define OTG_FIFO1DAT (*(volatile uint32_t *)(OTG_BASE + 0x84)) // missing in rt
|
||||||
|
#define OTG_FIFO2DAT (*(volatile uint32_t *)(OTG_BASE + 0x88)) // missing in rt
|
||||||
|
|
||||||
|
#define OTG_EP0INDAT (*(volatile uint8_t *)(OTG_BASE + 0x100) // ok
|
||||||
|
|
||||||
|
#define OTG_EP0OUTDAT (*(volatile uint8_t *)(OTG_BASE + 0x140) // ok
|
||||||
|
|
||||||
|
#define OTG_SETUPDAT (*(volatile uint8_t *)(OTG_BASE + 0x180) // ok
|
||||||
|
#define OTG_USBIRQ (*(volatile uint8_t *)(OTG_BASE + 0x18C) // ok
|
||||||
|
|
||||||
|
#define OTG_USBIEN (*(volatile uint8_t *)(OTG_BASE + 0x198)) // ok
|
||||||
|
|
||||||
|
#define OTG_IVECT (*(volatile uint8_t *)(OTG_BASE + 0x1A0)) // missing in rt
|
||||||
|
#define OTG_ENDPRST (*(volatile uint8_t *)(OTG_BASE + 0x1A2)) // ok
|
||||||
|
#define OTG_USBCS (*(volatile uint8_t *)(OTG_BASE + 0x1A3)) // ok
|
||||||
|
#define SOFT_DISCONN (1<<6) // set for soft disconnect
|
||||||
|
|
||||||
|
#define OTG_FIFOCTL (*(volatile uint8_t *)(OTG_BASE + 0x1A8)) // ok
|
||||||
|
|
||||||
|
|
||||||
|
#define OTG_OTGIRQ (*(volatile uint8_t *)(OTG_BASE + 0x1BC))
|
||||||
|
#define OTG_FSMSTAT (*(volatile uint8_t *)(OTG_BASE + 0x1BD))
|
||||||
|
#define OTG_CTRL (*(volatile uint8_t *)(OTG_BASE + 0x1BE))
|
||||||
|
#define OTG_STAT (*(volatile uint8_t *)(OTG_BASE + 0x1BF))
|
||||||
|
#define OTG_OTGIEN (*(volatile uint8_t *)(OTG_BASE + 0x1C0))
|
||||||
|
|
||||||
|
#define OTG_TAAIDLBDIS (*(volatile uint8_t *)(OTG_BASE + 0x1C1))
|
||||||
|
#define OTG_TAWAITBCON (*(volatile uint8_t *)(OTG_BASE + 0x1C2))
|
||||||
|
#define OTG_TBVBUSPLS (*(volatile uint8_t *)(OTG_BASE + 0x1C3))
|
||||||
|
#define OTG_TBVBUSDISPLS (*(volatile uint8_t *)(OTG_BASE + 0x1C7))
|
||||||
|
|
||||||
|
#define OTG_HCIN1MAXPCKL (*(volatile uint8_t *)(OTG_BASE + 0x1E2))
|
||||||
|
#define OTG_HCIN1MAXPCKH (*(volatile uint8_t *)(OTG_BASE + 0x1E3))
|
||||||
|
|
||||||
|
#define OTG_OUT1STADDR ((*(volatile uint8_t *)(OTG_BASE + 0x304))
|
||||||
|
|
||||||
|
#define OTG_IN2STADDR ((*(volatile uint8_t *)(OTG_BASE + 0x348))
|
||||||
|
|
||||||
|
#define OTG_HCOUT2MAXPCKL ((*(volatile uint8_t *)(OTG_BASE + 0x3E4))
|
||||||
|
#define OTG_HCOUT2MAXPCKH ((*(volatile uint8_t *)(OTG_BASE + 0x3E5))
|
||||||
|
|
||||||
|
#define OTG_USBEIRQ ((*(volatile uint8_t *)(OTG_BASE + 0x400))
|
||||||
|
|
||||||
|
#define OTG_DMAEPSEL ((*(volatile uint8_t *)(OTG_BASE + 0x40C))
|
||||||
|
|
||||||
|
#define YUV2RGB_BASE 0xB00F0000
|
||||||
|
#define YUV2RGB_CTL (*(volatile uint32_t *)(YUV2RGB_BASE + 0x00))
|
||||||
|
#define YUV2RGB_FIFODATA (*(volatile uint32_t *)(YUV2RGB_BASE + 0x04))
|
||||||
|
#define YUV2RGB_CLKCTL (*(volatile uint32_t *)(YUV2RGB_BASE + 0x08))
|
||||||
|
#define YUV2RGB_FRAMECOUNT (*(volatile uint32_t *)(YUV2RGB_BASE + 0x0C))
|
||||||
|
|
||||||
|
#define DAC_BASE 0xB0100000
|
||||||
|
#define DAC_CTL (*(volatile uint32_t *)(DAC_BASE + 0x00))
|
||||||
|
#define DAC_FIFOCTL (*(volatile uint32_t *)(DAC_BASE + 0x04))
|
||||||
|
#define DAC_DAT (*(volatile uint32_t *)(DAC_BASE + 0x08))
|
||||||
|
#define DAC_DEBUG (*(volatile uint32_t *)(DAC_BASE + 0x0C))
|
||||||
|
#define DAC_ANALOG (*(volatile uint32_t *)(DAC_BASE + 0x10))
|
||||||
|
|
||||||
|
#define ADC_BASE 0xB0110000
|
||||||
|
#define ADC_CTL (*(volatile uint32_t *)(ADC_BASE + 0x00))
|
||||||
|
#define ADC_FIFOCTL (*(volatile uint32_t *)(ADC_BASE + 0x04))
|
||||||
|
#define ADC_DAT (*(volatile uint32_t *)(ADC_BASE + 0x08))
|
||||||
|
#define ADC_DEBUG (*(volatile uint32_t *)(ADC_BASE + 0x0C))
|
||||||
|
#define ADC_ANALOG (*(volatile uint32_t *)(ADC_BASE + 0x10))
|
||||||
|
|
||||||
|
#define TP_BASE 0xB0120000
|
||||||
|
#define TP_CTL (*(volatile uint32_t *)(TP_BASE + 0x00))
|
||||||
|
#define TP_DAT (*(volatile uint32_t *)(TP_BASE + 0x04))
|
||||||
|
|
||||||
|
#define SPDIF_BASE 0xB0140000
|
||||||
|
#define SPDIF_CTL (*(volatile uint32_t *)(SPDIF_BASE + 0x00))
|
||||||
|
#define SPDIF_STAT (*(volatile uint32_t *)(SPDIF_BASE + 0x04))
|
||||||
|
#define SPDIF_TXDAT (*(volatile uint32_t *)(SPDIF_BASE + 0x08))
|
||||||
|
#define SPDIF_RXDAT (*(volatile uint32_t *)(SPDIF_BASE + 0x0C))
|
||||||
|
#define SPDIF_TXCSTAT (*(volatile uint32_t *)(SPDIF_BASE + 0x10))
|
||||||
|
#define SPDIF_RXCSTAT (*(volatile uint32_t *)(SPDIF_BASE + 0x14))
|
||||||
|
|
||||||
|
#define PCM_BASE 0xB0150000
|
||||||
|
#define PCM_CTL (*(volatile uint32_t *)(PCM_BASE + 0x00))
|
||||||
|
#define PCM_STAT (*(volatile uint32_t *)(PCM_BASE + 0x04))
|
||||||
|
#define PCM_RXDAT (*(volatile uint32_t *)(PCM_BASE + 0x08))
|
||||||
|
#define PCM_TXDAT (*(volatile uint32_t *)(PCM_BASE + 0x0C))
|
||||||
|
|
||||||
|
/* n = 0,1 */
|
||||||
|
#define UART_BASE(n) (0xB0160000 + (n<<5))
|
||||||
|
#define UART_CTL(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x00))
|
||||||
|
#define UART_RXDAT(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x04))
|
||||||
|
#define UART_TXDAT(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x08))
|
||||||
|
#define UART_STAT(n) (*(volatile uint32_t *)(UART_BASE(n) + 0x0C))
|
||||||
|
|
||||||
|
#define IR_PL (*(volatile uint32_t *)(UART_BASE(0) + 0x10))
|
||||||
|
#define IR_RBC (*(volatile uint32_t *)(UART_BASE(0) + 0x14))
|
||||||
|
|
||||||
|
/* n = 0,1 */
|
||||||
|
#define I2C_BASE(n) (0xB0180000 + (n<<5))
|
||||||
|
#define I2C_CTL(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x00))
|
||||||
|
#define I2C_CLKDIV(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x04))
|
||||||
|
#define I2C_STAT(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x08))
|
||||||
|
#define I2C_ADDR(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x0C))
|
||||||
|
#define I2C_DAT(n) (*(volatile uint32_t *)(I2C_BASE(n) + 0x10))
|
||||||
|
|
||||||
|
#define SPI_BASE 0xB0190000
|
||||||
|
#define SPI_CTL (*(volatile uint32_t *)(SPI_BASE + 0x00))
|
||||||
|
#define SPI_CLKDIV (*(volatile uint32_t *)(SPI_BASE + 0x04))
|
||||||
|
#define SPI_STAT (*(volatile uint32_t *)(SPI_BASE + 0x08))
|
||||||
|
#define SPI_RXDAT (*(volatile uint32_t *)(SPI_BASE + 0x0C))
|
||||||
|
#define SPI_TXDAT (*(volatile uint32_t *)(SPI_BASE + 0x10))
|
||||||
|
|
||||||
|
#define KEY_BASE 0xB01A0000
|
||||||
|
#define KEY_CTL (*(volatile uint32_t *)(KEY_BASE + 0x00))
|
||||||
|
#define KEY_DAT0 (*(volatile uint32_t *)(KEY_BASE + 0x04))
|
||||||
|
#define KEY_DAT1 (*(volatile uint32_t *)(KEY_BASE + 0x08))
|
||||||
|
#define KEY_DAT2 (*(volatile uint32_t *)(KEY_BASE + 0x0C))
|
||||||
|
#define KEY_DAT3 (*(volatile uint32_t *)(KEY_BASE + 0x10))
|
||||||
|
|
||||||
|
#define GPIO_BASE 0xB01C0000
|
||||||
|
#define GPIO_AOUTEN (*(volatile uint32_t *)(GPIO_BASE + 0x00))
|
||||||
|
#define GPIO_AINEN (*(volatile uint32_t *)(GPIO_BASE + 0x04))
|
||||||
|
#define GPIO_ADAT (*(volatile uint32_t *)(GPIO_BASE + 0x08))
|
||||||
|
#define GPIO_BOUTEN (*(volatile uint32_t *)(GPIO_BASE + 0x0C))
|
||||||
|
#define GPIO_BINEN (*(volatile uint32_t *)(GPIO_BASE + 0x10))
|
||||||
|
#define GPIO_BDAT (*(volatile uint32_t *)(GPIO_BASE + 0x14))
|
||||||
|
#define GPIO_MFCTL0 (*(volatile uint32_t *)(GPIO_BASE + 0x18))
|
||||||
|
#define GPIO_MFCTL1 (*(volatile uint32_t *)(GPIO_BASE + 0x1C))
|
||||||
98
utils/atj2137/adfuload/test_binary/lcm/crt0.S
Normal file
98
utils/atj2137/adfuload/test_binary/lcm/crt0.S
Normal file
|
|
@ -0,0 +1,98 @@
|
||||||
|
#include "mips.h"
|
||||||
|
|
||||||
|
.extern main
|
||||||
|
.global start
|
||||||
|
|
||||||
|
.set mips32r2
|
||||||
|
.set noreorder
|
||||||
|
.set noat
|
||||||
|
|
||||||
|
.section .init.text,"ax",%progbits
|
||||||
|
|
||||||
|
start:
|
||||||
|
di # disable interrupts
|
||||||
|
bltzal zero, load_addr # ra = PC + 8, branch not taken
|
||||||
|
nop
|
||||||
|
|
||||||
|
load_addr:
|
||||||
|
addiu v0, ra, -12 # calc real load address
|
||||||
|
# account for branch delay slot
|
||||||
|
# and very first 'di' instruction
|
||||||
|
lui t3, 0xa000 # use KSEG1 uncached unmapped
|
||||||
|
la t0, relocstart # addresses as we don't know
|
||||||
|
or t0, t0, t3 # the state of caches
|
||||||
|
la t1, relocend
|
||||||
|
or t1, t1, t3
|
||||||
|
beq t0, v0, cache_init # no relocation needed
|
||||||
|
nop
|
||||||
|
|
||||||
|
reloc_loop:
|
||||||
|
lw t2, 0(v0) # src
|
||||||
|
addiu v0, 4 # inc src addr
|
||||||
|
addiu t0, 4 # inc dst addr
|
||||||
|
bne t0, t1, reloc_loop
|
||||||
|
sw t2, -4(t0) # dst
|
||||||
|
|
||||||
|
cache_init:
|
||||||
|
# setup caches
|
||||||
|
# 4-way, 256 sets, 16 bytes cacheline I/D
|
||||||
|
li t0, 3 # enable cache for kseg0 accesses
|
||||||
|
mtc0 t0, C0_CONFIG
|
||||||
|
|
||||||
|
la t0, 0x80000000 # an idx op should use an unmappable address
|
||||||
|
ori t1, t0, 0x4000 # 16kB cache
|
||||||
|
mtc0 zero, C0_TAGLO
|
||||||
|
mtc0 zero, C0_TAGHI
|
||||||
|
|
||||||
|
cache_init_loop:
|
||||||
|
cache 8, 0(t0) # index store icache tag
|
||||||
|
cache 9, 0(t0) # index store dcache tag
|
||||||
|
addiu t0, t0, 0x10
|
||||||
|
bne t0, t1, cache_init_loop
|
||||||
|
nop
|
||||||
|
|
||||||
|
intc_setup:
|
||||||
|
li t0, 0xb0020000 # INTC base
|
||||||
|
lw zero, 4(t0) # INTC_MSK mask all interrupt sources
|
||||||
|
|
||||||
|
core_irq_setup:
|
||||||
|
li t0, 0x00404000 # BEV=1 for C0_EBASE setup, IM6=1, IE=0
|
||||||
|
mtc0 t0, C0_STATUS
|
||||||
|
|
||||||
|
la t0, _irqbase # vectors base address must be 4k aligned
|
||||||
|
mtc0 t0, C0_EBASE
|
||||||
|
|
||||||
|
li t0, 0x00004000
|
||||||
|
mtc0 t0, C0_STATUS # BEV=0, IM6=1, IE=0
|
||||||
|
|
||||||
|
li t1, 0x08800000
|
||||||
|
mtc0 t1, C0_CAUSE # DC=1, IV=1
|
||||||
|
mtc0 zero,C0_INTCTL # VS = 0
|
||||||
|
|
||||||
|
# clear bss
|
||||||
|
la t0, bssbegin
|
||||||
|
la t1, bssend
|
||||||
|
|
||||||
|
clear_bss_loop:
|
||||||
|
addiu t0, 4
|
||||||
|
bne t0, t1, clear_bss_loop
|
||||||
|
sw zero, -4(t0)
|
||||||
|
|
||||||
|
# setup stack
|
||||||
|
la k0, irqstackend
|
||||||
|
la sp, stackend
|
||||||
|
la t0, stackbegin
|
||||||
|
li t1, 0xdeadbeef
|
||||||
|
|
||||||
|
stack_munge_loop:
|
||||||
|
addiu t0, 4
|
||||||
|
bne t0, sp, stack_munge_loop
|
||||||
|
sw t1, -4(t0)
|
||||||
|
|
||||||
|
# jump to C code with enabled interrupts
|
||||||
|
la t0, main
|
||||||
|
jr t0
|
||||||
|
ei
|
||||||
|
|
||||||
|
.set at
|
||||||
|
.set reorder
|
||||||
93
utils/atj2137/adfuload/test_binary/lcm/irq_handler.S
Normal file
93
utils/atj2137/adfuload/test_binary/lcm/irq_handler.S
Normal file
|
|
@ -0,0 +1,93 @@
|
||||||
|
#include "mips.h"
|
||||||
|
/* s0-s7 not saved as this are callee saved registers
|
||||||
|
* CO_STATUS is not saved as nested interrupts are not supported
|
||||||
|
*
|
||||||
|
* Separate irqstack is used for context save and irq processing
|
||||||
|
* k0 holds the address of the top of this stack and k1 is used
|
||||||
|
* to hold original sp value. Since we do not support nesting
|
||||||
|
* there is nothing to warry about
|
||||||
|
*/
|
||||||
|
.extern irqvector
|
||||||
|
|
||||||
|
.global irq_handler
|
||||||
|
.set mips32r2
|
||||||
|
.set noreorder
|
||||||
|
.set noat
|
||||||
|
.section .irq_vector,"ax",%progbits
|
||||||
|
|
||||||
|
irq_handler:
|
||||||
|
move k1, sp
|
||||||
|
move sp, k0
|
||||||
|
addiu sp, sp, -84
|
||||||
|
|
||||||
|
/* context save */
|
||||||
|
sw AT, 0(sp)
|
||||||
|
sw v0, 4(sp)
|
||||||
|
sw v1, 8(sp)
|
||||||
|
sw a0, 12(sp)
|
||||||
|
sw a1, 16(sp)
|
||||||
|
sw a2, 20(sp)
|
||||||
|
sw a3, 24(sp)
|
||||||
|
sw t0, 28(sp)
|
||||||
|
sw t1, 32(sp)
|
||||||
|
sw t2, 36(sp)
|
||||||
|
sw t3, 40(sp)
|
||||||
|
sw t4, 44(sp)
|
||||||
|
sw t5, 48(sp)
|
||||||
|
sw t6, 52(sp)
|
||||||
|
sw t7, 56(sp)
|
||||||
|
sw t8, 60(sp)
|
||||||
|
sw t9, 64(sp)
|
||||||
|
sw fp, 68(sp)
|
||||||
|
sw ra, 72(sp)
|
||||||
|
|
||||||
|
mfhi t0
|
||||||
|
mflo t1
|
||||||
|
sw t0, 76(sp)
|
||||||
|
sw t1, 80(sp)
|
||||||
|
|
||||||
|
/* handle interrupt */
|
||||||
|
lui t0, 0xb002 /* INTC base */
|
||||||
|
lw t1, 0(t0) /* INTC_PD */
|
||||||
|
lw t2 , 4(t0) /* INTC_MSK */
|
||||||
|
and t1, t1, t2 /* mask */
|
||||||
|
clz t1, t1
|
||||||
|
sll t0, t1, 2 /* offset */
|
||||||
|
la t1, irqvector
|
||||||
|
addu t0, t1, t0 /* irq handler pointer address */
|
||||||
|
lw t0, 0(t0)
|
||||||
|
jalr t0 /* call handler function */
|
||||||
|
nop
|
||||||
|
|
||||||
|
/* context restore */
|
||||||
|
lw t0, 76(sp)
|
||||||
|
lw t1, 80(sp)
|
||||||
|
mthi t0
|
||||||
|
mtlo t1
|
||||||
|
|
||||||
|
lw AT, 0(sp)
|
||||||
|
lw v0, 4(sp)
|
||||||
|
lw v1, 8(sp)
|
||||||
|
lw a0, 12(sp)
|
||||||
|
lw a1, 16(sp)
|
||||||
|
lw a2, 20(sp)
|
||||||
|
lw a3, 24(sp)
|
||||||
|
lw t0, 28(sp)
|
||||||
|
lw t1, 32(sp)
|
||||||
|
lw t2, 36(sp)
|
||||||
|
lw t3, 40(sp)
|
||||||
|
lw t4, 44(sp)
|
||||||
|
lw t5, 48(sp)
|
||||||
|
lw t6, 52(sp)
|
||||||
|
lw t7, 56(sp)
|
||||||
|
lw t8, 60(sp)
|
||||||
|
lw t9, 64(sp)
|
||||||
|
lw fp, 68(sp)
|
||||||
|
lw ra, 72(sp)
|
||||||
|
|
||||||
|
addiu sp, sp, 84
|
||||||
|
move sp, k1
|
||||||
|
eret
|
||||||
|
|
||||||
|
.set reorder
|
||||||
|
.set at
|
||||||
2358
utils/atj2137/adfuload/test_binary/lcm/mips-archdefs.h
Normal file
2358
utils/atj2137/adfuload/test_binary/lcm/mips-archdefs.h
Normal file
File diff suppressed because it is too large
Load diff
820
utils/atj2137/adfuload/test_binary/lcm/mips.h
Normal file
820
utils/atj2137/adfuload/test_binary/lcm/mips.h
Normal file
|
|
@ -0,0 +1,820 @@
|
||||||
|
/**************************************************************************
|
||||||
|
* *
|
||||||
|
* PROJECT : MIPS port for uC/OS-II *
|
||||||
|
* *
|
||||||
|
* MODULE : MIPS.h *
|
||||||
|
* *
|
||||||
|
* AUTHOR : Michael Anburaj *
|
||||||
|
* URL : http://geocities.com/michaelanburaj/ *
|
||||||
|
* EMAIL: michaelanburaj@hotmail.com *
|
||||||
|
* *
|
||||||
|
* PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board *
|
||||||
|
* *
|
||||||
|
* TOOL-CHAIN : SDE & Cygnus *
|
||||||
|
* *
|
||||||
|
* DESCRIPTION : *
|
||||||
|
* MIPS processor definitions. *
|
||||||
|
* The basic CPU definitions are found in the file archdefs.h, which *
|
||||||
|
* is included by mips.h. *
|
||||||
|
* *
|
||||||
|
* mips.h implements aliases for some of the definitions in archdefs.h *
|
||||||
|
* and adds various definitions. *
|
||||||
|
* *
|
||||||
|
**************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __MIPS_H__
|
||||||
|
#define __MIPS_H__
|
||||||
|
|
||||||
|
#include "mips-archdefs.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* ********************************************************************* */
|
||||||
|
/* Module configuration */
|
||||||
|
|
||||||
|
|
||||||
|
/* ********************************************************************* */
|
||||||
|
/* Interface macro & data definition */
|
||||||
|
|
||||||
|
#ifndef MSK
|
||||||
|
#define MSK(n) ((1 << (n)) - 1)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CPU registers */
|
||||||
|
#define SYS_CPUREG_ZERO 0
|
||||||
|
#define SYS_CPUREG_AT 1
|
||||||
|
#define SYS_CPUREG_V0 2
|
||||||
|
#define SYS_CPUREG_V1 3
|
||||||
|
#define SYS_CPUREG_A0 4
|
||||||
|
#define SYS_CPUREG_A1 5
|
||||||
|
#define SYS_CPUREG_A2 6
|
||||||
|
#define SYS_CPUREG_A3 7
|
||||||
|
#define SYS_CPUREG_T0 8
|
||||||
|
#define SYS_CPUREG_T1 9
|
||||||
|
#define SYS_CPUREG_T2 10
|
||||||
|
#define SYS_CPUREG_T3 11
|
||||||
|
#define SYS_CPUREG_T4 12
|
||||||
|
#define SYS_CPUREG_T5 13
|
||||||
|
#define SYS_CPUREG_T6 14
|
||||||
|
#define SYS_CPUREG_T7 15
|
||||||
|
#define SYS_CPUREG_S0 16
|
||||||
|
#define SYS_CPUREG_S1 17
|
||||||
|
#define SYS_CPUREG_S2 18
|
||||||
|
#define SYS_CPUREG_S3 19
|
||||||
|
#define SYS_CPUREG_S4 20
|
||||||
|
#define SYS_CPUREG_S5 21
|
||||||
|
#define SYS_CPUREG_S6 22
|
||||||
|
#define SYS_CPUREG_S7 23
|
||||||
|
#define SYS_CPUREG_T8 24
|
||||||
|
#define SYS_CPUREG_T9 25
|
||||||
|
#define SYS_CPUREG_K0 26
|
||||||
|
#define SYS_CPUREG_K1 27
|
||||||
|
#define SYS_CPUREG_GP 28
|
||||||
|
#define SYS_CPUREG_SP 29
|
||||||
|
#define SYS_CPUREG_S8 30
|
||||||
|
#define SYS_CPUREG_FP SYS_CPUREG_S8
|
||||||
|
#define SYS_CPUREG_RA 31
|
||||||
|
|
||||||
|
|
||||||
|
/* CPU register fp ($30) has an alias s8 */
|
||||||
|
#define s8 fp
|
||||||
|
|
||||||
|
|
||||||
|
/* Aliases for System Control Coprocessor (CP0) registers */
|
||||||
|
#define C0_INDEX C0_Index
|
||||||
|
#define C0_RANDOM C0_Random
|
||||||
|
#define C0_ENTRYLO0 C0_EntryLo0
|
||||||
|
#define C0_ENTRYLO1 C0_EntryLo1
|
||||||
|
#define C0_CONTEXT C0_Context
|
||||||
|
#define C0_PAGEMASK C0_PageMask
|
||||||
|
#define C0_WIRED C0_Wired
|
||||||
|
#define C0_BADVADDR C0_BadVAddr
|
||||||
|
#define C0_COUNT C0_Count
|
||||||
|
#define C0_ENTRYHI C0_EntryHi
|
||||||
|
#define C0_COMPARE C0_Compare
|
||||||
|
#define C0_STATUS C0_Status
|
||||||
|
#define C0_CAUSE C0_Cause
|
||||||
|
|
||||||
|
#ifdef C0_PRID /* ArchDefs has an obsolete def. of C0_PRID */
|
||||||
|
#undef C0_PRID
|
||||||
|
#endif
|
||||||
|
#define C0_PRID C0_PRId
|
||||||
|
|
||||||
|
#define C0_CONFIG C0_Config
|
||||||
|
#define C0_CONFIG1 C0_Config1
|
||||||
|
#define C0_LLADDR C0_LLAddr
|
||||||
|
#define C0_WATCHLO C0_WatchLo
|
||||||
|
#define C0_WATCHHI C0_WatchHi
|
||||||
|
#define C0_DEBUG C0_Debug
|
||||||
|
#define C0_PERFCNT C0_PerfCnt
|
||||||
|
#define C0_ERRCTL C0_ErrCtl
|
||||||
|
#define C0_CACHEERR C0_CacheErr
|
||||||
|
#define C0_TAGLO C0_TagLo
|
||||||
|
#define C0_DATALO C0_DataLo
|
||||||
|
#define C0_TAGHI C0_TagHi
|
||||||
|
#define C0_DATAHI C0_DataHi
|
||||||
|
#define C0_ERROREPC C0_ErrorEPC
|
||||||
|
#if 0
|
||||||
|
#define C0_DESAVE C0_DESAVE
|
||||||
|
#define C0_EPC C0_EPC
|
||||||
|
#define C0_DEPC C0_DEPC
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* System Control Coprocessor (CP0) registers select fields */
|
||||||
|
#define C0_INDEX_SEL 0 /* TLB Index */
|
||||||
|
#define C0_RANDOM_SEL 0 /* TLB Random */
|
||||||
|
#define C0_TLBLO0_SEL 0 /* TLB EntryLo0 */
|
||||||
|
#define C0_TLBLO1_SEL 0 /* TLB EntryLo1 */
|
||||||
|
#define C0_CONTEXT_SEL 0 /* Context */
|
||||||
|
#define C0_PAGEMASK_SEL 0 /* TLB PageMask */
|
||||||
|
#define C0_WIRED_SEL 0 /* TLB Wired */
|
||||||
|
#define C0_BADVADDR_SEL 0 /* Bad Virtual Address */
|
||||||
|
#define C0_COUNT_SEL 0 /* Count */
|
||||||
|
#define C0_ENTRYHI_SEL 0 /* TLB EntryHi */
|
||||||
|
#define C0_COMPARE_SEL 0 /* Compare */
|
||||||
|
#define C0_STATUS_SEL 0 /* Processor Status */
|
||||||
|
#define C0_CAUSE_SEL 0 /* Exception Cause */
|
||||||
|
#define C0_EPC_SEL 0 /* Exception PC */
|
||||||
|
#define C0_PRID_SEL 0 /* Processor Revision Indentifier */
|
||||||
|
#define C0_CONFIG_SEL 0 /* Config */
|
||||||
|
#define C0_CONFIG1_SEL 1 /* Config1 */
|
||||||
|
#define C0_LLADDR_SEL 0 /* LLAddr */
|
||||||
|
#define C0_WATCHLO_SEL 0 /* WatchpointLo */
|
||||||
|
#define C0_WATCHHI_SEL 0 /* WatchpointHi */
|
||||||
|
#define C0_DEBUG_SEL 0 /* EJTAG Debug Register */
|
||||||
|
#define C0_DEPC_SEL 0 /* Program counter at last EJTAG debug exception */
|
||||||
|
#define C0_PERFCNT_SEL 0 /* Performance counter interface */
|
||||||
|
#define C0_ERRCTL_SEL 0 /* ERRCTL */
|
||||||
|
#define C0_CACHEERR_SEL 0 /* CacheErr */
|
||||||
|
#define C0_TAGLO_SEL 0 /* TagLo */
|
||||||
|
#define C0_DATALO_SEL 1 /* DataLo */
|
||||||
|
#define C0_DTAGLO_SEL 2 /* DTagLo */
|
||||||
|
#define C0_TAGHI_SEL 0 /* TagHi */
|
||||||
|
#define C0_DATAHI_SEL 1 /* DataHi */
|
||||||
|
#define C0_DTAGHI_SEL 2 /* DTagHi */
|
||||||
|
#define C0_ERROREPC_SEL 0 /* ErrorEPC */
|
||||||
|
#define C0_DESAVE_SEL 0 /* EJTAG dbg exc. save register */
|
||||||
|
|
||||||
|
|
||||||
|
/* C0_CONFIG register encoding */
|
||||||
|
|
||||||
|
#define C0_CONFIG_M_SHF S_ConfigMore
|
||||||
|
#define C0_CONFIG_M_MSK M_ConfigMore
|
||||||
|
#define C0_CONFIG_M_BIT C0_CONFIG_M_MSK
|
||||||
|
|
||||||
|
#define C0_CONFIG_BE_SHF S_ConfigBE
|
||||||
|
#define C0_CONFIG_BE_MSK M_ConfigBE
|
||||||
|
#define C0_CONFIG_BE_BIT C0_CONFIG_BE_MSK
|
||||||
|
|
||||||
|
#define C0_CONFIG_AT_SHF S_ConfigAT
|
||||||
|
#define C0_CONFIG_AT_MSK M_ConfigAT
|
||||||
|
#define C0_CONFIG_AT_MIPS32 K_ConfigAT_MIPS32
|
||||||
|
#define C0_CONFIG_AT_MIPS64_32ADDR K_ConfigAT_MIPS64S
|
||||||
|
#define C0_CONFIG_AT_MIPS64 K_ConfigAT_MIPS64
|
||||||
|
|
||||||
|
#define C0_CONFIG_AR_SHF S_ConfigAR
|
||||||
|
#define C0_CONFIG_AR_MSK M_ConfigAR
|
||||||
|
|
||||||
|
#define C0_CONFIG_MT_SHF S_ConfigMT
|
||||||
|
#define C0_CONFIG_MT_MSK M_ConfigMT
|
||||||
|
#define C0_CONFIG_MT_NONE K_ConfigMT_NoMMU
|
||||||
|
#define C0_CONFIG_MT_TLB K_ConfigMT_TLBMMU
|
||||||
|
#define C0_CONFIG_MT_BAT K_ConfigMT_BATMMU
|
||||||
|
#define C0_CONFIG_MT_NON_STD K_ConfigMT_FMMMU
|
||||||
|
|
||||||
|
#define C0_CONFIG_K0_SHF S_ConfigK0
|
||||||
|
#define C0_CONFIG_K0_MSK M_ConfigK0
|
||||||
|
#define C0_CONFIG_K0_WTHRU_NOALLOC K_CacheAttrCWTnWA
|
||||||
|
#define C0_CONFIG_K0_WTHRU_ALLOC K_CacheAttrCWTWA
|
||||||
|
#define C0_CONFIG_K0_UNCACHED K_CacheAttrU
|
||||||
|
#define C0_CONFIG_K0_NONCOHERENT K_CacheAttrCN
|
||||||
|
#define C0_CONFIG_K0_COHERENTXCL K_CacheAttrCCE
|
||||||
|
#define C0_CONFIG_K0_COHERENTXCLW K_CacheAttrCCS
|
||||||
|
#define C0_CONFIG_K0_COHERENTUPD K_CacheAttrCCU
|
||||||
|
#define C0_CONFIG_K0_UNCACHED_ACCEL K_CacheAttrUA
|
||||||
|
|
||||||
|
|
||||||
|
/* WC field.
|
||||||
|
*
|
||||||
|
* This feature is present specifically to support configuration
|
||||||
|
* testing of the core in a lead vehicle, and is not supported
|
||||||
|
* in any other environment. Attempting to use this feature
|
||||||
|
* outside of the scope of a lead vehicle is a violation of the
|
||||||
|
* MIPS Architecture, and may cause unpredictable operation of
|
||||||
|
* the processor.
|
||||||
|
*/
|
||||||
|
#define C0_CONFIG_WC_SHF 19
|
||||||
|
#define C0_CONFIG_WC_MSK (MSK(1) << C0_CONFIG_WC_SHF)
|
||||||
|
#define C0_CONFIG_WC_BIT C0_CONFIG_WC_MSK
|
||||||
|
|
||||||
|
|
||||||
|
/* C0_CONFIG1 register encoding */
|
||||||
|
|
||||||
|
#define C0_CONFIG1_MMUSIZE_SHF S_Config1MMUSize
|
||||||
|
#define C0_CONFIG1_MMUSIZE_MSK M_Config1MMUSize
|
||||||
|
|
||||||
|
#define C0_CONFIG1_IS_SHF S_Config1IS
|
||||||
|
#define C0_CONFIG1_IS_MSK M_Config1IS
|
||||||
|
|
||||||
|
#define C0_CONFIG1_IL_SHF S_Config1IL
|
||||||
|
#define C0_CONFIG1_IL_MSK M_Config1IL
|
||||||
|
|
||||||
|
#define C0_CONFIG1_IA_SHF S_Config1IA
|
||||||
|
#define C0_CONFIG1_IA_MSK M_Config1IA
|
||||||
|
|
||||||
|
#define C0_CONFIG1_DS_SHF S_Config1DS
|
||||||
|
#define C0_CONFIG1_DS_MSK M_Config1DS
|
||||||
|
|
||||||
|
#define C0_CONFIG1_DL_SHF S_Config1DL
|
||||||
|
#define C0_CONFIG1_DL_MSK M_Config1DL
|
||||||
|
|
||||||
|
#define C0_CONFIG1_DA_SHF S_Config1DA
|
||||||
|
#define C0_CONFIG1_DA_MSK M_Config1DA
|
||||||
|
|
||||||
|
#define C0_CONFIG1_WR_SHF S_Config1WR
|
||||||
|
#define C0_CONFIG1_WR_MSK M_Config1WR
|
||||||
|
#define C0_CONFIG1_WR_BIT C0_CONFIG1_WR_MSK
|
||||||
|
|
||||||
|
#define C0_CONFIG1_CA_SHF S_Config1CA
|
||||||
|
#define C0_CONFIG1_CA_MSK M_Config1CA
|
||||||
|
#define C0_CONFIG1_CA_BIT C0_CONFIG1_CA_MSK
|
||||||
|
|
||||||
|
#define C0_CONFIG1_EP_SHF S_Config1EP
|
||||||
|
#define C0_CONFIG1_EP_MSK M_Config1EP
|
||||||
|
#define C0_CONFIG1_EP_BIT C0_CONFIG1_EP_MSK
|
||||||
|
|
||||||
|
#define C0_CONFIG1_FP_SHF S_Config1FP
|
||||||
|
#define C0_CONFIG1_FP_MSK M_Config1FP
|
||||||
|
#define C0_CONFIG1_FP_BIT C0_CONFIG1_FP_MSK
|
||||||
|
|
||||||
|
|
||||||
|
/* C0_STATUS register encoding */
|
||||||
|
|
||||||
|
#define C0_STATUS_CU3_SHF S_StatusCU3
|
||||||
|
#define C0_STATUS_CU3_MSK M_StatusCU3
|
||||||
|
#define C0_STATUS_CU3_BIT C0_STATUS_CU3_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_CU2_SHF S_StatusCU2
|
||||||
|
#define C0_STATUS_CU2_MSK M_StatusCU2
|
||||||
|
#define C0_STATUS_CU2_BIT C0_STATUS_CU2_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_CU1_SHF S_StatusCU1
|
||||||
|
#define C0_STATUS_CU1_MSK M_StatusCU1
|
||||||
|
#define C0_STATUS_CU1_BIT C0_STATUS_CU1_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_CU0_SHF S_StatusCU1
|
||||||
|
#define C0_STATUS_CU0_MSK M_StatusCU1
|
||||||
|
#define C0_STATUS_CU0_BIT C0_STATUS_CU0_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_RP_SHF S_StatusRP
|
||||||
|
#define C0_STATUS_RP_MSK M_StatusRP
|
||||||
|
#define C0_STATUS_RP_BIT C0_STATUS_RP_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_FR_SHF S_StatusFR
|
||||||
|
#define C0_STATUS_FR_MSK M_StatusFR
|
||||||
|
#define C0_STATUS_FR_BIT C0_STATUS_FR_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_RE_SHF S_StatusRE
|
||||||
|
#define C0_STATUS_RE_MSK M_StatusRE
|
||||||
|
#define C0_STATUS_RE_BIT C0_STATUS_RE_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_BEV_SHF S_StatusBEV
|
||||||
|
#define C0_STATUS_BEV_MSK M_StatusBEV
|
||||||
|
#define C0_STATUS_BEV_BIT C0_STATUS_BEV_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_TS_SHF S_StatusTS
|
||||||
|
#define C0_STATUS_TS_MSK M_StatusTS
|
||||||
|
#define C0_STATUS_TS_BIT C0_STATUS_TS_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_SR_SHF S_StatusSR
|
||||||
|
#define C0_STATUS_SR_MSK M_StatusSR
|
||||||
|
#define C0_STATUS_SR_BIT C0_STATUS_SR_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_NMI_SHF S_StatusNMI
|
||||||
|
#define C0_STATUS_NMI_MSK M_StatusNMI
|
||||||
|
#define C0_STATUS_NMI_BIT C0_STATUS_NMI_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_IM_SHF S_StatusIM
|
||||||
|
#define C0_STATUS_IM_MSK M_StatusIM
|
||||||
|
/* Note that the the definitions below indicate the interrupt number
|
||||||
|
* rather than the mask.
|
||||||
|
* (0..1 for SW interrupts and 2...7 for HW interrupts)
|
||||||
|
*/
|
||||||
|
#define C0_STATUS_IM_SW0 (S_StatusIM0 - S_StatusIM)
|
||||||
|
#define C0_STATUS_IM_SW1 (S_StatusIM1 - S_StatusIM)
|
||||||
|
#define C0_STATUS_IM_HW0 (S_StatusIM2 - S_StatusIM)
|
||||||
|
#define C0_STATUS_IM_HW1 (S_StatusIM3 - S_StatusIM)
|
||||||
|
#define C0_STATUS_IM_HW2 (S_StatusIM4 - S_StatusIM)
|
||||||
|
#define C0_STATUS_IM_HW3 (S_StatusIM5 - S_StatusIM)
|
||||||
|
#define C0_STATUS_IM_HW4 (S_StatusIM6 - S_StatusIM)
|
||||||
|
#define C0_STATUS_IM_HW5 (S_StatusIM7 - S_StatusIM)
|
||||||
|
|
||||||
|
/* Max interrupt code */
|
||||||
|
#define C0_STATUS_IM_MAX C0_STATUS_IM_HW5
|
||||||
|
|
||||||
|
#define C0_STATUS_KSU_SHF S_StatusKSU
|
||||||
|
#define C0_STATUS_KSU_MSK M_StatusKSU
|
||||||
|
|
||||||
|
#define C0_STATUS_UM_SHF S_StatusUM
|
||||||
|
#define C0_STATUS_UM_MSK M_StatusUM
|
||||||
|
#define C0_STATUS_UM_BIT C0_STATUS_UM_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_ERL_SHF S_StatusERL
|
||||||
|
#define C0_STATUS_ERL_MSK M_StatusERL
|
||||||
|
#define C0_STATUS_ERL_BIT C0_STATUS_ERL_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_EXL_SHF S_StatusEXL
|
||||||
|
#define C0_STATUS_EXL_MSK M_StatusEXL
|
||||||
|
#define C0_STATUS_EXL_BIT C0_STATUS_EXL_MSK
|
||||||
|
|
||||||
|
#define C0_STATUS_IE_SHF S_StatusIE
|
||||||
|
#define C0_STATUS_IE_MSK M_StatusIE
|
||||||
|
#define C0_STATUS_IE_BIT C0_STATUS_IE_MSK
|
||||||
|
|
||||||
|
|
||||||
|
/* C0_PRID register encoding */
|
||||||
|
|
||||||
|
#define C0_PRID_OPT_SHF S_PRIdCoOpt
|
||||||
|
#define C0_PRID_OPT_MSK M_PRIdCoOpt
|
||||||
|
|
||||||
|
#define C0_PRID_COMP_SHF S_PRIdCoID
|
||||||
|
#define C0_PRID_COMP_MSK M_PRIdCoID
|
||||||
|
#define C0_PRID_COMP_MIPS K_PRIdCoID_MIPS
|
||||||
|
#define C0_PRID_COMP_NOT_MIPS32_64 0
|
||||||
|
|
||||||
|
#define C0_PRID_PRID_SHF S_PRIdImp
|
||||||
|
#define C0_PRID_PRID_MSK M_PRIdImp
|
||||||
|
|
||||||
|
/* Jade */
|
||||||
|
#define C0_PRID_PRID_4Kc K_PRIdImp_Jade
|
||||||
|
#define C0_PRID_PRID_4Kmp K_PRIdImp_JadeLite /* 4Km/4Kp */
|
||||||
|
/* Emerald */
|
||||||
|
#define C0_PRID_PRID_4KEc K_PRIdImp_4KEc
|
||||||
|
#define C0_PRID_PRID_4KEmp K_PRIdImp_4KEmp
|
||||||
|
/* Coral */
|
||||||
|
#define C0_PRID_PRID_4KSc K_PRIdImp_4KSc
|
||||||
|
/* Opal */
|
||||||
|
#define C0_PRID_PRID_5K K_PRIdImp_Opal
|
||||||
|
/* Ruby */
|
||||||
|
#define C0_PRID_PRID_20Kc K_PRIdImp_Ruby
|
||||||
|
/* Other CPUs */
|
||||||
|
#define C0_PRID_PRID_R4000 K_PRIdImp_R4000
|
||||||
|
#define C0_PRID_PRID_RM52XX K_PRIdImp_R5200
|
||||||
|
#define C0_PRID_PRID_RM70XX 0x27
|
||||||
|
|
||||||
|
#define C0_PRID_REV_SHF S_PRIdRev
|
||||||
|
#define C0_PRID_REV_MSK M_PRIdRev
|
||||||
|
|
||||||
|
|
||||||
|
#define MIPS_4Kc ( (C0_PRID_COMP_MIPS << \
|
||||||
|
C0_PRID_COMP_SHF) | \
|
||||||
|
(C0_PRID_PRID_4Kc << \
|
||||||
|
C0_PRID_PRID_SHF) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define MIPS_4Kmp ( (C0_PRID_COMP_MIPS << \
|
||||||
|
C0_PRID_COMP_SHF) | \
|
||||||
|
(C0_PRID_PRID_4Kmp << \
|
||||||
|
C0_PRID_PRID_SHF) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define MIPS_4KEc ( (C0_PRID_COMP_MIPS << \
|
||||||
|
C0_PRID_COMP_SHF) | \
|
||||||
|
(C0_PRID_PRID_4KEc << \
|
||||||
|
C0_PRID_PRID_SHF) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define MIPS_4KEmp ( (C0_PRID_COMP_MIPS << \
|
||||||
|
C0_PRID_COMP_SHF) | \
|
||||||
|
(C0_PRID_PRID_4KEmp << \
|
||||||
|
C0_PRID_PRID_SHF) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define MIPS_4KSc ( (C0_PRID_COMP_MIPS << \
|
||||||
|
C0_PRID_COMP_SHF) | \
|
||||||
|
(C0_PRID_PRID_4KSc << \
|
||||||
|
C0_PRID_PRID_SHF) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define MIPS_5K ( (C0_PRID_COMP_MIPS << \
|
||||||
|
C0_PRID_COMP_SHF) | \
|
||||||
|
(C0_PRID_PRID_5K << \
|
||||||
|
C0_PRID_PRID_SHF) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define MIPS_20Kc ( (C0_PRID_COMP_MIPS << \
|
||||||
|
C0_PRID_COMP_SHF) | \
|
||||||
|
(C0_PRID_PRID_20Kc << \
|
||||||
|
C0_PRID_PRID_SHF) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define QED_RM52XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \
|
||||||
|
C0_PRID_COMP_SHF) | \
|
||||||
|
(C0_PRID_PRID_RM52XX << \
|
||||||
|
C0_PRID_PRID_SHF) \
|
||||||
|
)
|
||||||
|
|
||||||
|
#define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \
|
||||||
|
C0_PRID_COMP_SHF) | \
|
||||||
|
(C0_PRID_PRID_RM70XX << \
|
||||||
|
C0_PRID_PRID_SHF) \
|
||||||
|
)
|
||||||
|
|
||||||
|
/* C0_ENTRYHI register encoding */
|
||||||
|
|
||||||
|
#define C0_ENTRYHI_VPN2_SHF S_EntryHiVPN2
|
||||||
|
#define C0_ENTRYHI_VPN2_MSK M_EntryHiVPN2
|
||||||
|
|
||||||
|
#define C0_ENTRYHI_ASID_SHF S_EntryHiASID
|
||||||
|
#define C0_ENTRYHI_ASID_MSK M_EntryHiASID
|
||||||
|
|
||||||
|
|
||||||
|
/* C0_CAUSE register encoding */
|
||||||
|
|
||||||
|
#define C0_CAUSE_BD_SHF S_CauseBD
|
||||||
|
#define C0_CAUSE_BD_MSK M_CauseBD
|
||||||
|
#define C0_CAUSE_BD_BIT C0_CAUSE_BD_MSK
|
||||||
|
|
||||||
|
#define C0_CAUSE_CE_SHF S_CauseCE
|
||||||
|
#define C0_CAUSE_CE_MSK M_CauseCE
|
||||||
|
|
||||||
|
#define C0_CAUSE_IV_SHF S_CauseIV
|
||||||
|
#define C0_CAUSE_IV_MSK M_CauseIV
|
||||||
|
#define C0_CAUSE_IV_BIT C0_CAUSE_IV_MSK
|
||||||
|
|
||||||
|
#define C0_CAUSE_WP_SHF S_CauseWP
|
||||||
|
#define C0_CAUSE_WP_MSK M_CauseWP
|
||||||
|
#define C0_CAUSE_WP_BIT C0_CAUSE_WP_MSK
|
||||||
|
|
||||||
|
#define C0_CAUSE_IP_SHF S_CauseIP
|
||||||
|
#define C0_CAUSE_IP_MSK M_CauseIP
|
||||||
|
|
||||||
|
#define C0_CAUSE_CODE_SHF S_CauseExcCode
|
||||||
|
#define C0_CAUSE_CODE_MSK M_CauseExcCode
|
||||||
|
|
||||||
|
#define C0_CAUSE_CODE_INT EX_INT
|
||||||
|
#define C0_CAUSE_CODE_MOD EX_MOD
|
||||||
|
#define C0_CAUSE_CODE_TLBL EX_TLBL
|
||||||
|
#define C0_CAUSE_CODE_TLBS EX_TLBS
|
||||||
|
#define C0_CAUSE_CODE_ADEL EX_ADEL
|
||||||
|
#define C0_CAUSE_CODE_ADES EX_ADES
|
||||||
|
#define C0_CAUSE_CODE_IBE EX_IBE
|
||||||
|
#define C0_CAUSE_CODE_DBE EX_DBE
|
||||||
|
#define C0_CAUSE_CODE_SYS EX_SYS
|
||||||
|
#define C0_CAUSE_CODE_BP EX_BP
|
||||||
|
#define C0_CAUSE_CODE_RI EX_RI
|
||||||
|
#define C0_CAUSE_CODE_CPU EX_CPU
|
||||||
|
#define C0_CAUSE_CODE_OV EX_OV
|
||||||
|
#define C0_CAUSE_CODE_TR EV_TR
|
||||||
|
#define C0_CAUSE_CODE_FPE EX_FPE
|
||||||
|
#define C0_CAUSE_CODE_WATCH EX_WATCH
|
||||||
|
#define C0_CAUSE_CODE_MCHECK EX_MCHECK
|
||||||
|
|
||||||
|
/* Max cause code */
|
||||||
|
#define C0_CAUSE_CODE_MAX EX_MCHECK
|
||||||
|
|
||||||
|
|
||||||
|
/* C0_PAGEMASK register encoding */
|
||||||
|
#define C0_PAGEMASK_MASK_SHF S_PageMaskMask
|
||||||
|
#define C0_PAGEMASK_MASK_MSK M_PageMaskMask
|
||||||
|
#define C0_PAGEMASK_MASK_4K K_PageMask4K
|
||||||
|
#define C0_PAGEMASK_MASK_16K K_PageMask16K
|
||||||
|
#define C0_PAGEMASK_MASK_64K K_PageMask64K
|
||||||
|
#define C0_PAGEMASK_MASK_256K K_PageMask256K
|
||||||
|
#define C0_PAGEMASK_MASK_1M K_PageMask1M
|
||||||
|
#define C0_PAGEMASK_MASK_4M K_PageMask4M
|
||||||
|
#define C0_PAGEMASK_MASK_16M K_PageMask16M
|
||||||
|
|
||||||
|
|
||||||
|
/* C0_ENTRYLO0 register encoding (equiv. to C0_ENTRYLO1) */
|
||||||
|
#define C0_ENTRYLO0_PFN_SHF S_EntryLoPFN
|
||||||
|
#define C0_ENTRYLO0_PFN_MSK M_EntryLoPFN
|
||||||
|
|
||||||
|
#define C0_ENTRYLO0_C_SHF S_EntryLoC
|
||||||
|
#define C0_ENTRYLO0_C_MSK M_EntryLoC
|
||||||
|
|
||||||
|
#define C0_ENTRYLO0_D_SHF S_EntryLoD
|
||||||
|
#define C0_ENTRYLO0_D_MSK M_EntryLoD
|
||||||
|
|
||||||
|
#define C0_ENTRYLO0_V_SHF S_EntryLoV
|
||||||
|
#define C0_ENTRYLO0_V_MSK M_EntryLoV
|
||||||
|
|
||||||
|
#define C0_ENTRYLO0_G_SHF S_EntryLoG
|
||||||
|
#define C0_ENTRYLO0_G_MSK M_EntryLoG
|
||||||
|
|
||||||
|
|
||||||
|
/* FPU (CP1) FIR register encoding */
|
||||||
|
#define C1_FIR_3D_SHF S_FIRConfig3D
|
||||||
|
#define C1_FIR_3D_MSK M_FIRConfig3D
|
||||||
|
|
||||||
|
#define C1_FIR_PS_SHF S_FIRConfigPS
|
||||||
|
#define C1_FIR_PS_MSK M_FIRConfigPS
|
||||||
|
|
||||||
|
#define C1_FIR_D_SHF S_FIRConfigD
|
||||||
|
#define C1_FIR_D_MSK M_FIRConfigD
|
||||||
|
|
||||||
|
#define C1_FIR_S_SHF S_FIRConfigS
|
||||||
|
#define C1_FIR_S_MSK M_FIRConfigS
|
||||||
|
|
||||||
|
#define C1_FIR_PRID_SHF S_FIRImp
|
||||||
|
#define C1_FIR_PRID_MSK M_FIRImp
|
||||||
|
|
||||||
|
#define C1_FIR_REV_SHF S_FIRRev
|
||||||
|
#define C1_FIR_REV_MSK M_FIRRev
|
||||||
|
|
||||||
|
|
||||||
|
/* FPU (CP1) FCSR control/status register */
|
||||||
|
#define C1_FCSR_FCC_SHF S_FCSRFCC7_1
|
||||||
|
#define C1_FCSR_FCC_MSK M_FCSRFCC7_1
|
||||||
|
|
||||||
|
#define C1_FCSR_FS_SHF S_FCSRFS
|
||||||
|
#define C1_FCSR_FS_MSK M_FCSRFS
|
||||||
|
#define C1_FCSR_FS_BIT C1_FCSR_FS_MSK
|
||||||
|
|
||||||
|
#define C1_FCSR_CC_SHF S_FCSRCC
|
||||||
|
#define C1_FCSR_CC_MSK M_FCSRCC
|
||||||
|
|
||||||
|
#define C1_FCSR_IMPL_SHF S_FCSRImpl
|
||||||
|
#define C1_FCSR_IMPL_MSK M_FCSRImpl
|
||||||
|
|
||||||
|
#define C1_FCSR_EXC_SHF S_FCSRExc
|
||||||
|
#define C1_FCSR_EXC_MSK M_FCSRExc
|
||||||
|
|
||||||
|
#define C1_FCSR_ENA_SHF S_FCSREna
|
||||||
|
#define C1_FCSR_ENA_MSK M_FCSREna
|
||||||
|
|
||||||
|
#define C1_FCSR_FLG_SHF S_FCSRFlg
|
||||||
|
#define C1_FCSR_FLG_MSK M_FCSRFlg
|
||||||
|
|
||||||
|
#define C1_FCSR_RM_SHF S_FCSRRM
|
||||||
|
#define C1_FCSR_RM_MSK M_FCSRRM
|
||||||
|
#define C1_FCSR_RM_RN K_FCSRRM_RN
|
||||||
|
#define C1_FCSR_RM_RZ K_FCSRRM_RZ
|
||||||
|
#define C1_FCSR_RM_RP K_FCSRRM_RP
|
||||||
|
#define C1_FCSR_RM_RM K_FCSRRM_RM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* cache operations */
|
||||||
|
|
||||||
|
#define CACHE_OP( code, type ) ( ((code) << 2) | (type) )
|
||||||
|
|
||||||
|
#define ICACHE_INDEX_INVALIDATE CACHE_OP(0x0, 0)
|
||||||
|
#define ICACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 0)
|
||||||
|
#define ICACHE_INDEX_STORE_TAG CACHE_OP(0x2, 0)
|
||||||
|
#define DCACHE_INDEX_WRITEBACK_INVALIDATE CACHE_OP(0x0, 1)
|
||||||
|
#define DCACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 1)
|
||||||
|
#define DCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 1)
|
||||||
|
#define SCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 3)
|
||||||
|
|
||||||
|
#define ICACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 0)
|
||||||
|
#define ICACHE_ADDR_FILL CACHE_OP(0x5, 0)
|
||||||
|
#define ICACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 0)
|
||||||
|
#define DCACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 1)
|
||||||
|
#define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 1)
|
||||||
|
#define DCACHE_ADDR_HIT_WRITEBACK CACHE_OP(0x6, 1)
|
||||||
|
#define DCACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 1)
|
||||||
|
|
||||||
|
#define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 3)
|
||||||
|
|
||||||
|
/* Workaround for bug in early revisions of MIPS 4K family of
|
||||||
|
* processors. Only relevant in early engineering samples of test
|
||||||
|
* chips (RTL revision <= 3.0).
|
||||||
|
*
|
||||||
|
* The bug is described in :
|
||||||
|
*
|
||||||
|
* MIPS32 4K(tm) Processor Core Family RTL Errata Sheet
|
||||||
|
* MIPS Document No: MD00003
|
||||||
|
*
|
||||||
|
* The bug is identified as : C16
|
||||||
|
*/
|
||||||
|
#ifndef SET_MIPS0
|
||||||
|
#define SET_MIPS0()
|
||||||
|
#define SET_PUSH()
|
||||||
|
#define SET_POP()
|
||||||
|
#endif
|
||||||
|
#define ICACHE_INVALIDATE_WORKAROUND(reg) \
|
||||||
|
SET_PUSH(); \
|
||||||
|
SET_MIPS0(); \
|
||||||
|
la reg, 999f; \
|
||||||
|
SET_POP(); \
|
||||||
|
cache ICACHE_ADDR_FILL, 0(reg); \
|
||||||
|
sync; \
|
||||||
|
nop; nop; nop; nop; \
|
||||||
|
999:
|
||||||
|
|
||||||
|
/* EMPTY_PIPELINE is used for the below cache invalidation operations.
|
||||||
|
* When $I is invalidated, there will still be operations in the
|
||||||
|
* pipeline. We make sure these are 'nop' operations.
|
||||||
|
*/
|
||||||
|
#define EMPTY_PIPELINE nop; nop; nop; nop
|
||||||
|
|
||||||
|
#define ICACHE_INDEX_INVALIDATE_OP(index,scratch) \
|
||||||
|
ICACHE_INVALIDATE_WORKAROUND(scratch); \
|
||||||
|
cache ICACHE_INDEX_INVALIDATE, 0(index); \
|
||||||
|
EMPTY_PIPELINE
|
||||||
|
|
||||||
|
#define ICACHE_ADDR_INVALIDATE_OP(addr,scratch) \
|
||||||
|
ICACHE_INVALIDATE_WORKAROUND(scratch); \
|
||||||
|
cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr); \
|
||||||
|
EMPTY_PIPELINE
|
||||||
|
|
||||||
|
/* The sync used in the below macro is there in case we are installing
|
||||||
|
* a new instruction (flush $D, sync, invalidate $I sequence).
|
||||||
|
*/
|
||||||
|
#define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg) \
|
||||||
|
cache SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg); \
|
||||||
|
sync; \
|
||||||
|
EMPTY_PIPELINE
|
||||||
|
|
||||||
|
/* Config1 cache field decoding */
|
||||||
|
#define CACHE_CALC_SPW(s) ( 64 << (s) )
|
||||||
|
#define CACHE_CALC_LS(l) ( (l) ? 2 << (l) : 0 )
|
||||||
|
#define CACHE_CALC_BPW(l,s) ( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) )
|
||||||
|
#define CACHE_CALC_ASSOC(a) ( (a) + 1 )
|
||||||
|
|
||||||
|
|
||||||
|
/**** Move from/to Coprocessor operations ****/
|
||||||
|
|
||||||
|
/* We use ssnop instead of nop operations in order to handle
|
||||||
|
* superscalar CPUs.
|
||||||
|
* The "sll zero,zero,1" notation is compiler backwards compatible.
|
||||||
|
*/
|
||||||
|
#define SSNOP sll zero,zero,1
|
||||||
|
#define NOPS SSNOP; SSNOP; SSNOP; SSNOP
|
||||||
|
|
||||||
|
#define MFLO(dst) \
|
||||||
|
mflo dst;\
|
||||||
|
NOPS
|
||||||
|
|
||||||
|
/* Workaround for bug in early revisions of MIPS 4K family of
|
||||||
|
* processors.
|
||||||
|
*
|
||||||
|
* This concerns the nop instruction before mtc0 in the
|
||||||
|
* MTC0 macro below.
|
||||||
|
*
|
||||||
|
* The bug is described in :
|
||||||
|
*
|
||||||
|
* MIPS32 4K(tm) Processor Core Family RTL Errata Sheet
|
||||||
|
* MIPS Document No: MD00003
|
||||||
|
*
|
||||||
|
* The bug is identified as : C27
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define MTC0(src, dst) \
|
||||||
|
nop; \
|
||||||
|
mtc0 src,dst;\
|
||||||
|
NOPS
|
||||||
|
|
||||||
|
#define DMTC0(src, dst) \
|
||||||
|
nop; \
|
||||||
|
dmtc0 src,dst;\
|
||||||
|
NOPS
|
||||||
|
|
||||||
|
#define MFC0(dst, src) \
|
||||||
|
mfc0 dst,src;\
|
||||||
|
NOPS
|
||||||
|
|
||||||
|
#define DMFC0(dst, src) \
|
||||||
|
dmfc0 dst,src;\
|
||||||
|
NOPS
|
||||||
|
|
||||||
|
#define MFC0_SEL_OPCODE(dst, src, sel)\
|
||||||
|
.##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel));\
|
||||||
|
NOPS
|
||||||
|
|
||||||
|
#define MTC0_SEL_OPCODE(dst, src, sel)\
|
||||||
|
.##word (0x40800000 | ((dst)<<16) | ((src)<<11) | (sel));\
|
||||||
|
NOPS
|
||||||
|
|
||||||
|
#define LDC1(dst, src, offs)\
|
||||||
|
.##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs))
|
||||||
|
|
||||||
|
#define SDC1(src, dst, offs)\
|
||||||
|
.##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs))
|
||||||
|
|
||||||
|
|
||||||
|
/* Instruction opcode fields */
|
||||||
|
#define OPC_SPECIAL 0x0
|
||||||
|
#define OPC_REGIM 0x1
|
||||||
|
#define OPC_J 0x2
|
||||||
|
#define OPC_JAL 0x3
|
||||||
|
#define OPC_BEQ 0x4
|
||||||
|
#define OPC_BNE 0x5
|
||||||
|
#define OPC_BLEZ 0x6
|
||||||
|
#define OPC_BGTZ 0x7
|
||||||
|
#define OPC_COP1 0x11
|
||||||
|
#define OPC_JALX 0x1D
|
||||||
|
#define OPC_BEQL 0x14
|
||||||
|
#define OPC_BNEL 0x15
|
||||||
|
#define OPC_BLEZL 0x16
|
||||||
|
#define OPC_BGTZL 0x17
|
||||||
|
|
||||||
|
/* Instruction function fields */
|
||||||
|
#define FUNC_JR 0x8
|
||||||
|
#define FUNC_JALR 0x9
|
||||||
|
|
||||||
|
/* Instruction rt fields */
|
||||||
|
#define RT_BLTZ 0x0
|
||||||
|
#define RT_BGEZ 0x1
|
||||||
|
#define RT_BLTZL 0x2
|
||||||
|
#define RT_BGEZL 0x3
|
||||||
|
#define RT_BLTZAL 0x10
|
||||||
|
#define RT_BGEZAL 0x11
|
||||||
|
#define RT_BLTZALL 0x12
|
||||||
|
#define RT_BGEZALL 0x13
|
||||||
|
|
||||||
|
/* Instruction rs fields */
|
||||||
|
#define RS_BC1 0x08
|
||||||
|
|
||||||
|
/* Access macros for instruction fields */
|
||||||
|
#define MIPS_OPCODE( instr) ((instr) >> 26)
|
||||||
|
#define MIPS_FUNCTION(instr) ((instr) & MSK(6))
|
||||||
|
#define MIPS_RT(instr) (((instr) >> 16) & MSK(5))
|
||||||
|
#define MIPS_RS(instr) (((instr) >> 21) & MSK(5))
|
||||||
|
#define MIPS_OFFSET(instr) ((instr) & 0xFFFF)
|
||||||
|
#define MIPS_TARGET(instr) ((instr) & MSK(26))
|
||||||
|
|
||||||
|
/* Instructions */
|
||||||
|
#define OPCODE_DERET 0x4200001f
|
||||||
|
#define OPCODE_BREAK 0x0005000d
|
||||||
|
#define OPCODE_NOP 0
|
||||||
|
#define OPCODE_JUMP(addr) ( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) )
|
||||||
|
|
||||||
|
#define DERET .##word OPCODE_DERET
|
||||||
|
|
||||||
|
/* MIPS16e opcodes and instruction field access macros */
|
||||||
|
|
||||||
|
#define MIPS16E_OPCODE(inst) (((inst) >> 11) & 0x1f)
|
||||||
|
#define MIPS16E_I8_FUNCTION(inst) (((inst) >> 8) & 0x7)
|
||||||
|
#define MIPS16E_X(inst) (((inst) >> 26) & 0x1)
|
||||||
|
#define MIPS16E_RR_FUNCTION(inst) (((inst) >> 0) & 0x1f)
|
||||||
|
#define MIPS16E_RY(inst) (((inst) >> 5) & 0x3)
|
||||||
|
#define MIPS16E_OPC_EXTEND 0x1e
|
||||||
|
#define MIPS16E_OPC_JAL_X 0x03
|
||||||
|
#define MIPS16E_OPC_B 0x02
|
||||||
|
#define MIPS16E_OPC_BEQZ 0x04
|
||||||
|
#define MIPS16E_OPC_BNEZ 0x05
|
||||||
|
#define MIPS16E_OPC_I8 0x0c
|
||||||
|
#define MIPS16E_I8_FUNC_BTEQZ 0x00
|
||||||
|
#define MIPS16E_I8_FUNC_BTNEZ 0x01
|
||||||
|
#define MIPS16E_X_JALX 0x01
|
||||||
|
#define MIPS16E_OPC_RR 0x1d
|
||||||
|
#define MIPS16E_RR_FUNC_JALRC 0x00
|
||||||
|
#define MIPS16E_RR_RY_JRRX 0x00
|
||||||
|
#define MIPS16E_RR_RY_JRRA 0x01
|
||||||
|
#define MIPS16E_RR_RY_JALR 0x02
|
||||||
|
#define MIPS16E_RR_RY_JRCRX 0x04
|
||||||
|
#define MIPS16E_RR_RY_JRCRA 0x05
|
||||||
|
#define MIPS16E_RR_RY_JALRC 0x06
|
||||||
|
|
||||||
|
#define MIPS16E_OPCODE_BREAK 0xE805
|
||||||
|
#define MIPS16E_OPCODE_NOP 0x6500
|
||||||
|
|
||||||
|
/* MIPS reset vector */
|
||||||
|
#define MIPS_RESET_VECTOR 0x1fc00000
|
||||||
|
|
||||||
|
/* Clock periods per count register increment */
|
||||||
|
#define MIPS4K_COUNT_CLK_PER_CYCLE 2
|
||||||
|
#define MIPS5K_COUNT_CLK_PER_CYCLE 2
|
||||||
|
#define MIPS20Kc_COUNT_CLK_PER_CYCLE 1
|
||||||
|
|
||||||
|
|
||||||
|
/**** MIPS 4K/5K families specific fields of CONFIG register ****/
|
||||||
|
|
||||||
|
#define C0_CONFIG_MIPS4K5K_K23_SHF S_ConfigK23
|
||||||
|
#define C0_CONFIG_MIPS4K5K_K23_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_K23_SHF)
|
||||||
|
|
||||||
|
#define C0_CONFIG_MIPS4K5K_KU_SHF S_ConfigKU
|
||||||
|
#define C0_CONFIG_MIPS4K5K_KU_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_KU_SHF)
|
||||||
|
|
||||||
|
|
||||||
|
/**** MIPS 20Kc specific fields of CONFIG register ****/
|
||||||
|
|
||||||
|
#define C0_CONFIG_MIPS20KC_EC_SHF 28
|
||||||
|
#define C0_CONFIG_MIPS20KC_EC_MSK (MSK(3) << C0_CONFIG_MIPS20KC_EC_SHF)
|
||||||
|
|
||||||
|
#define C0_CONFIG_MIPS20KC_DD_SHF 27
|
||||||
|
#define C0_CONFIG_MIPS20KC_DD_MSK (MSK(1) << C0_CONFIG_MIPS20KC_DD_SHF)
|
||||||
|
#define C0_CONFIG_MIPS20KC_DD_BIT C0_CONFIG_MIPS20KC_DD_MSK
|
||||||
|
|
||||||
|
#define C0_CONFIG_MIPS20KC_LP_SHF 26
|
||||||
|
#define C0_CONFIG_MIPS20KC_LP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_LP_SHF)
|
||||||
|
#define C0_CONFIG_MIPS20KC_LP_BIT C0_CONFIG_MIPS20KC_LP_MSK
|
||||||
|
|
||||||
|
#define C0_CONFIG_MIPS20KC_SP_SHF 25
|
||||||
|
#define C0_CONFIG_MIPS20KC_SP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_SP_SHF)
|
||||||
|
#define C0_CONFIG_MIPS20KC_SP_BIT C0_CONFIG_MIPS20KC_SP_MSK
|
||||||
|
|
||||||
|
#define C0_CONFIG_MIPS20KC_TI_SHF 24
|
||||||
|
#define C0_CONFIG_MIPS20KC_TI_MSK (MSK(1) << C0_CONFIG_MIPS20KC_TI_SHF)
|
||||||
|
#define C0_CONFIG_MIPS20KC_TI_BIT C0_CONFIG_MIPS20KC_TI_MSK
|
||||||
|
|
||||||
|
|
||||||
|
/* ********************************************************************* */
|
||||||
|
/* Interface function definition */
|
||||||
|
|
||||||
|
|
||||||
|
/* ********************************************************************* */
|
||||||
|
|
||||||
|
#endif /* #ifndef __MIPS_H__ */
|
||||||
1853
utils/atj2137/adfuload/test_binary/lcm/rockboxlogo.240x74x16.c
Normal file
1853
utils/atj2137/adfuload/test_binary/lcm/rockboxlogo.240x74x16.c
Normal file
File diff suppressed because it is too large
Load diff
63
utils/atj2137/adfuload/test_binary/lcm/system-atj213x.c
Normal file
63
utils/atj2137/adfuload/test_binary/lcm/system-atj213x.c
Normal file
|
|
@ -0,0 +1,63 @@
|
||||||
|
#define default_interrupt(name) \
|
||||||
|
extern __attribute__((weak,alias("UIRQ"))) void name (void)
|
||||||
|
|
||||||
|
default_interrupt(INT_MCA);
|
||||||
|
default_interrupt(INT_SD);
|
||||||
|
default_interrupt(INT_MHA);
|
||||||
|
/* default_interrupt(INT_USB); seems wrong */
|
||||||
|
default_interrupt(INT_DSP);
|
||||||
|
default_interrupt(INT_PCNT);
|
||||||
|
default_interrupt(INT_WD);
|
||||||
|
default_interrupt(INT_T1);
|
||||||
|
default_interrupt(INT_T0);
|
||||||
|
default_interrupt(INT_RTC);
|
||||||
|
default_interrupt(INT_DMA);
|
||||||
|
default_interrupt(INT_KEY);
|
||||||
|
default_interrupt(INT_EXT);
|
||||||
|
default_interrupt(INT_IIC2);
|
||||||
|
default_interrupt(INT_IIC1);
|
||||||
|
default_interrupt(INT_ADC);
|
||||||
|
default_interrupt(INT_DAC);
|
||||||
|
default_interrupt(INT_NAND);
|
||||||
|
default_interrupt(INT_YUV);
|
||||||
|
|
||||||
|
/* this will be panicf() on regular rockbox fw */
|
||||||
|
static void UIRQ(void)
|
||||||
|
{
|
||||||
|
while(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* TRICK ALERT !!!!
|
||||||
|
* The table is organized in reversed order so
|
||||||
|
* clz on INTC_PD returns the index in this table
|
||||||
|
*/
|
||||||
|
void (* const irqvector[])(void) __attribute__((used)) =
|
||||||
|
{
|
||||||
|
UIRQ, UIRQ, UIRQ, UIRQ, UIRQ, INT_YUV, UIRQ, INT_NAND,
|
||||||
|
UIRQ, INT_DAC, INT_ADC, UIRQ, UIRQ, INT_IIC1, INT_IIC2, UIRQ,
|
||||||
|
UIRQ, INT_EXT, INT_KEY, INT_DMA, INT_RTC, INT_T0, INT_T1, INT_WD,
|
||||||
|
INT_PCNT, UIRQ, INT_DSP, UIRQ, INT_MHA, INT_SD, UIRQ, INT_MCA
|
||||||
|
};
|
||||||
|
|
||||||
|
#define CPU_FREQ 60000000UL //???
|
||||||
|
void udelay(unsigned int usec)
|
||||||
|
{
|
||||||
|
unsigned int i = ((usec * CPU_FREQ) / 2000000);
|
||||||
|
asm volatile (
|
||||||
|
".set noreorder \n"
|
||||||
|
"1: \n"
|
||||||
|
"bne %0, $0, 1b \n"
|
||||||
|
"addiu %0, %0, -1 \n"
|
||||||
|
".set reorder \n"
|
||||||
|
: "=r" (i)
|
||||||
|
: "0" (i)
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
void mdelay(unsigned int msec)
|
||||||
|
{
|
||||||
|
unsigned int i;
|
||||||
|
for(i=0; i<msec; i++)
|
||||||
|
udelay(1000);
|
||||||
|
}
|
||||||
|
|
||||||
51
utils/atj2137/adfuload/test_binary/lcm/test.lds
Normal file
51
utils/atj2137/adfuload/test_binary/lcm/test.lds
Normal file
|
|
@ -0,0 +1,51 @@
|
||||||
|
OUTPUT_ARCH(mips)
|
||||||
|
ENTRY(main)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
|
||||||
|
|
||||||
|
.text 0xa0000000 :
|
||||||
|
{
|
||||||
|
relocstart = .;
|
||||||
|
*(.init.text*)
|
||||||
|
*(.text*)
|
||||||
|
}
|
||||||
|
|
||||||
|
. = ALIGN(0x1000);
|
||||||
|
_irqbase = .;
|
||||||
|
|
||||||
|
.exception_handlers :
|
||||||
|
{
|
||||||
|
. += 0x200;
|
||||||
|
*(.irq_vector*)
|
||||||
|
}
|
||||||
|
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
*(.rodata*)
|
||||||
|
*(.data*)
|
||||||
|
relocend = .;
|
||||||
|
}
|
||||||
|
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
bssbegin = .;
|
||||||
|
*(.sbss*)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
*(.scommon*)
|
||||||
|
bssend = .;
|
||||||
|
}
|
||||||
|
|
||||||
|
.stack (NOLOAD) :
|
||||||
|
{
|
||||||
|
stackbegin = .;
|
||||||
|
. += 0x2000;
|
||||||
|
stackend = .;
|
||||||
|
irqstackbegin = .;
|
||||||
|
. += 0x400;
|
||||||
|
irqstackend = .;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
316
utils/atj2137/adfuload/test_binary/lcm/test_lcm.c
Normal file
316
utils/atj2137/adfuload/test_binary/lcm/test_lcm.c
Normal file
|
|
@ -0,0 +1,316 @@
|
||||||
|
#include "mips.h"
|
||||||
|
#include "atj213x.h"
|
||||||
|
|
||||||
|
extern const unsigned short rockboxlogo[];
|
||||||
|
|
||||||
|
unsigned short framebuffer[320*240] __attribute__((aligned(32))) = {[0 ... 76799] = 0};
|
||||||
|
|
||||||
|
static void backlight_init(void)
|
||||||
|
{
|
||||||
|
/* backlight clock enable, select backlight clock as 32kHz */
|
||||||
|
CMU_FMCLK = (CMU_FMCLK & ~(CMU_FMCLK_BCLK_MASK)) | CMU_FMCLK_BCKE | CMU_FMCLK_BCLK_32K;
|
||||||
|
|
||||||
|
/* baclight enable */
|
||||||
|
PMU_CTL |= PMU_CTL_BL_EN;
|
||||||
|
|
||||||
|
/* pwm output, phase high, some initial duty cycle set as 24/32 */
|
||||||
|
PMU_CHG = ((PMU_CHG & ~PMU_CHG_PDOUT_MASK)| PMU_CHG_PBLS_PWM | PMU_CHG_PPHS_HIGH | PMU_CHG_PDUT(24));
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
static void backlight_set(int level)
|
||||||
|
{
|
||||||
|
/* set duty cycle in 1/32 units */
|
||||||
|
PMU_CHG = ((PMU_CHG & ~PMU_CHG_PDOUT_MASK) | PMU_CHG_PDUT(level));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void wdt_feed(void)
|
||||||
|
{
|
||||||
|
RTC_WDCTL |= RTC_WDCTL_CLR;
|
||||||
|
}
|
||||||
|
|
||||||
|
void set_sw_interrupt0(void)
|
||||||
|
{
|
||||||
|
unsigned int val;
|
||||||
|
asm volatile("mfc0 %0,$13" : "=r" (val));
|
||||||
|
val |= 0x100;
|
||||||
|
asm volatile("mtc0 %0,$13" : "+r" (val));
|
||||||
|
}
|
||||||
|
|
||||||
|
int lcm_wait_fifo_empty(void)
|
||||||
|
{
|
||||||
|
volatile int timeout = 100000;
|
||||||
|
|
||||||
|
while (--timeout)
|
||||||
|
if (YUV2RGB_CTL & 0x04)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void lcm_rs_command(void)
|
||||||
|
{
|
||||||
|
lcm_wait_fifo_empty();
|
||||||
|
|
||||||
|
YUV2RGB_CTL = 0x802ae;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void lcm_rs_data(void)
|
||||||
|
{
|
||||||
|
lcm_wait_fifo_empty();
|
||||||
|
|
||||||
|
YUV2RGB_CTL = 0x902ae;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void lcm_fb_data(void)
|
||||||
|
{
|
||||||
|
lcm_rs_command();
|
||||||
|
YUV2RGB_FIFODATA = 0x22; /* write GRAM command */
|
||||||
|
YUV2RGB_CTL = 0xa02ae; /* AHB bus write fifo */
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline lcd_reg_write(int reg, int val)
|
||||||
|
{
|
||||||
|
lcm_rs_command();
|
||||||
|
YUV2RGB_FIFODATA = reg;
|
||||||
|
lcm_rs_data();
|
||||||
|
YUV2RGB_FIFODATA = val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* strips off MIPS segment coding */
|
||||||
|
#define PHYADDR(x) ((x) & 0x1fffffff)
|
||||||
|
|
||||||
|
/* rb compat defines */
|
||||||
|
#define LCD_WIDTH 240
|
||||||
|
#define LCD_HEIGHT 320
|
||||||
|
#define FBADDR(x,y) ((short *)framebuffer + LCD_WIDTH*y + x)
|
||||||
|
|
||||||
|
static void lcd_set_gram_area(int x_start, int y_start,
|
||||||
|
int x_end, int y_end)
|
||||||
|
{
|
||||||
|
/* here we exploit the fact that width fits in LSB only */
|
||||||
|
lcd_reg_write(0x02, 0x00); /* column start MSB */
|
||||||
|
lcd_reg_write(0x03, x_start); /* column start LSB */
|
||||||
|
lcd_reg_write(0x04, 0x00); /* column end MSB */
|
||||||
|
lcd_reg_write(0x05, x_end); /* column end LSB */
|
||||||
|
|
||||||
|
lcd_reg_write(0x06, y_start>>8); /* row start MSB */
|
||||||
|
lcd_reg_write(0x07, y_start&0xff); /* row start LSB */
|
||||||
|
lcd_reg_write(0x08, y_end>>8); /* row end MSB */
|
||||||
|
lcd_reg_write(0x09, y_end&0xff); /* row end LSB */
|
||||||
|
}
|
||||||
|
|
||||||
|
void lcd_update_rect(int x, int y, int width, int height)
|
||||||
|
{
|
||||||
|
unsigned int end_x, end_y, row, col, *fbptr;
|
||||||
|
|
||||||
|
x &= ~1; /* we transfer 2px at once */
|
||||||
|
width = (width + 1) & ~1; /* adjust the width */
|
||||||
|
|
||||||
|
end_x = x + width - 1;
|
||||||
|
end_y = y + height - 1;
|
||||||
|
|
||||||
|
lcd_set_gram_area(x, y, end_x, end_y); /* set GRAM window */
|
||||||
|
lcm_fb_data(); /* prepare for AHB write to fifo */
|
||||||
|
|
||||||
|
for (row=y; row<=end_y; row++)
|
||||||
|
{
|
||||||
|
fbptr = (uint32_t *)FBADDR(x,row);
|
||||||
|
for (col=x; col<end_x; col+=2)
|
||||||
|
YUV2RGB_FIFODATA = *fbptr++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* for reference
|
||||||
|
* When in act213x_fb_data()
|
||||||
|
* YUV2RGB_CTL = 0xa02ae; -> DMA0-3 (AHB bus)
|
||||||
|
* YUV2RGB_CTL = 0xa00ae; -> DMA4-7 (special bus)
|
||||||
|
*/
|
||||||
|
static void lcd_update_dma(void)
|
||||||
|
{
|
||||||
|
lcd_set_gram_area(0, 0, LCD_WIDTH-1, LCD_HEIGHT-1);
|
||||||
|
|
||||||
|
/* AHB bus DMA channels are 0-3 */
|
||||||
|
DMA_MODE(0) = (0x00<<29) | /* dst burst length = single */
|
||||||
|
(0x00<<28) | /* DMA no reload */
|
||||||
|
(0x00<<27) | /* dst DSP mode disable */
|
||||||
|
(0x00<<26) | /* dst row mode */
|
||||||
|
(0x00<<25) | /* dst address count dir - don't care */
|
||||||
|
(0x01<<24) | /* dst fixed address */
|
||||||
|
(0x18<<19) | /* dst DRQ trig source LCM */
|
||||||
|
(0x02<<17) | /* dst transfer width 32bits */
|
||||||
|
(0x01<<16) | /* dst transfer fixed size chunks */
|
||||||
|
(0x05<<13) | /* src burst length = incr8 */
|
||||||
|
(0x00<<12) | /* reserved */
|
||||||
|
(0x00<<11) | /* src DSP mode disable */
|
||||||
|
(0x00<<10) | /* src row mode */
|
||||||
|
(0x00<<9) | /* src address count dir - increase */
|
||||||
|
(0x00<<8) | /* src address not fixed */
|
||||||
|
(0x10<<3) | /* src DRQ trig source SDRAM */
|
||||||
|
(0x02<<1) | /* src transfer width 32bit */
|
||||||
|
(0x00<<0); /* src transfer not in fixed chunks */
|
||||||
|
|
||||||
|
DMA_SRC(0) = PHYADDR((uint32_t)framebuffer);
|
||||||
|
DMA_DST(0) = PHYADDR((uint32_t)&YUV2RGB_FIFODATA);
|
||||||
|
|
||||||
|
DMA_CNT(0) = 240*320*2; /* in bytes */
|
||||||
|
DMA_CMD(0) = 1; /* start dma operation */
|
||||||
|
}
|
||||||
|
|
||||||
|
static lcm_init(void)
|
||||||
|
{
|
||||||
|
CMU_DEVCLKEN |= (1<<8)|(1<<1); /* dma clk, lcm clk */
|
||||||
|
CMU_DMACLK = 1; /* DMA4 clock enable */
|
||||||
|
|
||||||
|
/* reset DMA4 */
|
||||||
|
DMAC_CTL |= (1<<20);
|
||||||
|
udelay(1);
|
||||||
|
DMAC_CTL &= ~(1<<20);
|
||||||
|
|
||||||
|
GPIO_MFCTL1 = (1<<31); // enable multifunction
|
||||||
|
GPIO_MFCTL0 = (GPIO_MFCTL0 & ~(0x07<<22 | 0x03<<14 | 0x03<<6 | 0x07<<3 | 0x07)) | // 0xfe3f3f00
|
||||||
|
0x02<<22 | 0x02<<14 | 0x02<<6 | 0x02<<3|0x02; // 0x808092
|
||||||
|
udelay(1);
|
||||||
|
|
||||||
|
lcm_rs_command(); /* this has side effect of enabling whole block */
|
||||||
|
YUV2RGB_CLKCTL = 0x102; /* lcm clock divider */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* google says COG-IZT2298 is 2.8" lcd module */
|
||||||
|
static lcd_init(void)
|
||||||
|
{
|
||||||
|
int x,y;
|
||||||
|
|
||||||
|
/* lcd reset pin GPIOA16 */
|
||||||
|
GPIO_AOUTEN |= (1<<16);
|
||||||
|
GPIO_ADAT |= (1<<16);
|
||||||
|
mdelay(10);
|
||||||
|
GPIO_ADAT &= ~(1<<16);
|
||||||
|
mdelay(10);
|
||||||
|
GPIO_ADAT |= (1<<16);
|
||||||
|
mdelay(10);
|
||||||
|
|
||||||
|
/* lcd controller init sequence matching HX8347-D */
|
||||||
|
lcd_reg_write(0xea, 0x00);
|
||||||
|
lcd_reg_write(0xeb, 0x20);
|
||||||
|
lcd_reg_write(0xec, 0x0f);
|
||||||
|
lcd_reg_write(0xed, 0xc4);
|
||||||
|
lcd_reg_write(0xe8, 0xc4);
|
||||||
|
lcd_reg_write(0xe9, 0xc4);
|
||||||
|
lcd_reg_write(0xf1, 0xc4);
|
||||||
|
lcd_reg_write(0xf2, 0xc4);
|
||||||
|
lcd_reg_write(0x27, 0xc4);
|
||||||
|
lcd_reg_write(0x40, 0x00); /* gamma block start */
|
||||||
|
lcd_reg_write(0x41, 0x00);
|
||||||
|
lcd_reg_write(0x42, 0x01);
|
||||||
|
lcd_reg_write(0x43, 0x13);
|
||||||
|
lcd_reg_write(0x44, 0x10);
|
||||||
|
lcd_reg_write(0x45, 0x26);
|
||||||
|
lcd_reg_write(0x46, 0x08);
|
||||||
|
lcd_reg_write(0x47, 0x51);
|
||||||
|
lcd_reg_write(0x48, 0x02);
|
||||||
|
lcd_reg_write(0x49, 0x12);
|
||||||
|
lcd_reg_write(0x4a, 0x18);
|
||||||
|
lcd_reg_write(0x4b, 0x19);
|
||||||
|
lcd_reg_write(0x4c, 0x14);
|
||||||
|
lcd_reg_write(0x50, 0x19);
|
||||||
|
lcd_reg_write(0x51, 0x2f);
|
||||||
|
lcd_reg_write(0x52, 0x2c);
|
||||||
|
lcd_reg_write(0x53, 0x3e);
|
||||||
|
lcd_reg_write(0x54, 0x3f);
|
||||||
|
lcd_reg_write(0x55, 0x3f);
|
||||||
|
lcd_reg_write(0x56, 0x2e);
|
||||||
|
lcd_reg_write(0x57, 0x77);
|
||||||
|
lcd_reg_write(0x58, 0x0b);
|
||||||
|
lcd_reg_write(0x59, 0x06);
|
||||||
|
lcd_reg_write(0x5a, 0x07);
|
||||||
|
lcd_reg_write(0x5b, 0x0d);
|
||||||
|
lcd_reg_write(0x5c, 0x1d);
|
||||||
|
lcd_reg_write(0x5d, 0xcc); /* gamma block end */
|
||||||
|
lcd_reg_write(0x1b, 0x1b);
|
||||||
|
lcd_reg_write(0x1a, 0x01);
|
||||||
|
lcd_reg_write(0x24, 0x2f);
|
||||||
|
lcd_reg_write(0x25, 0x57);
|
||||||
|
lcd_reg_write(0x23, 0x86);
|
||||||
|
lcd_reg_write(0x18, 0x36); /* 70Hz framerate */
|
||||||
|
lcd_reg_write(0x19, 0x01); /* osc enable */
|
||||||
|
lcd_reg_write(0x01, 0x00);
|
||||||
|
lcd_reg_write(0x1f, 0x88);
|
||||||
|
mdelay(5);
|
||||||
|
lcd_reg_write(0x1f, 0x80);
|
||||||
|
mdelay(5);
|
||||||
|
lcd_reg_write(0x1f, 0x90);
|
||||||
|
mdelay(5);
|
||||||
|
lcd_reg_write(0x1f, 0xd0);
|
||||||
|
mdelay(5);
|
||||||
|
lcd_reg_write(0x17, 0x05); /* 16bpp */
|
||||||
|
lcd_reg_write(0x36, 0x00);
|
||||||
|
lcd_reg_write(0x28, 0x38);
|
||||||
|
mdelay(40);
|
||||||
|
lcd_reg_write(0x28, 0x3c);
|
||||||
|
|
||||||
|
lcd_reg_write(0x02, 0x00); /* column start MSB */
|
||||||
|
lcd_reg_write(0x03, 0x00); /* column start LSB */
|
||||||
|
lcd_reg_write(0x04, 0x00); /* column end MSB */
|
||||||
|
lcd_reg_write(0x05, 0xef); /* column end LSB */
|
||||||
|
lcd_reg_write(0x06, 0x00); /* row start MSB */
|
||||||
|
lcd_reg_write(0x07, 0x00); /* row start LSB */
|
||||||
|
lcd_reg_write(0x08, 0x01); /* row end MSB */
|
||||||
|
lcd_reg_write(0x09, 0x3f); /* row end LSB */
|
||||||
|
|
||||||
|
lcm_fb_data(); /* prepare for DMA write to fifo */
|
||||||
|
|
||||||
|
/* clear lcd gram */
|
||||||
|
for (y=0; y<LCD_HEIGHT; y++)
|
||||||
|
for (x=0; x<(LCD_WIDTH>>1); x++)
|
||||||
|
YUV2RGB_FIFODATA = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int main(void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
RTC_WDCTL &= ~(1<<4); /* disable WDT */
|
||||||
|
|
||||||
|
/* Configure T0 interrupt as IP6. IP6 is unmasked in crt0.S */
|
||||||
|
INTC_CFG0 = 0;
|
||||||
|
INTC_CFG1 = 0;
|
||||||
|
INTC_CFG2 = (1<<10);
|
||||||
|
|
||||||
|
/* unmask T0 source in INTC */
|
||||||
|
INTC_MSK |= (1<<10);
|
||||||
|
|
||||||
|
backlight_init();
|
||||||
|
|
||||||
|
/* copy rb logo image */
|
||||||
|
for (i=0; i<240*74; i++)
|
||||||
|
framebuffer[i] = rockboxlogo[i];
|
||||||
|
|
||||||
|
lcm_init();
|
||||||
|
lcd_init();
|
||||||
|
lcd_update_rect(0,0,240,74);
|
||||||
|
|
||||||
|
/* ADEC_N63.BIN seems to setup P_CLK as 7.5MHz which is timer clk */
|
||||||
|
RTC_T0 = (7500000*10/32); /* with this we should see transition every ~0.3125s and 'black' every ~10s */
|
||||||
|
RTC_T0CTL = (1<<5) | (1<<2) | (1<<1) | (1<<0); /* timer enable, timer reload, timer irq, clear irq pending bit */
|
||||||
|
|
||||||
|
while(1)
|
||||||
|
{
|
||||||
|
/* otherwise wdt will trigger reset */
|
||||||
|
//wdt_feed();
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Timer T0 interrupt service routine */
|
||||||
|
INT_T0()
|
||||||
|
{
|
||||||
|
static int j = 0;
|
||||||
|
|
||||||
|
/* clear pending bit in timer module */
|
||||||
|
RTC_T0CTL |= 1;
|
||||||
|
|
||||||
|
/* change backligh */
|
||||||
|
backlight_set(++j);
|
||||||
|
}
|
||||||
Loading…
Add table
Add a link
Reference in a new issue