forked from len0rd/rockbox
Coldfire targets: Adjusted PLL settings (lowest possible VCO clock for each setting) and IDE timing (especially it's faster now on M5+X5). * Added/updated table showing the necessary settings (PLL, refresh, waitstates, IDE timing) for each possible clock frequency.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13230 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
b1f0049307
commit
c49d5dd631
2 changed files with 48 additions and 23 deletions
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@ -24,6 +24,28 @@
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#include "timer.h"
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#include "pcf50606.h"
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/* Settings for all possible clock frequencies (with properly working timers)
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*
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* xxx_REFRESH_TIMER below
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* system.h, CPUFREQ_xxx_MULT |
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* | |
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* V V
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* PLLCR & Rftim. IDECONFIG1/IDECONFIG2
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* CPUCLK/Hz MULT ~0x70c00000 16MB CSCR0 CSCR1 CS2Pre CS2Post CS2Wait
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* -------------------------------------------------------------------------
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* 11289600 1 0x00000200 4 0x0180 0x0180 1 1 0
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* 22579200 2 0x05028049 10 0x0180 0x0180 1 1 0
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* 33868800 3 0x03024049 15 0x0180 0x0180 1 1 0
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* 45158400 4 0x05028045 21 0x0180 0x0180 1 1 0
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* 56448000 5 0x02028049 26 0x0580 0x0580 2 1 0
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* 67737600 6 0x03024045 32 0x0580 0x0980 2 1 0
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* 79027200 7 0x0302a045 37 0x0580 0x0d80 2 1 0
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* 90316800 8 0x03030045 43 0x0980 0x0d80 2 1 0
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* 101606400 9 0x01024049 48 0x0980 0x1180 2 1 0
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* 112896000 10 0x01028049 54 0x0980 0x1580 3 1 0
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* 124185600 11 0x0102c049 59 0x0980 0x1180 3 1 1
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*/
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#define MAX_REFRESH_TIMER 59
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#define NORMAL_REFRESH_TIMER 21
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#define DEFAULT_REFRESH_TIMER 4
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@ -42,7 +64,7 @@ void set_cpu_frequency(long frequency)
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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RECALC_DELAYS(CPUFREQ_MAX);
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PLLCR = 0x03042045 | (PLLCR & 0x70C00000);
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PLLCR = 0x0102c049 | (PLLCR & 0x70C00000);
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CSCR0 = 0x00001180; /* Flash: 4 wait states */
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CSCR1 = 0x00000980; /* LCD: 2 wait states */
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while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
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@ -50,7 +72,8 @@ void set_cpu_frequency(long frequency)
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timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
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DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_MAX;
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IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
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IDECONFIG1 = 0x100000 | (1 << 13) | (3 << 10);
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/* BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
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break;
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@ -60,7 +83,7 @@ void set_cpu_frequency(long frequency)
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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RECALC_DELAYS(CPUFREQ_NORMAL);
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PLLCR = 0x06030045 | (PLLCR & 0x70C00000);
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PLLCR = 0x05028045 | (PLLCR & 0x70C00000);
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CSCR0 = 0x00000580; /* Flash: 1 wait state */
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
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@ -68,7 +91,8 @@ void set_cpu_frequency(long frequency)
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timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
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DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_NORMAL;
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IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
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IDECONFIG1 = 0x100000 | (1 << 13) | (1 << 10);
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/* BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
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break;
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default:
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@ -83,7 +107,8 @@ void set_cpu_frequency(long frequency)
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_DEFAULT;
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IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
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IDECONFIG1 = 0x100000 | (1 << 13) | (1 << 10);
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/* BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
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break;
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}
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@ -31,20 +31,20 @@
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* system.h, CPUFREQ_xxx_MULT |
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* | |
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* V V
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* Refreshtim. IDECONFIG1/IDECONFIG2
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* CPUCLK/Hz MULT PLLCR 16MB 32MB CSCR0 CSCR1 CSCR3 CS2Pre CS2Post CS2Wait
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* PLLCR & Refreshtim. IDECONFIG1/IDECONFIG2
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* CPUCLK/Hz MULT ~0x70400000 16MB 32MB CSCR0 CSCR1 CSCR3 CS2Pre CS2Post CS2Wait
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* ---------------------------------------------------------------------------------------
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* 11289600 1 0x10c00200 4 1 0x0180 0x0180 0x0180 1 0 0
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* 22579200 2 0x15c9e025 10 4 0x0180 0x0180 0x0180 1 0 0
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* 33868800 3 0x13c8e025 15 7 0x0180 0x0180 0x0180 1 0 0
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* 45158400 4 0x15c9e021 21 10 0x0580 0x0180 0x0580 1 0 0
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* 56448000 5 0x12c9e025 26 12 0x0580 0x0980
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* 67737600 6 0x13c8e021 32 15 0x0980 0x0d80
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* 79027200 7 0x13ca6021 37 18 0x0980 0x1180
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* 90316800 8 0x13cbe021 43 21 0x0d80 0x1580
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* 101606400 9 0x11c92025 48 23 0x0d80 0x1980
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* 112896000 10 0x11c9e025 54 26 0x1180 0x1d80
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* 124185600 11 0x11cae025 59 29 0x1180 0x1180 0x2180 2 1 2
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* 11289600 1 0x00800200 4 1 0x0180 0x0180 0x0180 1 1 0
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* 22579200 2 0x0589e025 10 4 0x0180 0x0180 0x0180 1 1 0
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* 33868800 3 0x0388e025 15 7 0x0180 0x0180 0x0180 1 1 0
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* 45158400 4 0x0589e021 21 10 0x0580 0x0180 0x0580 1 1 0
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* 56448000 5 0x0289e025 26 12 0x0580 0x0580 0x0980 2 1 0
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* 67737600 6 0x0388e021 32 15 0x0980 0x0980 0x0d80 2 1 0
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* 79027200 7 0x038a6021 37 18 0x0980 0x0d80 0x1180 2 1 0
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* 90316800 8 0x038be021 43 21 0x0d80 0x0d80 0x1580 2 1 0
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* 101606400 9 0x01892025 48 23 0x0d80 0x1180 0x1980 2 1 0
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* 112896000 10 0x0189e025 54 26 0x1180 0x1580 0x1d80 3 1 0
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* 124185600 11 0x018ae025 59 29 0x1180 0x1580 0x2180 3 1 1
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*/
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#if MEM < 32
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@ -93,9 +93,9 @@ void set_cpu_frequency(long frequency)
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timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
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DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_MAX;
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IDECONFIG1 = 0x10100000 | (1 << 13) | (2 << 10);
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IDECONFIG1 = 0x10100000 | (1 << 13) | (3 << 10);
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/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (2 << 8); /* TA enable + CS2wait */
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IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
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#ifdef HAVE_SERIAL
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UBG10 = BAUDRATE_DIV_MAX >> 8;
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@ -109,7 +109,7 @@ void set_cpu_frequency(long frequency)
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PLLCR &= ~1; /* Bypass mode */
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timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false);
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RECALC_DELAYS(CPUFREQ_NORMAL);
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PLLCR = 0x038be025 | (PLLCR & 0x70400000);
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PLLCR = 0x0589e021 | (PLLCR & 0x70400000);
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CSCR0 = 0x00000580; /* Flash: 1 wait state */
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CSCR1 = 0x00000180; /* LCD: 0 wait states */
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#if CONFIG_USBOTG == USBOTG_ISP1362
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@ -120,7 +120,7 @@ void set_cpu_frequency(long frequency)
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timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
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DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_NORMAL;
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IDECONFIG1 = 0x10100000 | (0 << 13) | (1 << 10);
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IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10);
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/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
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@ -144,7 +144,7 @@ void set_cpu_frequency(long frequency)
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#endif
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DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
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cpu_frequency = CPUFREQ_DEFAULT;
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IDECONFIG1 = 0x10100000 | (0 << 13) | (1 << 10);
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IDECONFIG1 = 0x10100000 | (1 << 13) | (1 << 10);
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/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
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IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
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