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hwstub: Force alignment of the context buffer

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Exception handling code assumes at least word alignment of the
context buffer. So far we were lucky that compiler placed it
correctly but after compiler upgrade I was hit by the bug
caused by missalignment of the context buffer.

Credit goes to pamaury
This commit is contained in:
Marcin Bukat 2023-09-27 22:25:06 +02:00
parent 4c533475d8
commit bf81914217
1 changed files with 14 additions and 13 deletions
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27
utils/hwstub/stub/asm/mips/system.S
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@ -25,6 +25,7 @@
* the code can register a "longjmp" buffer to restore the context in case of * the code can register a "longjmp" buffer to restore the context in case of
* fault */ * fault */
.data .data
.align 4
.global exception_jmp_ctx_ptr .global exception_jmp_ctx_ptr
exception_jmp_ctx_ptr: exception_jmp_ctx_ptr:
/* buffer contains in order: s0-s7, sp, s8, ra */ /* buffer contains in order: s0-s7, sp, s8, ra */
@ -56,19 +57,19 @@ set_exception_jmp:
* a0: exception type (EXCEPTION_*) */ * a0: exception type (EXCEPTION_*) */
.global restore_exception_jmp .global restore_exception_jmp
restore_exception_jmp: restore_exception_jmp:
la k1, exception_jmp_ctx_ptr la v0, exception_jmp_ctx_ptr
lw s0, 0(k1) lw s0, 0(v0)
lw s1, 4(k1) lw s1, 4(v0)
lw s2, 8(k1) lw s2, 8(v0)
lw s3, 12(k1) lw s3, 12(v0)
lw s4, 16(k1) lw s4, 16(v0)
lw s5, 20(k1) lw s5, 20(v0)
lw s6, 24(k1) lw s6, 24(v0)
lw s7, 28(k1) lw s7, 28(v0)
lw sp, 32(k1) lw sp, 32(v0)
lw s8, 36(k1) lw s8, 36(v0)
lw k1, 40(k1) lw v0, 40(v0)
mtc0 k1, C0_EPC mtc0 v0, C0_EPC
#ifdef CONFIG_JZ4760B #ifdef CONFIG_JZ4760B
/* XBurst has a 3 interlock cycle delay, but we don't know if the interlock /* XBurst has a 3 interlock cycle delay, but we don't know if the interlock
* works with eret */ * works with eret */