diff --git a/firmware/target/arm/stm32/stm32h7/flash.h b/firmware/target/arm/stm32/stm32h7/flash.h new file mode 100644 index 0000000000..5479b4d8ef --- /dev/null +++ b/firmware/target/arm/stm32/stm32h7/flash.h @@ -0,0 +1,49 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * stm32h743 version: 1.0 + * stm32h743 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_FLASH_H__ +#define __HEADERGEN_FLASH_H__ + +#include "macro.h" + +#define STA_FLASH (0x52002000) + +#define REG_FLASH_ACR st_reg(FLASH_ACR) +#define STA_FLASH_ACR (0x52002000 + 0x0) +#define STO_FLASH_ACR (0x0) +#define STT_FLASH_ACR STIO_32_RW +#define STN_FLASH_ACR FLASH_ACR +#define BP_FLASH_ACR_WRHIGHFREQ 3 +#define BM_FLASH_ACR_WRHIGHFREQ 0x38 +#define BF_FLASH_ACR_WRHIGHFREQ(v) (((v) & 0x7) << 3) +#define BFM_FLASH_ACR_WRHIGHFREQ(v) BM_FLASH_ACR_WRHIGHFREQ +#define BF_FLASH_ACR_WRHIGHFREQ_V(e) BF_FLASH_ACR_WRHIGHFREQ(BV_FLASH_ACR_WRHIGHFREQ__##e) +#define BFM_FLASH_ACR_WRHIGHFREQ_V(v) BM_FLASH_ACR_WRHIGHFREQ +#define BP_FLASH_ACR_LATENCY 0 +#define BM_FLASH_ACR_LATENCY 0xf +#define BF_FLASH_ACR_LATENCY(v) (((v) & 0xf) << 0) +#define BFM_FLASH_ACR_LATENCY(v) BM_FLASH_ACR_LATENCY +#define BF_FLASH_ACR_LATENCY_V(e) BF_FLASH_ACR_LATENCY(BV_FLASH_ACR_LATENCY__##e) +#define BFM_FLASH_ACR_LATENCY_V(v) BM_FLASH_ACR_LATENCY + +#endif /* __HEADERGEN_FLASH_H__*/ diff --git a/firmware/target/arm/stm32/stm32h7/fmc.h b/firmware/target/arm/stm32/stm32h7/fmc.h new file mode 100644 index 0000000000..29ac9c3cc8 --- /dev/null +++ b/firmware/target/arm/stm32/stm32h7/fmc.h @@ -0,0 +1,247 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * stm32h743 version: 1.0 + * stm32h743 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_FMC_H__ +#define __HEADERGEN_FMC_H__ + +#include "macro.h" + +#define STA_FMC (0x52004000) + +#define REG_FMC_BCR(_n1) st_reg(FMC_BCR(_n1)) +#define STA_FMC_BCR(_n1) (0x52004000 + 0x0 + (_n1) * 0x8) +#define STO_FMC_BCR(_n1) (0x0 + (_n1) * 0x8) +#define STT_FMC_BCR(_n1) STIO_32_RW +#define STN_FMC_BCR(_n1) FMC_BCR +#define BP_FMC_BCR_BMAP 24 +#define BM_FMC_BCR_BMAP 0x3000000 +#define BF_FMC_BCR_BMAP(v) (((v) & 0x3) << 24) +#define BFM_FMC_BCR_BMAP(v) BM_FMC_BCR_BMAP +#define BF_FMC_BCR_BMAP_V(e) BF_FMC_BCR_BMAP(BV_FMC_BCR_BMAP__##e) +#define BFM_FMC_BCR_BMAP_V(v) BM_FMC_BCR_BMAP +#define BP_FMC_BCR_FMCEN 31 +#define BM_FMC_BCR_FMCEN 0x80000000 +#define BF_FMC_BCR_FMCEN(v) (((v) & 0x1) << 31) +#define BFM_FMC_BCR_FMCEN(v) BM_FMC_BCR_FMCEN +#define BF_FMC_BCR_FMCEN_V(e) BF_FMC_BCR_FMCEN(BV_FMC_BCR_FMCEN__##e) +#define BFM_FMC_BCR_FMCEN_V(v) BM_FMC_BCR_FMCEN +#define BP_FMC_BCR_WFDIS 21 +#define BM_FMC_BCR_WFDIS 0x200000 +#define BF_FMC_BCR_WFDIS(v) (((v) & 0x1) << 21) +#define BFM_FMC_BCR_WFDIS(v) BM_FMC_BCR_WFDIS +#define BF_FMC_BCR_WFDIS_V(e) BF_FMC_BCR_WFDIS(BV_FMC_BCR_WFDIS__##e) +#define BFM_FMC_BCR_WFDIS_V(v) BM_FMC_BCR_WFDIS + +#define REG_FMC_SDCR(_n1) st_reg(FMC_SDCR(_n1)) +#define STA_FMC_SDCR(_n1) (0x52004000 + 0x140 + (_n1) * 0x4) +#define STO_FMC_SDCR(_n1) (0x140 + (_n1) * 0x4) +#define STT_FMC_SDCR(_n1) STIO_32_RW +#define STN_FMC_SDCR(_n1) FMC_SDCR +#define BP_FMC_SDCR_RPIPE 13 +#define BM_FMC_SDCR_RPIPE 0x6000 +#define BF_FMC_SDCR_RPIPE(v) (((v) & 0x3) << 13) +#define BFM_FMC_SDCR_RPIPE(v) BM_FMC_SDCR_RPIPE +#define BF_FMC_SDCR_RPIPE_V(e) BF_FMC_SDCR_RPIPE(BV_FMC_SDCR_RPIPE__##e) +#define BFM_FMC_SDCR_RPIPE_V(v) BM_FMC_SDCR_RPIPE +#define BP_FMC_SDCR_SDCLK 10 +#define BM_FMC_SDCR_SDCLK 0xc00 +#define BF_FMC_SDCR_SDCLK(v) (((v) & 0x3) << 10) +#define BFM_FMC_SDCR_SDCLK(v) BM_FMC_SDCR_SDCLK +#define BF_FMC_SDCR_SDCLK_V(e) BF_FMC_SDCR_SDCLK(BV_FMC_SDCR_SDCLK__##e) +#define BFM_FMC_SDCR_SDCLK_V(v) BM_FMC_SDCR_SDCLK +#define BP_FMC_SDCR_CAS 7 +#define BM_FMC_SDCR_CAS 0x180 +#define BF_FMC_SDCR_CAS(v) (((v) & 0x3) << 7) +#define BFM_FMC_SDCR_CAS(v) BM_FMC_SDCR_CAS +#define BF_FMC_SDCR_CAS_V(e) BF_FMC_SDCR_CAS(BV_FMC_SDCR_CAS__##e) +#define BFM_FMC_SDCR_CAS_V(v) BM_FMC_SDCR_CAS +#define BP_FMC_SDCR_MWID 4 +#define BM_FMC_SDCR_MWID 0x30 +#define BF_FMC_SDCR_MWID(v) (((v) & 0x3) << 4) +#define BFM_FMC_SDCR_MWID(v) BM_FMC_SDCR_MWID +#define BF_FMC_SDCR_MWID_V(e) BF_FMC_SDCR_MWID(BV_FMC_SDCR_MWID__##e) +#define BFM_FMC_SDCR_MWID_V(v) BM_FMC_SDCR_MWID +#define BP_FMC_SDCR_NR 2 +#define BM_FMC_SDCR_NR 0xc +#define BF_FMC_SDCR_NR(v) (((v) & 0x3) << 2) +#define BFM_FMC_SDCR_NR(v) BM_FMC_SDCR_NR +#define BF_FMC_SDCR_NR_V(e) BF_FMC_SDCR_NR(BV_FMC_SDCR_NR__##e) +#define BFM_FMC_SDCR_NR_V(v) BM_FMC_SDCR_NR +#define BP_FMC_SDCR_NC 0 +#define BM_FMC_SDCR_NC 0x3 +#define BF_FMC_SDCR_NC(v) (((v) & 0x3) << 0) +#define BFM_FMC_SDCR_NC(v) BM_FMC_SDCR_NC +#define BF_FMC_SDCR_NC_V(e) BF_FMC_SDCR_NC(BV_FMC_SDCR_NC__##e) +#define BFM_FMC_SDCR_NC_V(v) BM_FMC_SDCR_NC +#define BP_FMC_SDCR_RBURST 12 +#define BM_FMC_SDCR_RBURST 0x1000 +#define BF_FMC_SDCR_RBURST(v) (((v) & 0x1) << 12) +#define BFM_FMC_SDCR_RBURST(v) BM_FMC_SDCR_RBURST +#define BF_FMC_SDCR_RBURST_V(e) BF_FMC_SDCR_RBURST(BV_FMC_SDCR_RBURST__##e) +#define BFM_FMC_SDCR_RBURST_V(v) BM_FMC_SDCR_RBURST +#define BP_FMC_SDCR_WP 9 +#define BM_FMC_SDCR_WP 0x200 +#define BF_FMC_SDCR_WP(v) (((v) & 0x1) << 9) +#define BFM_FMC_SDCR_WP(v) BM_FMC_SDCR_WP +#define BF_FMC_SDCR_WP_V(e) BF_FMC_SDCR_WP(BV_FMC_SDCR_WP__##e) +#define BFM_FMC_SDCR_WP_V(v) BM_FMC_SDCR_WP +#define BP_FMC_SDCR_NB 6 +#define BM_FMC_SDCR_NB 0x40 +#define BF_FMC_SDCR_NB(v) (((v) & 0x1) << 6) +#define BFM_FMC_SDCR_NB(v) BM_FMC_SDCR_NB +#define BF_FMC_SDCR_NB_V(e) BF_FMC_SDCR_NB(BV_FMC_SDCR_NB__##e) +#define BFM_FMC_SDCR_NB_V(v) BM_FMC_SDCR_NB + +#define REG_FMC_SDTR(_n1) st_reg(FMC_SDTR(_n1)) +#define STA_FMC_SDTR(_n1) (0x52004000 + 0x148 + (_n1) * 0x4) +#define STO_FMC_SDTR(_n1) (0x148 + (_n1) * 0x4) +#define STT_FMC_SDTR(_n1) STIO_32_RW +#define STN_FMC_SDTR(_n1) FMC_SDTR +#define BP_FMC_SDTR_TRCD 24 +#define BM_FMC_SDTR_TRCD 0xf000000 +#define BF_FMC_SDTR_TRCD(v) (((v) & 0xf) << 24) +#define BFM_FMC_SDTR_TRCD(v) BM_FMC_SDTR_TRCD +#define BF_FMC_SDTR_TRCD_V(e) BF_FMC_SDTR_TRCD(BV_FMC_SDTR_TRCD__##e) +#define BFM_FMC_SDTR_TRCD_V(v) BM_FMC_SDTR_TRCD +#define BP_FMC_SDTR_TRP 20 +#define BM_FMC_SDTR_TRP 0xf00000 +#define BF_FMC_SDTR_TRP(v) (((v) & 0xf) << 20) +#define BFM_FMC_SDTR_TRP(v) BM_FMC_SDTR_TRP +#define BF_FMC_SDTR_TRP_V(e) BF_FMC_SDTR_TRP(BV_FMC_SDTR_TRP__##e) +#define BFM_FMC_SDTR_TRP_V(v) BM_FMC_SDTR_TRP +#define BP_FMC_SDTR_TWR 16 +#define BM_FMC_SDTR_TWR 0xf0000 +#define BF_FMC_SDTR_TWR(v) (((v) & 0xf) << 16) +#define BFM_FMC_SDTR_TWR(v) BM_FMC_SDTR_TWR +#define BF_FMC_SDTR_TWR_V(e) BF_FMC_SDTR_TWR(BV_FMC_SDTR_TWR__##e) +#define BFM_FMC_SDTR_TWR_V(v) BM_FMC_SDTR_TWR +#define BP_FMC_SDTR_TRC 12 +#define BM_FMC_SDTR_TRC 0xf000 +#define BF_FMC_SDTR_TRC(v) (((v) & 0xf) << 12) +#define BFM_FMC_SDTR_TRC(v) BM_FMC_SDTR_TRC +#define BF_FMC_SDTR_TRC_V(e) BF_FMC_SDTR_TRC(BV_FMC_SDTR_TRC__##e) +#define BFM_FMC_SDTR_TRC_V(v) BM_FMC_SDTR_TRC +#define BP_FMC_SDTR_TRAS 8 +#define BM_FMC_SDTR_TRAS 0xf00 +#define BF_FMC_SDTR_TRAS(v) (((v) & 0xf) << 8) +#define BFM_FMC_SDTR_TRAS(v) BM_FMC_SDTR_TRAS +#define BF_FMC_SDTR_TRAS_V(e) BF_FMC_SDTR_TRAS(BV_FMC_SDTR_TRAS__##e) +#define BFM_FMC_SDTR_TRAS_V(v) BM_FMC_SDTR_TRAS +#define BP_FMC_SDTR_TXSR 4 +#define BM_FMC_SDTR_TXSR 0xf0 +#define BF_FMC_SDTR_TXSR(v) (((v) & 0xf) << 4) +#define BFM_FMC_SDTR_TXSR(v) BM_FMC_SDTR_TXSR +#define BF_FMC_SDTR_TXSR_V(e) BF_FMC_SDTR_TXSR(BV_FMC_SDTR_TXSR__##e) +#define BFM_FMC_SDTR_TXSR_V(v) BM_FMC_SDTR_TXSR +#define BP_FMC_SDTR_TMRD 0 +#define BM_FMC_SDTR_TMRD 0xf +#define BF_FMC_SDTR_TMRD(v) (((v) & 0xf) << 0) +#define BFM_FMC_SDTR_TMRD(v) BM_FMC_SDTR_TMRD +#define BF_FMC_SDTR_TMRD_V(e) BF_FMC_SDTR_TMRD(BV_FMC_SDTR_TMRD__##e) +#define BFM_FMC_SDTR_TMRD_V(v) BM_FMC_SDTR_TMRD + +#define REG_FMC_SDCMR st_reg(FMC_SDCMR) +#define STA_FMC_SDCMR (0x52004000 + 0x150) +#define STO_FMC_SDCMR (0x150) +#define STT_FMC_SDCMR STIO_32_RW +#define STN_FMC_SDCMR FMC_SDCMR +#define BP_FMC_SDCMR_MRD 9 +#define BM_FMC_SDCMR_MRD 0x7ffe00 +#define BF_FMC_SDCMR_MRD(v) (((v) & 0x3fff) << 9) +#define BFM_FMC_SDCMR_MRD(v) BM_FMC_SDCMR_MRD +#define BF_FMC_SDCMR_MRD_V(e) BF_FMC_SDCMR_MRD(BV_FMC_SDCMR_MRD__##e) +#define BFM_FMC_SDCMR_MRD_V(v) BM_FMC_SDCMR_MRD +#define BP_FMC_SDCMR_NRFS 5 +#define BM_FMC_SDCMR_NRFS 0x1e0 +#define BF_FMC_SDCMR_NRFS(v) (((v) & 0xf) << 5) +#define BFM_FMC_SDCMR_NRFS(v) BM_FMC_SDCMR_NRFS +#define BF_FMC_SDCMR_NRFS_V(e) BF_FMC_SDCMR_NRFS(BV_FMC_SDCMR_NRFS__##e) +#define BFM_FMC_SDCMR_NRFS_V(v) BM_FMC_SDCMR_NRFS +#define BP_FMC_SDCMR_MODE 0 +#define BM_FMC_SDCMR_MODE 0x7 +#define BF_FMC_SDCMR_MODE(v) (((v) & 0x7) << 0) +#define BFM_FMC_SDCMR_MODE(v) BM_FMC_SDCMR_MODE +#define BF_FMC_SDCMR_MODE_V(e) BF_FMC_SDCMR_MODE(BV_FMC_SDCMR_MODE__##e) +#define BFM_FMC_SDCMR_MODE_V(v) BM_FMC_SDCMR_MODE +#define BP_FMC_SDCMR_CTB1 4 +#define BM_FMC_SDCMR_CTB1 0x10 +#define BF_FMC_SDCMR_CTB1(v) (((v) & 0x1) << 4) +#define BFM_FMC_SDCMR_CTB1(v) BM_FMC_SDCMR_CTB1 +#define BF_FMC_SDCMR_CTB1_V(e) BF_FMC_SDCMR_CTB1(BV_FMC_SDCMR_CTB1__##e) +#define BFM_FMC_SDCMR_CTB1_V(v) BM_FMC_SDCMR_CTB1 +#define BP_FMC_SDCMR_CTB2 3 +#define BM_FMC_SDCMR_CTB2 0x8 +#define BF_FMC_SDCMR_CTB2(v) (((v) & 0x1) << 3) +#define BFM_FMC_SDCMR_CTB2(v) BM_FMC_SDCMR_CTB2 +#define BF_FMC_SDCMR_CTB2_V(e) BF_FMC_SDCMR_CTB2(BV_FMC_SDCMR_CTB2__##e) +#define BFM_FMC_SDCMR_CTB2_V(v) BM_FMC_SDCMR_CTB2 + +#define REG_FMC_SDRTR st_reg(FMC_SDRTR) +#define STA_FMC_SDRTR (0x52004000 + 0x154) +#define STO_FMC_SDRTR (0x154) +#define STT_FMC_SDRTR STIO_32_RW +#define STN_FMC_SDRTR FMC_SDRTR +#define BP_FMC_SDRTR_COUNT 1 +#define BM_FMC_SDRTR_COUNT 0x3ffe +#define BF_FMC_SDRTR_COUNT(v) (((v) & 0x1fff) << 1) +#define BFM_FMC_SDRTR_COUNT(v) BM_FMC_SDRTR_COUNT +#define BF_FMC_SDRTR_COUNT_V(e) BF_FMC_SDRTR_COUNT(BV_FMC_SDRTR_COUNT__##e) +#define BFM_FMC_SDRTR_COUNT_V(v) BM_FMC_SDRTR_COUNT +#define BP_FMC_SDRTR_REIE 14 +#define BM_FMC_SDRTR_REIE 0x4000 +#define BF_FMC_SDRTR_REIE(v) (((v) & 0x1) << 14) +#define BFM_FMC_SDRTR_REIE(v) BM_FMC_SDRTR_REIE +#define BF_FMC_SDRTR_REIE_V(e) BF_FMC_SDRTR_REIE(BV_FMC_SDRTR_REIE__##e) +#define BFM_FMC_SDRTR_REIE_V(v) BM_FMC_SDRTR_REIE +#define BP_FMC_SDRTR_CRE 0 +#define BM_FMC_SDRTR_CRE 0x1 +#define BF_FMC_SDRTR_CRE(v) (((v) & 0x1) << 0) +#define BFM_FMC_SDRTR_CRE(v) BM_FMC_SDRTR_CRE +#define BF_FMC_SDRTR_CRE_V(e) BF_FMC_SDRTR_CRE(BV_FMC_SDRTR_CRE__##e) +#define BFM_FMC_SDRTR_CRE_V(v) BM_FMC_SDRTR_CRE + +#define REG_FMC_SDSR st_reg(FMC_SDSR) +#define STA_FMC_SDSR (0x52004000 + 0x158) +#define STO_FMC_SDSR (0x158) +#define STT_FMC_SDSR STIO_32_RW +#define STN_FMC_SDSR FMC_SDSR +#define BP_FMC_SDSR_MODES2 3 +#define BM_FMC_SDSR_MODES2 0x18 +#define BF_FMC_SDSR_MODES2(v) (((v) & 0x3) << 3) +#define BFM_FMC_SDSR_MODES2(v) BM_FMC_SDSR_MODES2 +#define BF_FMC_SDSR_MODES2_V(e) BF_FMC_SDSR_MODES2(BV_FMC_SDSR_MODES2__##e) +#define BFM_FMC_SDSR_MODES2_V(v) BM_FMC_SDSR_MODES2 +#define BP_FMC_SDSR_MODES1 1 +#define BM_FMC_SDSR_MODES1 0x6 +#define BF_FMC_SDSR_MODES1(v) (((v) & 0x3) << 1) +#define BFM_FMC_SDSR_MODES1(v) BM_FMC_SDSR_MODES1 +#define BF_FMC_SDSR_MODES1_V(e) BF_FMC_SDSR_MODES1(BV_FMC_SDSR_MODES1__##e) +#define BFM_FMC_SDSR_MODES1_V(v) BM_FMC_SDSR_MODES1 +#define BP_FMC_SDSR_RE 0 +#define BM_FMC_SDSR_RE 0x1 +#define BF_FMC_SDSR_RE(v) (((v) & 0x1) << 0) +#define BFM_FMC_SDSR_RE(v) BM_FMC_SDSR_RE +#define BF_FMC_SDSR_RE_V(e) BF_FMC_SDSR_RE(BV_FMC_SDSR_RE__##e) +#define BFM_FMC_SDSR_RE_V(v) BM_FMC_SDSR_RE + +#endif /* __HEADERGEN_FMC_H__*/ diff --git a/firmware/target/arm/stm32/stm32h7/gpio.h b/firmware/target/arm/stm32/stm32h7/gpio.h new file mode 100644 index 0000000000..99b33b2bdd --- /dev/null +++ b/firmware/target/arm/stm32/stm32h7/gpio.h @@ -0,0 +1,91 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * stm32h743 version: 1.0 + * stm32h743 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_GPIO_H__ +#define __HEADERGEN_GPIO_H__ + +#include "macro.h" + +#define STA_GPIO(_n1) (0x58020000 + (_n1) * 0x400) + +#define REG_GPIO_MODER(_n1) st_reg(GPIO_MODER(_n1)) +#define STA_GPIO_MODER(_n1) (0x58020000 + (_n1) * 0x400 + 0x0) +#define STO_GPIO_MODER (0x0) +#define STT_GPIO_MODER(_n1) STIO_32_RW +#define STN_GPIO_MODER(_n1) GPIO_MODER + +#define REG_GPIO_OTYPER(_n1) st_reg(GPIO_OTYPER(_n1)) +#define STA_GPIO_OTYPER(_n1) (0x58020000 + (_n1) * 0x400 + 0x4) +#define STO_GPIO_OTYPER (0x4) +#define STT_GPIO_OTYPER(_n1) STIO_32_RW +#define STN_GPIO_OTYPER(_n1) GPIO_OTYPER + +#define REG_GPIO_OSPEEDR(_n1) st_reg(GPIO_OSPEEDR(_n1)) +#define STA_GPIO_OSPEEDR(_n1) (0x58020000 + (_n1) * 0x400 + 0x8) +#define STO_GPIO_OSPEEDR (0x8) +#define STT_GPIO_OSPEEDR(_n1) STIO_32_RW +#define STN_GPIO_OSPEEDR(_n1) GPIO_OSPEEDR + +#define REG_GPIO_PUPDR(_n1) st_reg(GPIO_PUPDR(_n1)) +#define STA_GPIO_PUPDR(_n1) (0x58020000 + (_n1) * 0x400 + 0xc) +#define STO_GPIO_PUPDR (0xc) +#define STT_GPIO_PUPDR(_n1) STIO_32_RW +#define STN_GPIO_PUPDR(_n1) GPIO_PUPDR + +#define REG_GPIO_IDR(_n1) st_reg(GPIO_IDR(_n1)) +#define STA_GPIO_IDR(_n1) (0x58020000 + (_n1) * 0x400 + 0x10) +#define STO_GPIO_IDR (0x10) +#define STT_GPIO_IDR(_n1) STIO_32_RW +#define STN_GPIO_IDR(_n1) GPIO_IDR + +#define REG_GPIO_ODR(_n1) st_reg(GPIO_ODR(_n1)) +#define STA_GPIO_ODR(_n1) (0x58020000 + (_n1) * 0x400 + 0x14) +#define STO_GPIO_ODR (0x14) +#define STT_GPIO_ODR(_n1) STIO_32_RW +#define STN_GPIO_ODR(_n1) GPIO_ODR + +#define REG_GPIO_BSRR(_n1) st_reg(GPIO_BSRR(_n1)) +#define STA_GPIO_BSRR(_n1) (0x58020000 + (_n1) * 0x400 + 0x18) +#define STO_GPIO_BSRR (0x18) +#define STT_GPIO_BSRR(_n1) STIO_32_RW +#define STN_GPIO_BSRR(_n1) GPIO_BSRR + +#define REG_GPIO_LCKR(_n1) st_reg(GPIO_LCKR(_n1)) +#define STA_GPIO_LCKR(_n1) (0x58020000 + (_n1) * 0x400 + 0x1c) +#define STO_GPIO_LCKR (0x1c) +#define STT_GPIO_LCKR(_n1) STIO_32_RW +#define STN_GPIO_LCKR(_n1) GPIO_LCKR + +#define REG_GPIO_AFRL(_n1) st_reg(GPIO_AFRL(_n1)) +#define STA_GPIO_AFRL(_n1) (0x58020000 + (_n1) * 0x400 + 0x20) +#define STO_GPIO_AFRL (0x20) +#define STT_GPIO_AFRL(_n1) STIO_32_RW +#define STN_GPIO_AFRL(_n1) GPIO_AFRL + +#define REG_GPIO_AFRH(_n1) st_reg(GPIO_AFRH(_n1)) +#define STA_GPIO_AFRH(_n1) (0x58020000 + (_n1) * 0x400 + 0x24) +#define STO_GPIO_AFRH (0x24) +#define STT_GPIO_AFRH(_n1) STIO_32_RW +#define STN_GPIO_AFRH(_n1) GPIO_AFRH + +#endif /* __HEADERGEN_GPIO_H__*/ diff --git a/firmware/target/arm/stm32/stm32h7/macro.h b/firmware/target/arm/stm32/stm32h7/macro.h new file mode 100644 index 0000000000..f5835b2e1b --- /dev/null +++ b/firmware/target/arm/stm32/stm32h7/macro.h @@ -0,0 +1,454 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_MACRO_H__ +#define __HEADERGEN_MACRO_H__ + +#include + +#define __VAR_OR1(prefix, suffix) \ + (prefix##suffix) +#define __VAR_OR2(pre, s1, s2) \ + (__VAR_OR1(pre, s1) | __VAR_OR1(pre, s2)) +#define __VAR_OR3(pre, s1, s2, s3) \ + (__VAR_OR1(pre, s1) | __VAR_OR2(pre, s2, s3)) +#define __VAR_OR4(pre, s1, s2, s3, s4) \ + (__VAR_OR2(pre, s1, s2) | __VAR_OR2(pre, s3, s4)) +#define __VAR_OR5(pre, s1, s2, s3, s4, s5) \ + (__VAR_OR2(pre, s1, s2) | __VAR_OR3(pre, s3, s4, s5)) +#define __VAR_OR6(pre, s1, s2, s3, s4, s5, s6) \ + (__VAR_OR3(pre, s1, s2, s3) | __VAR_OR3(pre, s4, s5, s6)) +#define __VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) \ + (__VAR_OR3(pre, s1, s2, s3) | __VAR_OR4(pre, s4, s5, s6, s7)) +#define __VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) \ + (__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR4(pre, s5, s6, s7, s8)) +#define __VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) \ + (__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR5(pre, s5, s6, s7, s8, s9)) +#define __VAR_OR10(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10) \ + (__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR5(pre, s6, s7, s8, s9, s10)) +#define __VAR_OR11(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11) \ + (__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR6(pre, s6, s7, s8, s9, s10, s11)) +#define __VAR_OR12(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12) \ + (__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR6(pre, s7, s8, s9, s10, s11, s12)) +#define __VAR_OR13(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13) \ + (__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR7(pre, s7, s8, s9, s10, s11, s12, s13)) +#define __VAR_OR14(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14) \ + (__VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) | __VAR_OR7(pre, s8, s9, s10, s11, s12, s13, s14)) +#define __VAR_OR15(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15) \ + (__VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) | __VAR_OR8(pre, s8, s9, s10, s11, s12, s13, s14, s15)) +#define __VAR_OR16(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16) \ + (__VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) | __VAR_OR8(pre, s9, s10, s11, s12, s13, s14, s15, s16)) +#define __VAR_OR17(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17) \ + (__VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) | __VAR_OR9(pre, s9, s10, s11, s12, s13, s14, s15, s16, s17)) +#define __VAR_OR18(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18) \ + (__VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) | __VAR_OR9(pre, s10, s11, s12, s13, s14, s15, s16, s17, s18)) +#define __VAR_OR19(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19) \ + (__VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) | __VAR_OR10(pre, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19)) +#define __VAR_OR20(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20) \ + (__VAR_OR10(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10) | __VAR_OR10(pre, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20)) + +#define __VAR_NARGS(...) __VAR_NARGS_(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1) +#define __VAR_NARGS_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, N, ...) N + +#define __VAR_EXPAND(macro, prefix, ...) __VAR_EXPAND_(macro, __VAR_NARGS(__VA_ARGS__), prefix, __VA_ARGS__) +#define __VAR_EXPAND_(macro, cnt, prefix, ...) __VAR_EXPAND__(macro, cnt, prefix, __VA_ARGS__) +#define __VAR_EXPAND__(macro, cnt, prefix, ...) __VAR_EXPAND___(macro##cnt, prefix, __VA_ARGS__) +#define __VAR_EXPAND___(macro, prefix, ...) macro(prefix, __VA_ARGS__) + +#define STIO_8_RO(op, name, ...) STIO_8_RO_##op(name, __VA_ARGS__) +#define STIO_8_RO_RD(name, ...) (*(const volatile uint8_t *)(STA_##name)) +#define STIO_8_RO_WR(name, val) _Static_assert(0, #name " is read-only") +#define STIO_8_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only") +#define STIO_8_RO_VAR(name, ...) (*(const volatile uint8_t *)(STA_##name)) +#define STIO_8_RO_RDREL(name, base, ...) (*(const volatile uint8_t *)((base) + STO_##name)) +#define STIO_8_RO_WRREL(name, base, val) _Static_assert(0, #name " is read-only") +#define STIO_8_RO_RMWREL(name, base, vand, vor) _Static_assert(0, #name " is read-only") +#define STIO_8_RO_VARREL(name, base, ...) (*(const volatile uint8_t *)((base) + STO_##name)) + +#define STIO_16_RO(op, name, ...) STIO_16_RO_##op(name, __VA_ARGS__) +#define STIO_16_RO_RD(name, ...) (*(const volatile uint16_t *)(STA_##name)) +#define STIO_16_RO_WR(name, val) _Static_assert(0, #name " is read-only") +#define STIO_16_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only") +#define STIO_16_RO_VAR(name, ...) (*(const volatile uint16_t *)(STA_##name)) +#define STIO_16_RO_RDREL(name, base, ...) (*(const volatile uint16_t *)((base) + STO_##name)) +#define STIO_16_RO_WRREL(name, base, val) _Static_assert(0, #name " is read-only") +#define STIO_16_RO_RMWREL(name, base, vand, vor) _Static_assert(0, #name " is read-only") +#define STIO_16_RO_VARREL(name, base, ...) (*(const volatile uint16_t *)((base) + STO_##name)) + +#define STIO_32_RO(op, name, ...) STIO_32_RO_##op(name, __VA_ARGS__) +#define STIO_32_RO_RD(name, ...) (*(const volatile uint32_t *)(STA_##name)) +#define STIO_32_RO_WR(name, val) _Static_assert(0, #name " is read-only") +#define STIO_32_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only") +#define STIO_32_RO_VAR(name, ...) (*(const volatile uint32_t *)(STA_##name)) +#define STIO_32_RO_RDREL(name, base, ...) (*(const volatile uint32_t *)((base) + STO_##name)) +#define STIO_32_RO_WRREL(name, base, val) _Static_assert(0, #name " is read-only") +#define STIO_32_RO_RMWREL(name, base, vand, vor) _Static_assert(0, #name " is read-only") +#define STIO_32_RO_VARREL(name, base, ...) (*(const volatile uint32_t *)((base) + STO_##name)) + +#define STIO_8_RW(op, name, ...) STIO_8_RW_##op(name, __VA_ARGS__) +#define STIO_8_RW_RD(name, ...) (*(volatile uint8_t *)(STA_##name)) +#define STIO_8_RW_WR(name, val) (*(volatile uint8_t *)(STA_##name)) = (val) +#define STIO_8_RW_RMW(name, vand, vor) STIO_8_RW_WR(name, (STIO_8_RW_RD(name) & (vand)) | (vor)) +#define STIO_8_RW_VAR(name, ...) (*(volatile uint8_t *)(STA_##name)) +#define STIO_8_RW_RDREL(name, base, ...) (*(volatile uint8_t *)((base) + STO_##name)) +#define STIO_8_RW_WRREL(name, base, val) (*(volatile uint8_t *)((base) + STO_##name)) = (val) +#define STIO_8_RW_RMWREL(name, base, vand, vor) STIO_8_RW_WRREL(name, base, (STIO_8_RW_RDREL(name, base) & (vand)) | (vor)) +#define STIO_8_RW_VARREL(name, base, ...) (*(volatile uint8_t *)((base) + STO_##name)) + +#define STIO_16_RW(op, name, ...) STIO_16_RW_##op(name, __VA_ARGS__) +#define STIO_16_RW_RD(name, ...) (*(volatile uint16_t *)(STA_##name)) +#define STIO_16_RW_WR(name, val) (*(volatile uint16_t *)(STA_##name)) = (val) +#define STIO_16_RW_RMW(name, vand, vor) STIO_16_RW_WR(name, (STIO_16_RW_RD(name) & (vand)) | (vor)) +#define STIO_16_RW_VAR(name, ...) (*(volatile uint16_t *)(STA_##name)) +#define STIO_16_RW_RDREL(name, base, ...) (*(volatile uint16_t *)((base) + STO_##name)) +#define STIO_16_RW_WRREL(name, base, val) (*(volatile uint16_t *)((base) + STO_##name)) = (val) +#define STIO_16_RW_RMWREL(name, base, vand, vor) STIO_16_RW_WRREL(name, base, (STIO_16_RW_RDREL(name, base) & (vand)) | (vor)) +#define STIO_16_RW_VARREL(name, base, ...) (*(volatile uint16_t *)((base) + STO_##name)) + +#define STIO_32_RW(op, name, ...) STIO_32_RW_##op(name, __VA_ARGS__) +#define STIO_32_RW_RD(name, ...) (*(volatile uint32_t *)(STA_##name)) +#define STIO_32_RW_WR(name, val) (*(volatile uint32_t *)(STA_##name)) = (val) +#define STIO_32_RW_RMW(name, vand, vor) STIO_32_RW_WR(name, (STIO_32_RW_RD(name) & (vand)) | (vor)) +#define STIO_32_RW_VAR(name, ...) (*(volatile uint32_t *)(STA_##name)) +#define STIO_32_RW_RDREL(name, base, ...) (*(volatile uint32_t *)((base) + STO_##name)) +#define STIO_32_RW_WRREL(name, base, val) (*(volatile uint32_t *)((base) + STO_##name)) = (val) +#define STIO_32_RW_RMWREL(name, base, vand, vor) STIO_32_RW_WRREL(name, base, (STIO_32_RW_RDREL(name, base) & (vand)) | (vor)) +#define STIO_32_RW_VARREL(name, base, ...) (*(volatile uint32_t *)((base) + STO_##name)) + +#define STIO_8_WO(op, name, ...) STIO_8_WO_##op(name, __VA_ARGS__) +#define STIO_8_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;}) +#define STIO_8_WO_WR(name, val) (*(volatile uint8_t *)(STA_##name)) = (val) +#define STIO_8_WO_RMW(name, vand, vor) STIO_8_WO_WR(name, vor) +#define STIO_8_WO_VAR(name, ...) (*(volatile uint8_t *)(STA_##name)) +#define STIO_8_WO_RDREL(name, base, ...) ({_Static_assert(0, #name " is write-only"); 0;}) +#define STIO_8_WO_WRREL(name, base, val) (*(volatile uint8_t *)((base) + STO_##name)) = (val) +#define STIO_8_WO_RMWREL(name, base, vand, vor) STIO_8_WO_WRREL(name, base, vor) +#define STIO_8_WO_VARREL(name, base, ...) (*(volatile uint8_t *)((base) + STO_##name)) + +#define STIO_16_WO(op, name, ...) STIO_16_WO_##op(name, __VA_ARGS__) +#define STIO_16_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;}) +#define STIO_16_WO_WR(name, val) (*(volatile uint16_t *)(STA_##name)) = (val) +#define STIO_16_WO_RMW(name, vand, vor) STIO_16_WO_WR(name, vor) +#define STIO_16_WO_VAR(name, ...) (*(volatile uint16_t *)(STA_##name)) +#define STIO_16_WO_RDREL(name, base, ...) ({_Static_assert(0, #name " is write-only"); 0;}) +#define STIO_16_WO_WRREL(name, base, val) (*(volatile uint16_t *)((base) + STO_##name)) = (val) +#define STIO_16_WO_RMWREL(name, base, vand, vor) STIO_16_WO_WRREL(name, base, vor) +#define STIO_16_WO_VARREL(name, base, ...) (*(volatile uint16_t *)((base) + STO_##name)) + +#define STIO_32_WO(op, name, ...) STIO_32_WO_##op(name, __VA_ARGS__) +#define STIO_32_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;}) +#define STIO_32_WO_WR(name, val) (*(volatile uint32_t *)(STA_##name)) = (val) +#define STIO_32_WO_RMW(name, vand, vor) STIO_32_WO_WR(name, vor) +#define STIO_32_WO_VAR(name, ...) (*(volatile uint32_t *)(STA_##name)) +#define STIO_32_WO_RDREL(name, base, ...) ({_Static_assert(0, #name " is write-only"); 0;}) +#define STIO_32_WO_WRREL(name, base, val) (*(volatile uint32_t *)((base) + STO_##name)) = (val) +#define STIO_32_WO_RMWREL(name, base, vand, vor) STIO_32_WO_WRREL(name, base, vor) +#define STIO_32_WO_VARREL(name, base, ...) (*(volatile uint32_t *)((base) + STO_##name)) + + +/** st_orf + * + * usage: st_orf(register, f1(v1), f2(v2), ...) + * + * effect: expands to the register value where each field fi has value vi. + * Informally: reg_f1(v1) | reg_f2(v2) | ... + * note: enumerated values for fields can be obtained by using the syntax: + * f1_V(name) + * + * example: st_orf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) + */ +#define st_orf(reg, ...) __VAR_EXPAND(__VAR_OR, BF_##reg##_, __VA_ARGS__) + +/** __st_orfm + * + * usage: __st_orfm(register, f1(v1), f2(v2), ...) + * + * effect: expands to the register value where each field fi has maximum value (vi is ignored). + * note: internal usage + * + * example: __st_orfm(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) + */ +#define __st_orfm(reg, ...) __VAR_EXPAND(__VAR_OR, BFM_##reg##_, __VA_ARGS__) + +/** st_orm + * + * usage: st_orm(register, f1, f2, ...) + * + * effect: expands to the register value where each field fi is set to its maximum value. + * Informally: reg_f1_mask | reg_f2_mask | ... + * + * example: st_orm(ICOLL_CTRL, SFTRST, CLKGATE) + */ +#define st_orm(reg, ...) __VAR_EXPAND(__VAR_OR, BM_##reg##_, __VA_ARGS__) + + +/** st_vreadf + * + * usage: st_vreadf(value, register, field) + * + * effect: given a register value, return the value of a particular field + * note: this macro does NOT read any register + * + * example: st_vreadf(0xc0000000, ICOLL_CTRL, SFTRST) + * st_vreadf(0x46ff, ICOLL_ENABLE, CPU0_PRIO) + */ +#define st_vreadf(val, name, field) (((val) & BM_##name##_##field) >> BP_##name##_##field) + +/** st_vwritef + * + * usage: st_vwritef(var, register, f1(v1), f2(v2), ...) + * + * effect: change the variable value so that field fi has value vi + * note: this macro will perform a read-modify-write + * + * example: st_vwritef(var, ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) + * st_vwritef(var, ICOLL_ENABLE, CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) + */ +#define st_vwritef(var, name, ...) (var) = st_orf(name, __VA_ARGS__) | (~__st_orfm(name, __VA_ARGS__) & (var)) + +/** st_read + * + * usage: st_read(register) + * + * effect: read the register and return its value + * note: register must be fully qualified if indexed + * + * example: st_read(ICOLL_STATUS) + * st_read(ICOLL_ENABLE(42)) + */ +#define st_read(name) STT_##name(RD, name) + +/** st_readf + * + * usage: st_readf(register, field) + * + * effect: read a register and return the value of a particular field + * note: register must be fully qualified if indexed + * + * example: st_readf(ICOLL_CTRL, SFTRST) + * st_readf(ICOLL_ENABLE(3), CPU0_PRIO) + */ +#define st_readf(name, field) st_readf_(st_read(name), STN_##name, field) +#define st_readf_(...) st_vreadf(__VA_ARGS__) + +/** st_write + * + * usage: st_write(register, value) + * + * effect: write a register + * note: register must be fully qualified if indexed + * + * example: st_write(ICOLL_CTRL, 0x42) + * st_write(ICOLL_ENABLE_SET(3), 0x37) + */ +#define st_write(name, val) STT_##name(WR, name, val) + +/** st_writef + * + * usage: st_writef(register, f1(v1), f2(v2), ...) + * + * effect: change the register value so that field fi has value vi + * note: register must be fully qualified if indexed + * note: this macro may perform a read-modify-write + * + * example: st_writef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) + * st_writef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) + */ +#define st_writef(name, ...) st_writef_(name, STN_##name, __VA_ARGS__) +#define st_writef_(name, name2, ...) STT_##name(RMW, name, ~__st_orfm(name2, __VA_ARGS__), st_orf(name2, __VA_ARGS__)) + +/** st_overwritef + * + * usage: st_overwritef(register, f1(v1), f2(v2), ...) + * + * effect: change the register value so that field fi has value vi and other fields have value zero + * thus this macro is equivalent to: + * st_write(register, st_orf(register, f1(v1), ...)) + * note: register must be fully qualified if indexed + * note: this macro will overwrite the register (it is NOT a read-modify-write) + * + * example: st_overwritef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) + * st_overwritef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) + */ +#define st_overwritef(name, ...) st_overwritef_(name, STN_##name, __VA_ARGS__) +#define st_overwritef_(name, name2, ...) STT_##name(WR, name, st_orf(name2, __VA_ARGS__)) + +/** st_setf + * + * usage: st_setf(register, f1, f2, ...) + * + * effect: change the register value so that field fi has maximum value + * note: this macro will perform a read-modify-write + * note: register must be fully qualified if indexed + * + * example: st_setf(ICOLL_CTRL, SFTRST, CLKGATE) + * st_setf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE) + */ +#define st_setf(name, ...) st_setf_(name, STN_##name, __VA_ARGS__) +#define st_setf_(name, name2, ...) STT_##name(RMW, name, ~0,st_orm(name2, __VA_ARGS__)) + +/** st_clrf + * + * usage: st_clrf(register, f1, f2, ...) + * + * effect: change the register value so that field fi has value zero + * note: this macro will perform a read-modify-write + * note: register must be fully qualified if indexed + * + * example: st_clrf(ICOLL_CTRL, SFTRST, CLKGATE) + * st_clrf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE) + */ +#define st_clrf(name, ...) st_clrf_(name, STN_##name, __VA_ARGS__) +#define st_clrf_(name, name2, ...) STT_##name(RMW, name, ~st_orm(name2, __VA_ARGS__), 0) + +/** st_reg + * + * usage: st_reg(register) + * + * effect: return a variable-like expression that can be read/written + * note: register must be fully qualified if indexed + * note: read-only registers will yield a constant expression + * + * example: unsigned x = st_reg(ICOLL_STATUS) + * unsigned x = st_reg(ICOLL_ENABLE(42)) + * st_reg(ICOLL_ENABLE(42)) = 64 + */ +#define st_reg(name) STT_##name(VAR, name) + +/** st_readl + * + * usage: st_readl(base, register) + * + * effect: read the register and return its value + * register address is calculated by offsetting from the base address + * note: register must be fully qualified if indexed + * + * example: st_readl(base, ICOLL_STATUS) + * st_readl(base, ICOLL_ENABLE(42)) + */ +#define st_readl(base, name) STT_##name(RDREL, name, base) + +/** st_readlf + * + * usage: st_readlf(base, register, field) + * + * effect: read a register and return the value of a particular field + * register address is calculated by offsetting from the base address + * note: register must be fully qualified if indexed + * + * example: st_readlf(base, ICOLL_CTRL, SFTRST) + * st_readlf(base, ICOLL_ENABLE(3), CPU0_PRIO) + */ +#define st_readlf(base, name, field) st_readlf_(st_readl(base, name), STN_##name, field) +#define st_readlf_(...) st_vreadf(__VA_ARGS__) + +/** st_writel + * + * usage: st_writel(base, register, value) + * + * effect: write a register + * register address is calculated by offsetting from the base address + * note: register must be fully qualified if indexed + * + * example: st_writel(base, ICOLL_CTRL, 0x42) + * st_writel(base, ICOLL_ENABLE_SET(3), 0x37) + */ +#define st_writel(base, name, val) STT_##name(WRREL, name, base, val) + +/** st_writelf + * + * usage: st_writelf(base, register, f1(v1), f2(v2), ...) + * + * effect: change the register value so that field fi has value vi + * register address is calculated by offsetting from the base address + * note: register must be fully qualified if indexed + * note: this macro may perform a read-modify-write + * + * example: st_writelf(base, ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) + * st_writelf(base, ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) + */ +#define st_writelf(base, name, ...) st_writelf_(base, name, STN_##name, __VA_ARGS__) +#define st_writelf_(base, name, name2, ...) STT_##name(RMWREL, name, base, ~__st_orfm(name2, __VA_ARGS__), st_orf(name2, __VA_ARGS__)) + +/** st_overwritelf + * + * usage: st_overwritelf(base, register, f1(v1), f2(v2), ...) + * + * effect: change the register value so that field fi has value vi and other fields have value zero + * register address is calculated by offsetting from the base address + * thus this macro is equivalent to: + * st_writel(base, register, st_orf(register, f1(v1), ...)) + * note: register must be fully qualified if indexed + * note: this macro will overwrite the register (it is NOT a read-modify-write) + * + * example: st_overwritelf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED)) + * st_overwritelf(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ)) + */ +#define st_overwritelf(base, name, ...) st_overwritelf_(base, name, STN_##name, __VA_ARGS__) +#define st_overwritelf_(base, name, name2, ...) STT_##name(WRREL, name, base, st_orf(name2, __VA_ARGS__)) + +/** st_setlf + * + * usage: st_setlf(base, register, f1, f2, ...) + * + * effect: change the register value so that field fi has maximum value + * register address is calculated by offsetting from the base address + * note: this macro will perform a read-modify-write + * note: register must be fully qualified if indexed + * + * example: st_setlf(base, ICOLL_CTRL, SFTRST, CLKGATE) + * st_setlf(base, ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE) + */ +#define st_setlf(base, name, ...) st_setlf_(base, name, STN_##name, __VA_ARGS__) +#define st_setlf_(base, name, name2, ...) STT_##name(RMWREL, name, base, ~0,st_orm(name2, __VA_ARGS__)) + +/** st_clrlf + * + * usage: st_clrlf(base, register, f1, f2, ...) + * + * effect: change the register value so that field fi has value zero + * register address is calculated by offsetting from the base address + * note: this macro will perform a read-modify-write + * note: register must be fully qualified if indexed + * + * example: st_clrlf(base, ICOLL_CTRL, SFTRST, CLKGATE) + * st_clrlf(base, ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE) + */ +#define st_clrlf(base, name, ...) st_clrlf_(base, name, STN_##name, __VA_ARGS__) +#define st_clrlf_(base, name, name2, ...) STT_##name(RMWREL, name, base, ~st_orm(name2, __VA_ARGS__), 0) + +/** st_regl + * + * usage: st_regl(base, register) + * + * effect: return a variable-like expression that can be read/written + * register address is calculated by offsetting from the base address + * note: register must be fully qualified if indexed + * note: read-only registers will yield a constant expression + * + * example: unsigned x = st_regl(base, ICOLL_STATUS) + * unsigned x = st_regl(base, ICOLL_ENABLE(42)) + * st_regl(base, ICOLL_ENABLE(42)) = 64 + */ +#define st_regl(base, name) STT_##name(VARREL, base, name) + + +#endif /* __HEADERGEN_MACRO_H__*/ diff --git a/firmware/target/arm/stm32/stm32h7/pwr.h b/firmware/target/arm/stm32/stm32h7/pwr.h new file mode 100644 index 0000000000..7976201036 --- /dev/null +++ b/firmware/target/arm/stm32/stm32h7/pwr.h @@ -0,0 +1,190 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * stm32h743 version: 1.0 + * stm32h743 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_PWR_H__ +#define __HEADERGEN_PWR_H__ + +#include "macro.h" + +#define STA_PWR (0x58024800) + +#define REG_PWR_CR1 st_reg(PWR_CR1) +#define STA_PWR_CR1 (0x58024800 + 0x0) +#define STO_PWR_CR1 (0x0) +#define STT_PWR_CR1 STIO_32_RW +#define STN_PWR_CR1 PWR_CR1 +#define BP_PWR_CR1_ALS 17 +#define BM_PWR_CR1_ALS 0x60000 +#define BF_PWR_CR1_ALS(v) (((v) & 0x3) << 17) +#define BFM_PWR_CR1_ALS(v) BM_PWR_CR1_ALS +#define BF_PWR_CR1_ALS_V(e) BF_PWR_CR1_ALS(BV_PWR_CR1_ALS__##e) +#define BFM_PWR_CR1_ALS_V(v) BM_PWR_CR1_ALS +#define BP_PWR_CR1_SVOS 14 +#define BM_PWR_CR1_SVOS 0xc000 +#define BF_PWR_CR1_SVOS(v) (((v) & 0x3) << 14) +#define BFM_PWR_CR1_SVOS(v) BM_PWR_CR1_SVOS +#define BF_PWR_CR1_SVOS_V(e) BF_PWR_CR1_SVOS(BV_PWR_CR1_SVOS__##e) +#define BFM_PWR_CR1_SVOS_V(v) BM_PWR_CR1_SVOS +#define BP_PWR_CR1_PLS 5 +#define BM_PWR_CR1_PLS 0xe0 +#define BF_PWR_CR1_PLS(v) (((v) & 0x7) << 5) +#define BFM_PWR_CR1_PLS(v) BM_PWR_CR1_PLS +#define BF_PWR_CR1_PLS_V(e) BF_PWR_CR1_PLS(BV_PWR_CR1_PLS__##e) +#define BFM_PWR_CR1_PLS_V(v) BM_PWR_CR1_PLS +#define BP_PWR_CR1_AVDEN 16 +#define BM_PWR_CR1_AVDEN 0x10000 +#define BF_PWR_CR1_AVDEN(v) (((v) & 0x1) << 16) +#define BFM_PWR_CR1_AVDEN(v) BM_PWR_CR1_AVDEN +#define BF_PWR_CR1_AVDEN_V(e) BF_PWR_CR1_AVDEN(BV_PWR_CR1_AVDEN__##e) +#define BFM_PWR_CR1_AVDEN_V(v) BM_PWR_CR1_AVDEN +#define BP_PWR_CR1_FLPS 9 +#define BM_PWR_CR1_FLPS 0x200 +#define BF_PWR_CR1_FLPS(v) (((v) & 0x1) << 9) +#define BFM_PWR_CR1_FLPS(v) BM_PWR_CR1_FLPS +#define BF_PWR_CR1_FLPS_V(e) BF_PWR_CR1_FLPS(BV_PWR_CR1_FLPS__##e) +#define BFM_PWR_CR1_FLPS_V(v) BM_PWR_CR1_FLPS +#define BP_PWR_CR1_DBP 8 +#define BM_PWR_CR1_DBP 0x100 +#define BF_PWR_CR1_DBP(v) (((v) & 0x1) << 8) +#define BFM_PWR_CR1_DBP(v) BM_PWR_CR1_DBP +#define BF_PWR_CR1_DBP_V(e) BF_PWR_CR1_DBP(BV_PWR_CR1_DBP__##e) +#define BFM_PWR_CR1_DBP_V(v) BM_PWR_CR1_DBP +#define BP_PWR_CR1_PVDE 4 +#define BM_PWR_CR1_PVDE 0x10 +#define BF_PWR_CR1_PVDE(v) (((v) & 0x1) << 4) +#define BFM_PWR_CR1_PVDE(v) BM_PWR_CR1_PVDE +#define BF_PWR_CR1_PVDE_V(e) BF_PWR_CR1_PVDE(BV_PWR_CR1_PVDE__##e) +#define BFM_PWR_CR1_PVDE_V(v) BM_PWR_CR1_PVDE +#define BP_PWR_CR1_LPDS 0 +#define BM_PWR_CR1_LPDS 0x1 +#define BF_PWR_CR1_LPDS(v) (((v) & 0x1) << 0) +#define BFM_PWR_CR1_LPDS(v) BM_PWR_CR1_LPDS +#define BF_PWR_CR1_LPDS_V(e) BF_PWR_CR1_LPDS(BV_PWR_CR1_LPDS__##e) +#define BFM_PWR_CR1_LPDS_V(v) BM_PWR_CR1_LPDS + +#define REG_PWR_CSR1 st_reg(PWR_CSR1) +#define STA_PWR_CSR1 (0x58024800 + 0x4) +#define STO_PWR_CSR1 (0x4) +#define STT_PWR_CSR1 STIO_32_RW +#define STN_PWR_CSR1 PWR_CSR1 +#define BP_PWR_CSR1_ACTVOS 14 +#define BM_PWR_CSR1_ACTVOS 0xc000 +#define BF_PWR_CSR1_ACTVOS(v) (((v) & 0x3) << 14) +#define BFM_PWR_CSR1_ACTVOS(v) BM_PWR_CSR1_ACTVOS +#define BF_PWR_CSR1_ACTVOS_V(e) BF_PWR_CSR1_ACTVOS(BV_PWR_CSR1_ACTVOS__##e) +#define BFM_PWR_CSR1_ACTVOS_V(v) BM_PWR_CSR1_ACTVOS +#define BP_PWR_CSR1_AVDO 16 +#define BM_PWR_CSR1_AVDO 0x10000 +#define BF_PWR_CSR1_AVDO(v) (((v) & 0x1) << 16) +#define BFM_PWR_CSR1_AVDO(v) BM_PWR_CSR1_AVDO +#define BF_PWR_CSR1_AVDO_V(e) BF_PWR_CSR1_AVDO(BV_PWR_CSR1_AVDO__##e) +#define BFM_PWR_CSR1_AVDO_V(v) BM_PWR_CSR1_AVDO +#define BP_PWR_CSR1_ACTVOSRDY 13 +#define BM_PWR_CSR1_ACTVOSRDY 0x2000 +#define BF_PWR_CSR1_ACTVOSRDY(v) (((v) & 0x1) << 13) +#define BFM_PWR_CSR1_ACTVOSRDY(v) BM_PWR_CSR1_ACTVOSRDY +#define BF_PWR_CSR1_ACTVOSRDY_V(e) BF_PWR_CSR1_ACTVOSRDY(BV_PWR_CSR1_ACTVOSRDY__##e) +#define BFM_PWR_CSR1_ACTVOSRDY_V(v) BM_PWR_CSR1_ACTVOSRDY +#define BP_PWR_CSR1_PVDO 4 +#define BM_PWR_CSR1_PVDO 0x10 +#define BF_PWR_CSR1_PVDO(v) (((v) & 0x1) << 4) +#define BFM_PWR_CSR1_PVDO(v) BM_PWR_CSR1_PVDO +#define BF_PWR_CSR1_PVDO_V(e) BF_PWR_CSR1_PVDO(BV_PWR_CSR1_PVDO__##e) +#define BFM_PWR_CSR1_PVDO_V(v) BM_PWR_CSR1_PVDO + +#define REG_PWR_CR3 st_reg(PWR_CR3) +#define STA_PWR_CR3 (0x58024800 + 0xc) +#define STO_PWR_CR3 (0xc) +#define STT_PWR_CR3 STIO_32_RW +#define STN_PWR_CR3 PWR_CR3 +#define BP_PWR_CR3_USB33RDY 26 +#define BM_PWR_CR3_USB33RDY 0x4000000 +#define BF_PWR_CR3_USB33RDY(v) (((v) & 0x1) << 26) +#define BFM_PWR_CR3_USB33RDY(v) BM_PWR_CR3_USB33RDY +#define BF_PWR_CR3_USB33RDY_V(e) BF_PWR_CR3_USB33RDY(BV_PWR_CR3_USB33RDY__##e) +#define BFM_PWR_CR3_USB33RDY_V(v) BM_PWR_CR3_USB33RDY +#define BP_PWR_CR3_USBREGEN 25 +#define BM_PWR_CR3_USBREGEN 0x2000000 +#define BF_PWR_CR3_USBREGEN(v) (((v) & 0x1) << 25) +#define BFM_PWR_CR3_USBREGEN(v) BM_PWR_CR3_USBREGEN +#define BF_PWR_CR3_USBREGEN_V(e) BF_PWR_CR3_USBREGEN(BV_PWR_CR3_USBREGEN__##e) +#define BFM_PWR_CR3_USBREGEN_V(v) BM_PWR_CR3_USBREGEN +#define BP_PWR_CR3_USB33DEN 24 +#define BM_PWR_CR3_USB33DEN 0x1000000 +#define BF_PWR_CR3_USB33DEN(v) (((v) & 0x1) << 24) +#define BFM_PWR_CR3_USB33DEN(v) BM_PWR_CR3_USB33DEN +#define BF_PWR_CR3_USB33DEN_V(e) BF_PWR_CR3_USB33DEN(BV_PWR_CR3_USB33DEN__##e) +#define BFM_PWR_CR3_USB33DEN_V(v) BM_PWR_CR3_USB33DEN +#define BP_PWR_CR3_VBRS 9 +#define BM_PWR_CR3_VBRS 0x200 +#define BF_PWR_CR3_VBRS(v) (((v) & 0x1) << 9) +#define BFM_PWR_CR3_VBRS(v) BM_PWR_CR3_VBRS +#define BF_PWR_CR3_VBRS_V(e) BF_PWR_CR3_VBRS(BV_PWR_CR3_VBRS__##e) +#define BFM_PWR_CR3_VBRS_V(v) BM_PWR_CR3_VBRS +#define BP_PWR_CR3_VBE 8 +#define BM_PWR_CR3_VBE 0x100 +#define BF_PWR_CR3_VBE(v) (((v) & 0x1) << 8) +#define BFM_PWR_CR3_VBE(v) BM_PWR_CR3_VBE +#define BF_PWR_CR3_VBE_V(e) BF_PWR_CR3_VBE(BV_PWR_CR3_VBE__##e) +#define BFM_PWR_CR3_VBE_V(v) BM_PWR_CR3_VBE +#define BP_PWR_CR3_SCUEN 2 +#define BM_PWR_CR3_SCUEN 0x4 +#define BF_PWR_CR3_SCUEN(v) (((v) & 0x1) << 2) +#define BFM_PWR_CR3_SCUEN(v) BM_PWR_CR3_SCUEN +#define BF_PWR_CR3_SCUEN_V(e) BF_PWR_CR3_SCUEN(BV_PWR_CR3_SCUEN__##e) +#define BFM_PWR_CR3_SCUEN_V(v) BM_PWR_CR3_SCUEN +#define BP_PWR_CR3_LDOEN 1 +#define BM_PWR_CR3_LDOEN 0x2 +#define BF_PWR_CR3_LDOEN(v) (((v) & 0x1) << 1) +#define BFM_PWR_CR3_LDOEN(v) BM_PWR_CR3_LDOEN +#define BF_PWR_CR3_LDOEN_V(e) BF_PWR_CR3_LDOEN(BV_PWR_CR3_LDOEN__##e) +#define BFM_PWR_CR3_LDOEN_V(v) BM_PWR_CR3_LDOEN +#define BP_PWR_CR3_BYPASS 0 +#define BM_PWR_CR3_BYPASS 0x1 +#define BF_PWR_CR3_BYPASS(v) (((v) & 0x1) << 0) +#define BFM_PWR_CR3_BYPASS(v) BM_PWR_CR3_BYPASS +#define BF_PWR_CR3_BYPASS_V(e) BF_PWR_CR3_BYPASS(BV_PWR_CR3_BYPASS__##e) +#define BFM_PWR_CR3_BYPASS_V(v) BM_PWR_CR3_BYPASS + +#define REG_PWR_D3CR st_reg(PWR_D3CR) +#define STA_PWR_D3CR (0x58024800 + 0x18) +#define STO_PWR_D3CR (0x18) +#define STT_PWR_D3CR STIO_32_RW +#define STN_PWR_D3CR PWR_D3CR +#define BP_PWR_D3CR_VOS 14 +#define BM_PWR_D3CR_VOS 0xc000 +#define BV_PWR_D3CR_VOS__VOS3 0x1 +#define BV_PWR_D3CR_VOS__VOS2 0x2 +#define BV_PWR_D3CR_VOS__VOS1 0x3 +#define BF_PWR_D3CR_VOS(v) (((v) & 0x3) << 14) +#define BFM_PWR_D3CR_VOS(v) BM_PWR_D3CR_VOS +#define BF_PWR_D3CR_VOS_V(e) BF_PWR_D3CR_VOS(BV_PWR_D3CR_VOS__##e) +#define BFM_PWR_D3CR_VOS_V(v) BM_PWR_D3CR_VOS +#define BP_PWR_D3CR_VOSRDY 13 +#define BM_PWR_D3CR_VOSRDY 0x2000 +#define BF_PWR_D3CR_VOSRDY(v) (((v) & 0x1) << 13) +#define BFM_PWR_D3CR_VOSRDY(v) BM_PWR_D3CR_VOSRDY +#define BF_PWR_D3CR_VOSRDY_V(e) BF_PWR_D3CR_VOSRDY(BV_PWR_D3CR_VOSRDY__##e) +#define BFM_PWR_D3CR_VOSRDY_V(v) BM_PWR_D3CR_VOSRDY + +#endif /* __HEADERGEN_PWR_H__*/ diff --git a/firmware/target/arm/stm32/stm32h7/rcc.h b/firmware/target/arm/stm32/stm32h7/rcc.h new file mode 100644 index 0000000000..385408924b --- /dev/null +++ b/firmware/target/arm/stm32/stm32h7/rcc.h @@ -0,0 +1,2109 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * stm32h743 version: 1.0 + * stm32h743 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_RCC_H__ +#define __HEADERGEN_RCC_H__ + +#include "macro.h" + +#define STA_RCC (0x58024400) + +#define REG_RCC_CR st_reg(RCC_CR) +#define STA_RCC_CR (0x58024400 + 0x0) +#define STO_RCC_CR (0x0) +#define STT_RCC_CR STIO_32_RW +#define STN_RCC_CR RCC_CR +#define BP_RCC_CR_HSIDIV 3 +#define BM_RCC_CR_HSIDIV 0x18 +#define BF_RCC_CR_HSIDIV(v) (((v) & 0x3) << 3) +#define BFM_RCC_CR_HSIDIV(v) BM_RCC_CR_HSIDIV +#define BF_RCC_CR_HSIDIV_V(e) BF_RCC_CR_HSIDIV(BV_RCC_CR_HSIDIV__##e) +#define BFM_RCC_CR_HSIDIV_V(v) BM_RCC_CR_HSIDIV +#define BP_RCC_CR_PLL3RDY 29 +#define BM_RCC_CR_PLL3RDY 0x20000000 +#define BF_RCC_CR_PLL3RDY(v) (((v) & 0x1) << 29) +#define BFM_RCC_CR_PLL3RDY(v) BM_RCC_CR_PLL3RDY +#define BF_RCC_CR_PLL3RDY_V(e) BF_RCC_CR_PLL3RDY(BV_RCC_CR_PLL3RDY__##e) +#define BFM_RCC_CR_PLL3RDY_V(v) BM_RCC_CR_PLL3RDY +#define BP_RCC_CR_PLL3ON 28 +#define BM_RCC_CR_PLL3ON 0x10000000 +#define BF_RCC_CR_PLL3ON(v) (((v) & 0x1) << 28) +#define BFM_RCC_CR_PLL3ON(v) BM_RCC_CR_PLL3ON +#define BF_RCC_CR_PLL3ON_V(e) BF_RCC_CR_PLL3ON(BV_RCC_CR_PLL3ON__##e) +#define BFM_RCC_CR_PLL3ON_V(v) BM_RCC_CR_PLL3ON +#define BP_RCC_CR_PLL2RDY 27 +#define BM_RCC_CR_PLL2RDY 0x8000000 +#define BF_RCC_CR_PLL2RDY(v) (((v) & 0x1) << 27) +#define BFM_RCC_CR_PLL2RDY(v) BM_RCC_CR_PLL2RDY +#define BF_RCC_CR_PLL2RDY_V(e) BF_RCC_CR_PLL2RDY(BV_RCC_CR_PLL2RDY__##e) +#define BFM_RCC_CR_PLL2RDY_V(v) BM_RCC_CR_PLL2RDY +#define BP_RCC_CR_PLL2ON 26 +#define BM_RCC_CR_PLL2ON 0x4000000 +#define BF_RCC_CR_PLL2ON(v) (((v) & 0x1) << 26) +#define BFM_RCC_CR_PLL2ON(v) BM_RCC_CR_PLL2ON +#define BF_RCC_CR_PLL2ON_V(e) BF_RCC_CR_PLL2ON(BV_RCC_CR_PLL2ON__##e) +#define BFM_RCC_CR_PLL2ON_V(v) BM_RCC_CR_PLL2ON +#define BP_RCC_CR_PLL1RDY 25 +#define BM_RCC_CR_PLL1RDY 0x2000000 +#define BF_RCC_CR_PLL1RDY(v) (((v) & 0x1) << 25) +#define BFM_RCC_CR_PLL1RDY(v) BM_RCC_CR_PLL1RDY +#define BF_RCC_CR_PLL1RDY_V(e) BF_RCC_CR_PLL1RDY(BV_RCC_CR_PLL1RDY__##e) +#define BFM_RCC_CR_PLL1RDY_V(v) BM_RCC_CR_PLL1RDY +#define BP_RCC_CR_PLL1ON 24 +#define BM_RCC_CR_PLL1ON 0x1000000 +#define BF_RCC_CR_PLL1ON(v) (((v) & 0x1) << 24) +#define BFM_RCC_CR_PLL1ON(v) BM_RCC_CR_PLL1ON +#define BF_RCC_CR_PLL1ON_V(e) BF_RCC_CR_PLL1ON(BV_RCC_CR_PLL1ON__##e) +#define BFM_RCC_CR_PLL1ON_V(v) BM_RCC_CR_PLL1ON +#define BP_RCC_CR_HSECSSON 19 +#define BM_RCC_CR_HSECSSON 0x80000 +#define BF_RCC_CR_HSECSSON(v) (((v) & 0x1) << 19) +#define BFM_RCC_CR_HSECSSON(v) BM_RCC_CR_HSECSSON +#define BF_RCC_CR_HSECSSON_V(e) BF_RCC_CR_HSECSSON(BV_RCC_CR_HSECSSON__##e) +#define BFM_RCC_CR_HSECSSON_V(v) BM_RCC_CR_HSECSSON +#define BP_RCC_CR_HSEBYP 18 +#define BM_RCC_CR_HSEBYP 0x40000 +#define BF_RCC_CR_HSEBYP(v) (((v) & 0x1) << 18) +#define BFM_RCC_CR_HSEBYP(v) BM_RCC_CR_HSEBYP +#define BF_RCC_CR_HSEBYP_V(e) BF_RCC_CR_HSEBYP(BV_RCC_CR_HSEBYP__##e) +#define BFM_RCC_CR_HSEBYP_V(v) BM_RCC_CR_HSEBYP +#define BP_RCC_CR_HSERDY 17 +#define BM_RCC_CR_HSERDY 0x20000 +#define BF_RCC_CR_HSERDY(v) (((v) & 0x1) << 17) +#define BFM_RCC_CR_HSERDY(v) BM_RCC_CR_HSERDY +#define BF_RCC_CR_HSERDY_V(e) BF_RCC_CR_HSERDY(BV_RCC_CR_HSERDY__##e) +#define BFM_RCC_CR_HSERDY_V(v) BM_RCC_CR_HSERDY +#define BP_RCC_CR_HSEON 16 +#define BM_RCC_CR_HSEON 0x10000 +#define BF_RCC_CR_HSEON(v) (((v) & 0x1) << 16) +#define BFM_RCC_CR_HSEON(v) BM_RCC_CR_HSEON +#define BF_RCC_CR_HSEON_V(e) BF_RCC_CR_HSEON(BV_RCC_CR_HSEON__##e) +#define BFM_RCC_CR_HSEON_V(v) BM_RCC_CR_HSEON +#define BP_RCC_CR_D2CKRDY 15 +#define BM_RCC_CR_D2CKRDY 0x8000 +#define BF_RCC_CR_D2CKRDY(v) (((v) & 0x1) << 15) +#define BFM_RCC_CR_D2CKRDY(v) BM_RCC_CR_D2CKRDY +#define BF_RCC_CR_D2CKRDY_V(e) BF_RCC_CR_D2CKRDY(BV_RCC_CR_D2CKRDY__##e) +#define BFM_RCC_CR_D2CKRDY_V(v) BM_RCC_CR_D2CKRDY +#define BP_RCC_CR_D1CKRDY 14 +#define BM_RCC_CR_D1CKRDY 0x4000 +#define BF_RCC_CR_D1CKRDY(v) (((v) & 0x1) << 14) +#define BFM_RCC_CR_D1CKRDY(v) BM_RCC_CR_D1CKRDY +#define BF_RCC_CR_D1CKRDY_V(e) BF_RCC_CR_D1CKRDY(BV_RCC_CR_D1CKRDY__##e) +#define BFM_RCC_CR_D1CKRDY_V(v) BM_RCC_CR_D1CKRDY +#define BP_RCC_CR_HSI48RDY 13 +#define BM_RCC_CR_HSI48RDY 0x2000 +#define BF_RCC_CR_HSI48RDY(v) (((v) & 0x1) << 13) +#define BFM_RCC_CR_HSI48RDY(v) BM_RCC_CR_HSI48RDY +#define BF_RCC_CR_HSI48RDY_V(e) BF_RCC_CR_HSI48RDY(BV_RCC_CR_HSI48RDY__##e) +#define BFM_RCC_CR_HSI48RDY_V(v) BM_RCC_CR_HSI48RDY +#define BP_RCC_CR_HSI48ON 12 +#define BM_RCC_CR_HSI48ON 0x1000 +#define BF_RCC_CR_HSI48ON(v) (((v) & 0x1) << 12) +#define BFM_RCC_CR_HSI48ON(v) BM_RCC_CR_HSI48ON +#define BF_RCC_CR_HSI48ON_V(e) BF_RCC_CR_HSI48ON(BV_RCC_CR_HSI48ON__##e) +#define BFM_RCC_CR_HSI48ON_V(v) BM_RCC_CR_HSI48ON +#define BP_RCC_CR_CSIKERON 9 +#define BM_RCC_CR_CSIKERON 0x200 +#define BF_RCC_CR_CSIKERON(v) (((v) & 0x1) << 9) +#define BFM_RCC_CR_CSIKERON(v) BM_RCC_CR_CSIKERON +#define BF_RCC_CR_CSIKERON_V(e) BF_RCC_CR_CSIKERON(BV_RCC_CR_CSIKERON__##e) +#define BFM_RCC_CR_CSIKERON_V(v) BM_RCC_CR_CSIKERON +#define BP_RCC_CR_CSIRDY 8 +#define BM_RCC_CR_CSIRDY 0x100 +#define BF_RCC_CR_CSIRDY(v) (((v) & 0x1) << 8) +#define BFM_RCC_CR_CSIRDY(v) BM_RCC_CR_CSIRDY +#define BF_RCC_CR_CSIRDY_V(e) BF_RCC_CR_CSIRDY(BV_RCC_CR_CSIRDY__##e) +#define BFM_RCC_CR_CSIRDY_V(v) BM_RCC_CR_CSIRDY +#define BP_RCC_CR_CSION 7 +#define BM_RCC_CR_CSION 0x80 +#define BF_RCC_CR_CSION(v) (((v) & 0x1) << 7) +#define BFM_RCC_CR_CSION(v) BM_RCC_CR_CSION +#define BF_RCC_CR_CSION_V(e) BF_RCC_CR_CSION(BV_RCC_CR_CSION__##e) +#define BFM_RCC_CR_CSION_V(v) BM_RCC_CR_CSION +#define BP_RCC_CR_HSIDIVF 5 +#define BM_RCC_CR_HSIDIVF 0x20 +#define BF_RCC_CR_HSIDIVF(v) (((v) & 0x1) << 5) +#define BFM_RCC_CR_HSIDIVF(v) BM_RCC_CR_HSIDIVF +#define BF_RCC_CR_HSIDIVF_V(e) BF_RCC_CR_HSIDIVF(BV_RCC_CR_HSIDIVF__##e) +#define BFM_RCC_CR_HSIDIVF_V(v) BM_RCC_CR_HSIDIVF +#define BP_RCC_CR_HSIRDY 2 +#define BM_RCC_CR_HSIRDY 0x4 +#define BF_RCC_CR_HSIRDY(v) (((v) & 0x1) << 2) +#define BFM_RCC_CR_HSIRDY(v) BM_RCC_CR_HSIRDY +#define BF_RCC_CR_HSIRDY_V(e) BF_RCC_CR_HSIRDY(BV_RCC_CR_HSIRDY__##e) +#define BFM_RCC_CR_HSIRDY_V(v) BM_RCC_CR_HSIRDY +#define BP_RCC_CR_HSIKERON 1 +#define BM_RCC_CR_HSIKERON 0x2 +#define BF_RCC_CR_HSIKERON(v) (((v) & 0x1) << 1) +#define BFM_RCC_CR_HSIKERON(v) BM_RCC_CR_HSIKERON +#define BF_RCC_CR_HSIKERON_V(e) BF_RCC_CR_HSIKERON(BV_RCC_CR_HSIKERON__##e) +#define BFM_RCC_CR_HSIKERON_V(v) BM_RCC_CR_HSIKERON +#define BP_RCC_CR_HSION 0 +#define BM_RCC_CR_HSION 0x1 +#define BF_RCC_CR_HSION(v) (((v) & 0x1) << 0) +#define BFM_RCC_CR_HSION(v) BM_RCC_CR_HSION +#define BF_RCC_CR_HSION_V(e) BF_RCC_CR_HSION(BV_RCC_CR_HSION__##e) +#define BFM_RCC_CR_HSION_V(v) BM_RCC_CR_HSION + +#define REG_RCC_CFGR st_reg(RCC_CFGR) +#define STA_RCC_CFGR (0x58024400 + 0x10) +#define STO_RCC_CFGR (0x10) +#define STT_RCC_CFGR STIO_32_RW +#define STN_RCC_CFGR RCC_CFGR +#define BP_RCC_CFGR_MCO2 29 +#define BM_RCC_CFGR_MCO2 0xe0000000 +#define BV_RCC_CFGR_MCO2__SYSCLK 0x0 +#define BV_RCC_CFGR_MCO2__PLL2P 0x1 +#define BV_RCC_CFGR_MCO2__HSE 0x2 +#define BV_RCC_CFGR_MCO2__PLL1P 0x3 +#define BV_RCC_CFGR_MCO2__CSI 0x4 +#define BV_RCC_CFGR_MCO2__LSI 0x5 +#define BF_RCC_CFGR_MCO2(v) (((v) & 0x7) << 29) +#define BFM_RCC_CFGR_MCO2(v) BM_RCC_CFGR_MCO2 +#define BF_RCC_CFGR_MCO2_V(e) BF_RCC_CFGR_MCO2(BV_RCC_CFGR_MCO2__##e) +#define BFM_RCC_CFGR_MCO2_V(v) BM_RCC_CFGR_MCO2 +#define BP_RCC_CFGR_MCO2PRE 25 +#define BM_RCC_CFGR_MCO2PRE 0x1e000000 +#define BF_RCC_CFGR_MCO2PRE(v) (((v) & 0xf) << 25) +#define BFM_RCC_CFGR_MCO2PRE(v) BM_RCC_CFGR_MCO2PRE +#define BF_RCC_CFGR_MCO2PRE_V(e) BF_RCC_CFGR_MCO2PRE(BV_RCC_CFGR_MCO2PRE__##e) +#define BFM_RCC_CFGR_MCO2PRE_V(v) BM_RCC_CFGR_MCO2PRE +#define BP_RCC_CFGR_MCO1 22 +#define BM_RCC_CFGR_MCO1 0x1c00000 +#define BV_RCC_CFGR_MCO1__HSI 0x0 +#define BV_RCC_CFGR_MCO1__LSE 0x1 +#define BV_RCC_CFGR_MCO1__HSE 0x2 +#define BV_RCC_CFGR_MCO1__PLL1Q 0x3 +#define BV_RCC_CFGR_MCO1__HSI48 0x4 +#define BF_RCC_CFGR_MCO1(v) (((v) & 0x7) << 22) +#define BFM_RCC_CFGR_MCO1(v) BM_RCC_CFGR_MCO1 +#define BF_RCC_CFGR_MCO1_V(e) BF_RCC_CFGR_MCO1(BV_RCC_CFGR_MCO1__##e) +#define BFM_RCC_CFGR_MCO1_V(v) BM_RCC_CFGR_MCO1 +#define BP_RCC_CFGR_MCO1PRE 18 +#define BM_RCC_CFGR_MCO1PRE 0x3c0000 +#define BF_RCC_CFGR_MCO1PRE(v) (((v) & 0xf) << 18) +#define BFM_RCC_CFGR_MCO1PRE(v) BM_RCC_CFGR_MCO1PRE +#define BF_RCC_CFGR_MCO1PRE_V(e) BF_RCC_CFGR_MCO1PRE(BV_RCC_CFGR_MCO1PRE__##e) +#define BFM_RCC_CFGR_MCO1PRE_V(v) BM_RCC_CFGR_MCO1PRE +#define BP_RCC_CFGR_RTCPRE 8 +#define BM_RCC_CFGR_RTCPRE 0x3f00 +#define BF_RCC_CFGR_RTCPRE(v) (((v) & 0x3f) << 8) +#define BFM_RCC_CFGR_RTCPRE(v) BM_RCC_CFGR_RTCPRE +#define BF_RCC_CFGR_RTCPRE_V(e) BF_RCC_CFGR_RTCPRE(BV_RCC_CFGR_RTCPRE__##e) +#define BFM_RCC_CFGR_RTCPRE_V(v) BM_RCC_CFGR_RTCPRE +#define BP_RCC_CFGR_SWS 3 +#define BM_RCC_CFGR_SWS 0x38 +#define BF_RCC_CFGR_SWS(v) (((v) & 0x7) << 3) +#define BFM_RCC_CFGR_SWS(v) BM_RCC_CFGR_SWS +#define BF_RCC_CFGR_SWS_V(e) BF_RCC_CFGR_SWS(BV_RCC_CFGR_SWS__##e) +#define BFM_RCC_CFGR_SWS_V(v) BM_RCC_CFGR_SWS +#define BP_RCC_CFGR_SW 0 +#define BM_RCC_CFGR_SW 0x7 +#define BV_RCC_CFGR_SW__HSI 0x0 +#define BV_RCC_CFGR_SW__CSI 0x1 +#define BV_RCC_CFGR_SW__HSE 0x2 +#define BV_RCC_CFGR_SW__PLL1P 0x3 +#define BF_RCC_CFGR_SW(v) (((v) & 0x7) << 0) +#define BFM_RCC_CFGR_SW(v) BM_RCC_CFGR_SW +#define BF_RCC_CFGR_SW_V(e) BF_RCC_CFGR_SW(BV_RCC_CFGR_SW__##e) +#define BFM_RCC_CFGR_SW_V(v) BM_RCC_CFGR_SW +#define BP_RCC_CFGR_TIMPRE 15 +#define BM_RCC_CFGR_TIMPRE 0x8000 +#define BF_RCC_CFGR_TIMPRE(v) (((v) & 0x1) << 15) +#define BFM_RCC_CFGR_TIMPRE(v) BM_RCC_CFGR_TIMPRE +#define BF_RCC_CFGR_TIMPRE_V(e) BF_RCC_CFGR_TIMPRE(BV_RCC_CFGR_TIMPRE__##e) +#define BFM_RCC_CFGR_TIMPRE_V(v) BM_RCC_CFGR_TIMPRE +#define BP_RCC_CFGR_HRTIMSEL 14 +#define BM_RCC_CFGR_HRTIMSEL 0x4000 +#define BF_RCC_CFGR_HRTIMSEL(v) (((v) & 0x1) << 14) +#define BFM_RCC_CFGR_HRTIMSEL(v) BM_RCC_CFGR_HRTIMSEL +#define BF_RCC_CFGR_HRTIMSEL_V(e) BF_RCC_CFGR_HRTIMSEL(BV_RCC_CFGR_HRTIMSEL__##e) +#define BFM_RCC_CFGR_HRTIMSEL_V(v) BM_RCC_CFGR_HRTIMSEL +#define BP_RCC_CFGR_STOPKERWUCK 7 +#define BM_RCC_CFGR_STOPKERWUCK 0x80 +#define BF_RCC_CFGR_STOPKERWUCK(v) (((v) & 0x1) << 7) +#define BFM_RCC_CFGR_STOPKERWUCK(v) BM_RCC_CFGR_STOPKERWUCK +#define BF_RCC_CFGR_STOPKERWUCK_V(e) BF_RCC_CFGR_STOPKERWUCK(BV_RCC_CFGR_STOPKERWUCK__##e) +#define BFM_RCC_CFGR_STOPKERWUCK_V(v) BM_RCC_CFGR_STOPKERWUCK +#define BP_RCC_CFGR_STOPWUCK 6 +#define BM_RCC_CFGR_STOPWUCK 0x40 +#define BF_RCC_CFGR_STOPWUCK(v) (((v) & 0x1) << 6) +#define BFM_RCC_CFGR_STOPWUCK(v) BM_RCC_CFGR_STOPWUCK +#define BF_RCC_CFGR_STOPWUCK_V(e) BF_RCC_CFGR_STOPWUCK(BV_RCC_CFGR_STOPWUCK__##e) +#define BFM_RCC_CFGR_STOPWUCK_V(v) BM_RCC_CFGR_STOPWUCK + +#define REG_RCC_D1CFGR st_reg(RCC_D1CFGR) +#define STA_RCC_D1CFGR (0x58024400 + 0x18) +#define STO_RCC_D1CFGR (0x18) +#define STT_RCC_D1CFGR STIO_32_RW +#define STN_RCC_D1CFGR RCC_D1CFGR +#define BP_RCC_D1CFGR_D1CPRE 8 +#define BM_RCC_D1CFGR_D1CPRE 0xf00 +#define BF_RCC_D1CFGR_D1CPRE(v) (((v) & 0xf) << 8) +#define BFM_RCC_D1CFGR_D1CPRE(v) BM_RCC_D1CFGR_D1CPRE +#define BF_RCC_D1CFGR_D1CPRE_V(e) BF_RCC_D1CFGR_D1CPRE(BV_RCC_D1CFGR_D1CPRE__##e) +#define BFM_RCC_D1CFGR_D1CPRE_V(v) BM_RCC_D1CFGR_D1CPRE +#define BP_RCC_D1CFGR_D1PPRE 4 +#define BM_RCC_D1CFGR_D1PPRE 0x70 +#define BF_RCC_D1CFGR_D1PPRE(v) (((v) & 0x7) << 4) +#define BFM_RCC_D1CFGR_D1PPRE(v) BM_RCC_D1CFGR_D1PPRE +#define BF_RCC_D1CFGR_D1PPRE_V(e) BF_RCC_D1CFGR_D1PPRE(BV_RCC_D1CFGR_D1PPRE__##e) +#define BFM_RCC_D1CFGR_D1PPRE_V(v) BM_RCC_D1CFGR_D1PPRE +#define BP_RCC_D1CFGR_HPRE 0 +#define BM_RCC_D1CFGR_HPRE 0x1f +#define BF_RCC_D1CFGR_HPRE(v) (((v) & 0x1f) << 0) +#define BFM_RCC_D1CFGR_HPRE(v) BM_RCC_D1CFGR_HPRE +#define BF_RCC_D1CFGR_HPRE_V(e) BF_RCC_D1CFGR_HPRE(BV_RCC_D1CFGR_HPRE__##e) +#define BFM_RCC_D1CFGR_HPRE_V(v) BM_RCC_D1CFGR_HPRE + +#define REG_RCC_D2CFGR st_reg(RCC_D2CFGR) +#define STA_RCC_D2CFGR (0x58024400 + 0x1c) +#define STO_RCC_D2CFGR (0x1c) +#define STT_RCC_D2CFGR STIO_32_RW +#define STN_RCC_D2CFGR RCC_D2CFGR +#define BP_RCC_D2CFGR_D2PPRE2 8 +#define BM_RCC_D2CFGR_D2PPRE2 0x700 +#define BF_RCC_D2CFGR_D2PPRE2(v) (((v) & 0x7) << 8) +#define BFM_RCC_D2CFGR_D2PPRE2(v) BM_RCC_D2CFGR_D2PPRE2 +#define BF_RCC_D2CFGR_D2PPRE2_V(e) BF_RCC_D2CFGR_D2PPRE2(BV_RCC_D2CFGR_D2PPRE2__##e) +#define BFM_RCC_D2CFGR_D2PPRE2_V(v) BM_RCC_D2CFGR_D2PPRE2 +#define BP_RCC_D2CFGR_D2PPRE1 4 +#define BM_RCC_D2CFGR_D2PPRE1 0x70 +#define BF_RCC_D2CFGR_D2PPRE1(v) (((v) & 0x7) << 4) +#define BFM_RCC_D2CFGR_D2PPRE1(v) BM_RCC_D2CFGR_D2PPRE1 +#define BF_RCC_D2CFGR_D2PPRE1_V(e) BF_RCC_D2CFGR_D2PPRE1(BV_RCC_D2CFGR_D2PPRE1__##e) +#define BFM_RCC_D2CFGR_D2PPRE1_V(v) BM_RCC_D2CFGR_D2PPRE1 + +#define REG_RCC_D3CFGR st_reg(RCC_D3CFGR) +#define STA_RCC_D3CFGR (0x58024400 + 0x20) +#define STO_RCC_D3CFGR (0x20) +#define STT_RCC_D3CFGR STIO_32_RW +#define STN_RCC_D3CFGR RCC_D3CFGR +#define BP_RCC_D3CFGR_D3PPRE 4 +#define BM_RCC_D3CFGR_D3PPRE 0x70 +#define BF_RCC_D3CFGR_D3PPRE(v) (((v) & 0x7) << 4) +#define BFM_RCC_D3CFGR_D3PPRE(v) BM_RCC_D3CFGR_D3PPRE +#define BF_RCC_D3CFGR_D3PPRE_V(e) BF_RCC_D3CFGR_D3PPRE(BV_RCC_D3CFGR_D3PPRE__##e) +#define BFM_RCC_D3CFGR_D3PPRE_V(v) BM_RCC_D3CFGR_D3PPRE + +#define REG_RCC_PLLCKSELR st_reg(RCC_PLLCKSELR) +#define STA_RCC_PLLCKSELR (0x58024400 + 0x28) +#define STO_RCC_PLLCKSELR (0x28) +#define STT_RCC_PLLCKSELR STIO_32_RW +#define STN_RCC_PLLCKSELR RCC_PLLCKSELR +#define BP_RCC_PLLCKSELR_DIVM3 20 +#define BM_RCC_PLLCKSELR_DIVM3 0x3f00000 +#define BF_RCC_PLLCKSELR_DIVM3(v) (((v) & 0x3f) << 20) +#define BFM_RCC_PLLCKSELR_DIVM3(v) BM_RCC_PLLCKSELR_DIVM3 +#define BF_RCC_PLLCKSELR_DIVM3_V(e) BF_RCC_PLLCKSELR_DIVM3(BV_RCC_PLLCKSELR_DIVM3__##e) +#define BFM_RCC_PLLCKSELR_DIVM3_V(v) BM_RCC_PLLCKSELR_DIVM3 +#define BP_RCC_PLLCKSELR_DIVM2 12 +#define BM_RCC_PLLCKSELR_DIVM2 0x3f000 +#define BF_RCC_PLLCKSELR_DIVM2(v) (((v) & 0x3f) << 12) +#define BFM_RCC_PLLCKSELR_DIVM2(v) BM_RCC_PLLCKSELR_DIVM2 +#define BF_RCC_PLLCKSELR_DIVM2_V(e) BF_RCC_PLLCKSELR_DIVM2(BV_RCC_PLLCKSELR_DIVM2__##e) +#define BFM_RCC_PLLCKSELR_DIVM2_V(v) BM_RCC_PLLCKSELR_DIVM2 +#define BP_RCC_PLLCKSELR_DIVM1 4 +#define BM_RCC_PLLCKSELR_DIVM1 0x3f0 +#define BF_RCC_PLLCKSELR_DIVM1(v) (((v) & 0x3f) << 4) +#define BFM_RCC_PLLCKSELR_DIVM1(v) BM_RCC_PLLCKSELR_DIVM1 +#define BF_RCC_PLLCKSELR_DIVM1_V(e) BF_RCC_PLLCKSELR_DIVM1(BV_RCC_PLLCKSELR_DIVM1__##e) +#define BFM_RCC_PLLCKSELR_DIVM1_V(v) BM_RCC_PLLCKSELR_DIVM1 +#define BP_RCC_PLLCKSELR_PLLSRC 0 +#define BM_RCC_PLLCKSELR_PLLSRC 0x3 +#define BV_RCC_PLLCKSELR_PLLSRC__HSI 0x0 +#define BV_RCC_PLLCKSELR_PLLSRC__CSI 0x1 +#define BV_RCC_PLLCKSELR_PLLSRC__HSE 0x2 +#define BV_RCC_PLLCKSELR_PLLSRC__NONE 0x3 +#define BF_RCC_PLLCKSELR_PLLSRC(v) (((v) & 0x3) << 0) +#define BFM_RCC_PLLCKSELR_PLLSRC(v) BM_RCC_PLLCKSELR_PLLSRC +#define BF_RCC_PLLCKSELR_PLLSRC_V(e) BF_RCC_PLLCKSELR_PLLSRC(BV_RCC_PLLCKSELR_PLLSRC__##e) +#define BFM_RCC_PLLCKSELR_PLLSRC_V(v) BM_RCC_PLLCKSELR_PLLSRC + +#define REG_RCC_PLLCFGR st_reg(RCC_PLLCFGR) +#define STA_RCC_PLLCFGR (0x58024400 + 0x2c) +#define STO_RCC_PLLCFGR (0x2c) +#define STT_RCC_PLLCFGR STIO_32_RW +#define STN_RCC_PLLCFGR RCC_PLLCFGR +#define BP_RCC_PLLCFGR_PLL3RGE 10 +#define BM_RCC_PLLCFGR_PLL3RGE 0xc00 +#define BV_RCC_PLLCFGR_PLL3RGE__1_2MHZ 0x0 +#define BV_RCC_PLLCFGR_PLL3RGE__2_4MHz 0x1 +#define BV_RCC_PLLCFGR_PLL3RGE__4_8MHz 0x2 +#define BV_RCC_PLLCFGR_PLL3RGE__8_16MHz 0x3 +#define BF_RCC_PLLCFGR_PLL3RGE(v) (((v) & 0x3) << 10) +#define BFM_RCC_PLLCFGR_PLL3RGE(v) BM_RCC_PLLCFGR_PLL3RGE +#define BF_RCC_PLLCFGR_PLL3RGE_V(e) BF_RCC_PLLCFGR_PLL3RGE(BV_RCC_PLLCFGR_PLL3RGE__##e) +#define BFM_RCC_PLLCFGR_PLL3RGE_V(v) BM_RCC_PLLCFGR_PLL3RGE +#define BP_RCC_PLLCFGR_PLL2RGE 6 +#define BM_RCC_PLLCFGR_PLL2RGE 0xc0 +#define BV_RCC_PLLCFGR_PLL2RGE__1_2MHZ 0x0 +#define BV_RCC_PLLCFGR_PLL2RGE__2_4MHz 0x1 +#define BV_RCC_PLLCFGR_PLL2RGE__4_8MHz 0x2 +#define BV_RCC_PLLCFGR_PLL2RGE__8_16MHz 0x3 +#define BF_RCC_PLLCFGR_PLL2RGE(v) (((v) & 0x3) << 6) +#define BFM_RCC_PLLCFGR_PLL2RGE(v) BM_RCC_PLLCFGR_PLL2RGE +#define BF_RCC_PLLCFGR_PLL2RGE_V(e) BF_RCC_PLLCFGR_PLL2RGE(BV_RCC_PLLCFGR_PLL2RGE__##e) +#define BFM_RCC_PLLCFGR_PLL2RGE_V(v) BM_RCC_PLLCFGR_PLL2RGE +#define BP_RCC_PLLCFGR_PLL1RGE 2 +#define BM_RCC_PLLCFGR_PLL1RGE 0xc +#define BV_RCC_PLLCFGR_PLL1RGE__1_2MHZ 0x0 +#define BV_RCC_PLLCFGR_PLL1RGE__2_4MHz 0x1 +#define BV_RCC_PLLCFGR_PLL1RGE__4_8MHz 0x2 +#define BV_RCC_PLLCFGR_PLL1RGE__8_16MHz 0x3 +#define BF_RCC_PLLCFGR_PLL1RGE(v) (((v) & 0x3) << 2) +#define BFM_RCC_PLLCFGR_PLL1RGE(v) BM_RCC_PLLCFGR_PLL1RGE +#define BF_RCC_PLLCFGR_PLL1RGE_V(e) BF_RCC_PLLCFGR_PLL1RGE(BV_RCC_PLLCFGR_PLL1RGE__##e) +#define BFM_RCC_PLLCFGR_PLL1RGE_V(v) BM_RCC_PLLCFGR_PLL1RGE +#define BP_RCC_PLLCFGR_DIVR3EN 24 +#define BM_RCC_PLLCFGR_DIVR3EN 0x1000000 +#define BF_RCC_PLLCFGR_DIVR3EN(v) (((v) & 0x1) << 24) +#define BFM_RCC_PLLCFGR_DIVR3EN(v) BM_RCC_PLLCFGR_DIVR3EN +#define BF_RCC_PLLCFGR_DIVR3EN_V(e) BF_RCC_PLLCFGR_DIVR3EN(BV_RCC_PLLCFGR_DIVR3EN__##e) +#define BFM_RCC_PLLCFGR_DIVR3EN_V(v) BM_RCC_PLLCFGR_DIVR3EN +#define BP_RCC_PLLCFGR_DIVQ3EN 23 +#define BM_RCC_PLLCFGR_DIVQ3EN 0x800000 +#define BF_RCC_PLLCFGR_DIVQ3EN(v) (((v) & 0x1) << 23) +#define BFM_RCC_PLLCFGR_DIVQ3EN(v) BM_RCC_PLLCFGR_DIVQ3EN +#define BF_RCC_PLLCFGR_DIVQ3EN_V(e) BF_RCC_PLLCFGR_DIVQ3EN(BV_RCC_PLLCFGR_DIVQ3EN__##e) +#define BFM_RCC_PLLCFGR_DIVQ3EN_V(v) BM_RCC_PLLCFGR_DIVQ3EN +#define BP_RCC_PLLCFGR_DIVP3EN 22 +#define BM_RCC_PLLCFGR_DIVP3EN 0x400000 +#define BF_RCC_PLLCFGR_DIVP3EN(v) (((v) & 0x1) << 22) +#define BFM_RCC_PLLCFGR_DIVP3EN(v) BM_RCC_PLLCFGR_DIVP3EN +#define BF_RCC_PLLCFGR_DIVP3EN_V(e) BF_RCC_PLLCFGR_DIVP3EN(BV_RCC_PLLCFGR_DIVP3EN__##e) +#define BFM_RCC_PLLCFGR_DIVP3EN_V(v) BM_RCC_PLLCFGR_DIVP3EN +#define BP_RCC_PLLCFGR_DIVR2EN 21 +#define BM_RCC_PLLCFGR_DIVR2EN 0x200000 +#define BF_RCC_PLLCFGR_DIVR2EN(v) (((v) & 0x1) << 21) +#define BFM_RCC_PLLCFGR_DIVR2EN(v) BM_RCC_PLLCFGR_DIVR2EN +#define BF_RCC_PLLCFGR_DIVR2EN_V(e) BF_RCC_PLLCFGR_DIVR2EN(BV_RCC_PLLCFGR_DIVR2EN__##e) +#define BFM_RCC_PLLCFGR_DIVR2EN_V(v) BM_RCC_PLLCFGR_DIVR2EN +#define BP_RCC_PLLCFGR_DIVQ2EN 20 +#define BM_RCC_PLLCFGR_DIVQ2EN 0x100000 +#define BF_RCC_PLLCFGR_DIVQ2EN(v) (((v) & 0x1) << 20) +#define BFM_RCC_PLLCFGR_DIVQ2EN(v) BM_RCC_PLLCFGR_DIVQ2EN +#define BF_RCC_PLLCFGR_DIVQ2EN_V(e) BF_RCC_PLLCFGR_DIVQ2EN(BV_RCC_PLLCFGR_DIVQ2EN__##e) +#define BFM_RCC_PLLCFGR_DIVQ2EN_V(v) BM_RCC_PLLCFGR_DIVQ2EN +#define BP_RCC_PLLCFGR_DIVP2EN 19 +#define BM_RCC_PLLCFGR_DIVP2EN 0x80000 +#define BF_RCC_PLLCFGR_DIVP2EN(v) (((v) & 0x1) << 19) +#define BFM_RCC_PLLCFGR_DIVP2EN(v) BM_RCC_PLLCFGR_DIVP2EN +#define BF_RCC_PLLCFGR_DIVP2EN_V(e) BF_RCC_PLLCFGR_DIVP2EN(BV_RCC_PLLCFGR_DIVP2EN__##e) +#define BFM_RCC_PLLCFGR_DIVP2EN_V(v) BM_RCC_PLLCFGR_DIVP2EN +#define BP_RCC_PLLCFGR_DIVR1EN 18 +#define BM_RCC_PLLCFGR_DIVR1EN 0x40000 +#define BF_RCC_PLLCFGR_DIVR1EN(v) (((v) & 0x1) << 18) +#define BFM_RCC_PLLCFGR_DIVR1EN(v) BM_RCC_PLLCFGR_DIVR1EN +#define BF_RCC_PLLCFGR_DIVR1EN_V(e) BF_RCC_PLLCFGR_DIVR1EN(BV_RCC_PLLCFGR_DIVR1EN__##e) +#define BFM_RCC_PLLCFGR_DIVR1EN_V(v) BM_RCC_PLLCFGR_DIVR1EN +#define BP_RCC_PLLCFGR_DIVQ1EN 17 +#define BM_RCC_PLLCFGR_DIVQ1EN 0x20000 +#define BF_RCC_PLLCFGR_DIVQ1EN(v) (((v) & 0x1) << 17) +#define BFM_RCC_PLLCFGR_DIVQ1EN(v) BM_RCC_PLLCFGR_DIVQ1EN +#define BF_RCC_PLLCFGR_DIVQ1EN_V(e) BF_RCC_PLLCFGR_DIVQ1EN(BV_RCC_PLLCFGR_DIVQ1EN__##e) +#define BFM_RCC_PLLCFGR_DIVQ1EN_V(v) BM_RCC_PLLCFGR_DIVQ1EN +#define BP_RCC_PLLCFGR_DIVP1EN 16 +#define BM_RCC_PLLCFGR_DIVP1EN 0x10000 +#define BF_RCC_PLLCFGR_DIVP1EN(v) (((v) & 0x1) << 16) +#define BFM_RCC_PLLCFGR_DIVP1EN(v) BM_RCC_PLLCFGR_DIVP1EN +#define BF_RCC_PLLCFGR_DIVP1EN_V(e) BF_RCC_PLLCFGR_DIVP1EN(BV_RCC_PLLCFGR_DIVP1EN__##e) +#define BFM_RCC_PLLCFGR_DIVP1EN_V(v) BM_RCC_PLLCFGR_DIVP1EN +#define BP_RCC_PLLCFGR_PLL3VCOSEL 9 +#define BM_RCC_PLLCFGR_PLL3VCOSEL 0x200 +#define BV_RCC_PLLCFGR_PLL3VCOSEL__WIDE 0x0 +#define BV_RCC_PLLCFGR_PLL3VCOSEL__MEDIUM 0x1 +#define BF_RCC_PLLCFGR_PLL3VCOSEL(v) (((v) & 0x1) << 9) +#define BFM_RCC_PLLCFGR_PLL3VCOSEL(v) BM_RCC_PLLCFGR_PLL3VCOSEL +#define BF_RCC_PLLCFGR_PLL3VCOSEL_V(e) BF_RCC_PLLCFGR_PLL3VCOSEL(BV_RCC_PLLCFGR_PLL3VCOSEL__##e) +#define BFM_RCC_PLLCFGR_PLL3VCOSEL_V(v) BM_RCC_PLLCFGR_PLL3VCOSEL +#define BP_RCC_PLLCFGR_PLL3FRACEN 8 +#define BM_RCC_PLLCFGR_PLL3FRACEN 0x100 +#define BF_RCC_PLLCFGR_PLL3FRACEN(v) (((v) & 0x1) << 8) +#define BFM_RCC_PLLCFGR_PLL3FRACEN(v) BM_RCC_PLLCFGR_PLL3FRACEN +#define BF_RCC_PLLCFGR_PLL3FRACEN_V(e) BF_RCC_PLLCFGR_PLL3FRACEN(BV_RCC_PLLCFGR_PLL3FRACEN__##e) +#define BFM_RCC_PLLCFGR_PLL3FRACEN_V(v) BM_RCC_PLLCFGR_PLL3FRACEN +#define BP_RCC_PLLCFGR_PLL2VCOSEL 5 +#define BM_RCC_PLLCFGR_PLL2VCOSEL 0x20 +#define BV_RCC_PLLCFGR_PLL2VCOSEL__WIDE 0x0 +#define BV_RCC_PLLCFGR_PLL2VCOSEL__MEDIUM 0x1 +#define BF_RCC_PLLCFGR_PLL2VCOSEL(v) (((v) & 0x1) << 5) +#define BFM_RCC_PLLCFGR_PLL2VCOSEL(v) BM_RCC_PLLCFGR_PLL2VCOSEL +#define BF_RCC_PLLCFGR_PLL2VCOSEL_V(e) BF_RCC_PLLCFGR_PLL2VCOSEL(BV_RCC_PLLCFGR_PLL2VCOSEL__##e) +#define BFM_RCC_PLLCFGR_PLL2VCOSEL_V(v) BM_RCC_PLLCFGR_PLL2VCOSEL +#define BP_RCC_PLLCFGR_PLL2FRACEN 4 +#define BM_RCC_PLLCFGR_PLL2FRACEN 0x10 +#define BF_RCC_PLLCFGR_PLL2FRACEN(v) (((v) & 0x1) << 4) +#define BFM_RCC_PLLCFGR_PLL2FRACEN(v) BM_RCC_PLLCFGR_PLL2FRACEN +#define BF_RCC_PLLCFGR_PLL2FRACEN_V(e) BF_RCC_PLLCFGR_PLL2FRACEN(BV_RCC_PLLCFGR_PLL2FRACEN__##e) +#define BFM_RCC_PLLCFGR_PLL2FRACEN_V(v) BM_RCC_PLLCFGR_PLL2FRACEN +#define BP_RCC_PLLCFGR_PLL1VCOSEL 1 +#define BM_RCC_PLLCFGR_PLL1VCOSEL 0x2 +#define BV_RCC_PLLCFGR_PLL1VCOSEL__WIDE 0x0 +#define BV_RCC_PLLCFGR_PLL1VCOSEL__MEDIUM 0x1 +#define BF_RCC_PLLCFGR_PLL1VCOSEL(v) (((v) & 0x1) << 1) +#define BFM_RCC_PLLCFGR_PLL1VCOSEL(v) BM_RCC_PLLCFGR_PLL1VCOSEL +#define BF_RCC_PLLCFGR_PLL1VCOSEL_V(e) BF_RCC_PLLCFGR_PLL1VCOSEL(BV_RCC_PLLCFGR_PLL1VCOSEL__##e) +#define BFM_RCC_PLLCFGR_PLL1VCOSEL_V(v) BM_RCC_PLLCFGR_PLL1VCOSEL +#define BP_RCC_PLLCFGR_PLL1FRACEN 0 +#define BM_RCC_PLLCFGR_PLL1FRACEN 0x1 +#define BF_RCC_PLLCFGR_PLL1FRACEN(v) (((v) & 0x1) << 0) +#define BFM_RCC_PLLCFGR_PLL1FRACEN(v) BM_RCC_PLLCFGR_PLL1FRACEN +#define BF_RCC_PLLCFGR_PLL1FRACEN_V(e) BF_RCC_PLLCFGR_PLL1FRACEN(BV_RCC_PLLCFGR_PLL1FRACEN__##e) +#define BFM_RCC_PLLCFGR_PLL1FRACEN_V(v) BM_RCC_PLLCFGR_PLL1FRACEN + +#define REG_RCC_PLL1DIVR st_reg(RCC_PLL1DIVR) +#define STA_RCC_PLL1DIVR (0x58024400 + 0x30) +#define STO_RCC_PLL1DIVR (0x30) +#define STT_RCC_PLL1DIVR STIO_32_RW +#define STN_RCC_PLL1DIVR RCC_PLL1DIVR +#define BP_RCC_PLL1DIVR_DIVR 24 +#define BM_RCC_PLL1DIVR_DIVR 0x7f000000 +#define BF_RCC_PLL1DIVR_DIVR(v) (((v) & 0x7f) << 24) +#define BFM_RCC_PLL1DIVR_DIVR(v) BM_RCC_PLL1DIVR_DIVR +#define BF_RCC_PLL1DIVR_DIVR_V(e) BF_RCC_PLL1DIVR_DIVR(BV_RCC_PLL1DIVR_DIVR__##e) +#define BFM_RCC_PLL1DIVR_DIVR_V(v) BM_RCC_PLL1DIVR_DIVR +#define BP_RCC_PLL1DIVR_DIVQ 16 +#define BM_RCC_PLL1DIVR_DIVQ 0x7f0000 +#define BF_RCC_PLL1DIVR_DIVQ(v) (((v) & 0x7f) << 16) +#define BFM_RCC_PLL1DIVR_DIVQ(v) BM_RCC_PLL1DIVR_DIVQ +#define BF_RCC_PLL1DIVR_DIVQ_V(e) BF_RCC_PLL1DIVR_DIVQ(BV_RCC_PLL1DIVR_DIVQ__##e) +#define BFM_RCC_PLL1DIVR_DIVQ_V(v) BM_RCC_PLL1DIVR_DIVQ +#define BP_RCC_PLL1DIVR_DIVP 9 +#define BM_RCC_PLL1DIVR_DIVP 0xfe00 +#define BF_RCC_PLL1DIVR_DIVP(v) (((v) & 0x7f) << 9) +#define BFM_RCC_PLL1DIVR_DIVP(v) BM_RCC_PLL1DIVR_DIVP +#define BF_RCC_PLL1DIVR_DIVP_V(e) BF_RCC_PLL1DIVR_DIVP(BV_RCC_PLL1DIVR_DIVP__##e) +#define BFM_RCC_PLL1DIVR_DIVP_V(v) BM_RCC_PLL1DIVR_DIVP +#define BP_RCC_PLL1DIVR_DIVN 0 +#define BM_RCC_PLL1DIVR_DIVN 0x1ff +#define BF_RCC_PLL1DIVR_DIVN(v) (((v) & 0x1ff) << 0) +#define BFM_RCC_PLL1DIVR_DIVN(v) BM_RCC_PLL1DIVR_DIVN +#define BF_RCC_PLL1DIVR_DIVN_V(e) BF_RCC_PLL1DIVR_DIVN(BV_RCC_PLL1DIVR_DIVN__##e) +#define BFM_RCC_PLL1DIVR_DIVN_V(v) BM_RCC_PLL1DIVR_DIVN + +#define REG_RCC_PLL2DIVR st_reg(RCC_PLL2DIVR) +#define STA_RCC_PLL2DIVR (0x58024400 + 0x38) +#define STO_RCC_PLL2DIVR (0x38) +#define STT_RCC_PLL2DIVR STIO_32_RW +#define STN_RCC_PLL2DIVR RCC_PLL2DIVR +#define BP_RCC_PLL2DIVR_DIVR 24 +#define BM_RCC_PLL2DIVR_DIVR 0x7f000000 +#define BF_RCC_PLL2DIVR_DIVR(v) (((v) & 0x7f) << 24) +#define BFM_RCC_PLL2DIVR_DIVR(v) BM_RCC_PLL2DIVR_DIVR +#define BF_RCC_PLL2DIVR_DIVR_V(e) BF_RCC_PLL2DIVR_DIVR(BV_RCC_PLL2DIVR_DIVR__##e) +#define BFM_RCC_PLL2DIVR_DIVR_V(v) BM_RCC_PLL2DIVR_DIVR +#define BP_RCC_PLL2DIVR_DIVQ 16 +#define BM_RCC_PLL2DIVR_DIVQ 0x7f0000 +#define BF_RCC_PLL2DIVR_DIVQ(v) (((v) & 0x7f) << 16) +#define BFM_RCC_PLL2DIVR_DIVQ(v) BM_RCC_PLL2DIVR_DIVQ +#define BF_RCC_PLL2DIVR_DIVQ_V(e) BF_RCC_PLL2DIVR_DIVQ(BV_RCC_PLL2DIVR_DIVQ__##e) +#define BFM_RCC_PLL2DIVR_DIVQ_V(v) BM_RCC_PLL2DIVR_DIVQ +#define BP_RCC_PLL2DIVR_DIVP 9 +#define BM_RCC_PLL2DIVR_DIVP 0xfe00 +#define BF_RCC_PLL2DIVR_DIVP(v) (((v) & 0x7f) << 9) +#define BFM_RCC_PLL2DIVR_DIVP(v) BM_RCC_PLL2DIVR_DIVP +#define BF_RCC_PLL2DIVR_DIVP_V(e) BF_RCC_PLL2DIVR_DIVP(BV_RCC_PLL2DIVR_DIVP__##e) +#define BFM_RCC_PLL2DIVR_DIVP_V(v) BM_RCC_PLL2DIVR_DIVP +#define BP_RCC_PLL2DIVR_DIVN 0 +#define BM_RCC_PLL2DIVR_DIVN 0x1ff +#define BF_RCC_PLL2DIVR_DIVN(v) (((v) & 0x1ff) << 0) +#define BFM_RCC_PLL2DIVR_DIVN(v) BM_RCC_PLL2DIVR_DIVN +#define BF_RCC_PLL2DIVR_DIVN_V(e) BF_RCC_PLL2DIVR_DIVN(BV_RCC_PLL2DIVR_DIVN__##e) +#define BFM_RCC_PLL2DIVR_DIVN_V(v) BM_RCC_PLL2DIVR_DIVN + +#define REG_RCC_PLL3DIVR st_reg(RCC_PLL3DIVR) +#define STA_RCC_PLL3DIVR (0x58024400 + 0x40) +#define STO_RCC_PLL3DIVR (0x40) +#define STT_RCC_PLL3DIVR STIO_32_RW +#define STN_RCC_PLL3DIVR RCC_PLL3DIVR +#define BP_RCC_PLL3DIVR_DIVR 24 +#define BM_RCC_PLL3DIVR_DIVR 0x7f000000 +#define BF_RCC_PLL3DIVR_DIVR(v) (((v) & 0x7f) << 24) +#define BFM_RCC_PLL3DIVR_DIVR(v) BM_RCC_PLL3DIVR_DIVR +#define BF_RCC_PLL3DIVR_DIVR_V(e) BF_RCC_PLL3DIVR_DIVR(BV_RCC_PLL3DIVR_DIVR__##e) +#define BFM_RCC_PLL3DIVR_DIVR_V(v) BM_RCC_PLL3DIVR_DIVR +#define BP_RCC_PLL3DIVR_DIVQ 16 +#define BM_RCC_PLL3DIVR_DIVQ 0x7f0000 +#define BF_RCC_PLL3DIVR_DIVQ(v) (((v) & 0x7f) << 16) +#define BFM_RCC_PLL3DIVR_DIVQ(v) BM_RCC_PLL3DIVR_DIVQ +#define BF_RCC_PLL3DIVR_DIVQ_V(e) BF_RCC_PLL3DIVR_DIVQ(BV_RCC_PLL3DIVR_DIVQ__##e) +#define BFM_RCC_PLL3DIVR_DIVQ_V(v) BM_RCC_PLL3DIVR_DIVQ +#define BP_RCC_PLL3DIVR_DIVP 9 +#define BM_RCC_PLL3DIVR_DIVP 0xfe00 +#define BF_RCC_PLL3DIVR_DIVP(v) (((v) & 0x7f) << 9) +#define BFM_RCC_PLL3DIVR_DIVP(v) BM_RCC_PLL3DIVR_DIVP +#define BF_RCC_PLL3DIVR_DIVP_V(e) BF_RCC_PLL3DIVR_DIVP(BV_RCC_PLL3DIVR_DIVP__##e) +#define BFM_RCC_PLL3DIVR_DIVP_V(v) BM_RCC_PLL3DIVR_DIVP +#define BP_RCC_PLL3DIVR_DIVN 0 +#define BM_RCC_PLL3DIVR_DIVN 0x1ff +#define BF_RCC_PLL3DIVR_DIVN(v) (((v) & 0x1ff) << 0) +#define BFM_RCC_PLL3DIVR_DIVN(v) BM_RCC_PLL3DIVR_DIVN +#define BF_RCC_PLL3DIVR_DIVN_V(e) BF_RCC_PLL3DIVR_DIVN(BV_RCC_PLL3DIVR_DIVN__##e) +#define BFM_RCC_PLL3DIVR_DIVN_V(v) BM_RCC_PLL3DIVR_DIVN + +#define REG_RCC_PLL1FRACR st_reg(RCC_PLL1FRACR) +#define STA_RCC_PLL1FRACR (0x58024400 + 0x34) +#define STO_RCC_PLL1FRACR (0x34) +#define STT_RCC_PLL1FRACR STIO_32_RW +#define STN_RCC_PLL1FRACR RCC_PLL1FRACR +#define BP_RCC_PLL1FRACR_FRACN 3 +#define BM_RCC_PLL1FRACR_FRACN 0xfff8 +#define BF_RCC_PLL1FRACR_FRACN(v) (((v) & 0x1fff) << 3) +#define BFM_RCC_PLL1FRACR_FRACN(v) BM_RCC_PLL1FRACR_FRACN +#define BF_RCC_PLL1FRACR_FRACN_V(e) BF_RCC_PLL1FRACR_FRACN(BV_RCC_PLL1FRACR_FRACN__##e) +#define BFM_RCC_PLL1FRACR_FRACN_V(v) BM_RCC_PLL1FRACR_FRACN + +#define REG_RCC_PLL2FRACR st_reg(RCC_PLL2FRACR) +#define STA_RCC_PLL2FRACR (0x58024400 + 0x3c) +#define STO_RCC_PLL2FRACR (0x3c) +#define STT_RCC_PLL2FRACR STIO_32_RW +#define STN_RCC_PLL2FRACR RCC_PLL2FRACR +#define BP_RCC_PLL2FRACR_FRACN 3 +#define BM_RCC_PLL2FRACR_FRACN 0xfff8 +#define BF_RCC_PLL2FRACR_FRACN(v) (((v) & 0x1fff) << 3) +#define BFM_RCC_PLL2FRACR_FRACN(v) BM_RCC_PLL2FRACR_FRACN +#define BF_RCC_PLL2FRACR_FRACN_V(e) BF_RCC_PLL2FRACR_FRACN(BV_RCC_PLL2FRACR_FRACN__##e) +#define BFM_RCC_PLL2FRACR_FRACN_V(v) BM_RCC_PLL2FRACR_FRACN + +#define REG_RCC_PLL3FRACR st_reg(RCC_PLL3FRACR) +#define STA_RCC_PLL3FRACR (0x58024400 + 0x44) +#define STO_RCC_PLL3FRACR (0x44) +#define STT_RCC_PLL3FRACR STIO_32_RW +#define STN_RCC_PLL3FRACR RCC_PLL3FRACR +#define BP_RCC_PLL3FRACR_FRACN 3 +#define BM_RCC_PLL3FRACR_FRACN 0xfff8 +#define BF_RCC_PLL3FRACR_FRACN(v) (((v) & 0x1fff) << 3) +#define BFM_RCC_PLL3FRACR_FRACN(v) BM_RCC_PLL3FRACR_FRACN +#define BF_RCC_PLL3FRACR_FRACN_V(e) BF_RCC_PLL3FRACR_FRACN(BV_RCC_PLL3FRACR_FRACN__##e) +#define BFM_RCC_PLL3FRACR_FRACN_V(v) BM_RCC_PLL3FRACR_FRACN + +#define REG_RCC_D1CCIPR st_reg(RCC_D1CCIPR) +#define STA_RCC_D1CCIPR (0x58024400 + 0x4c) +#define STO_RCC_D1CCIPR (0x4c) +#define STT_RCC_D1CCIPR STIO_32_RW +#define STN_RCC_D1CCIPR RCC_D1CCIPR +#define BP_RCC_D1CCIPR_CKPERSEL 28 +#define BM_RCC_D1CCIPR_CKPERSEL 0x30000000 +#define BV_RCC_D1CCIPR_CKPERSEL__HSI 0x0 +#define BV_RCC_D1CCIPR_CKPERSEL__CSI 0x1 +#define BV_RCC_D1CCIPR_CKPERSEL__HSE 0x2 +#define BF_RCC_D1CCIPR_CKPERSEL(v) (((v) & 0x3) << 28) +#define BFM_RCC_D1CCIPR_CKPERSEL(v) BM_RCC_D1CCIPR_CKPERSEL +#define BF_RCC_D1CCIPR_CKPERSEL_V(e) BF_RCC_D1CCIPR_CKPERSEL(BV_RCC_D1CCIPR_CKPERSEL__##e) +#define BFM_RCC_D1CCIPR_CKPERSEL_V(v) BM_RCC_D1CCIPR_CKPERSEL +#define BP_RCC_D1CCIPR_QSPISEL 4 +#define BM_RCC_D1CCIPR_QSPISEL 0x30 +#define BV_RCC_D1CCIPR_QSPISEL__AHB 0x0 +#define BV_RCC_D1CCIPR_QSPISEL__PLL1Q 0x1 +#define BV_RCC_D1CCIPR_QSPISEL__PLL2R 0x2 +#define BV_RCC_D1CCIPR_QSPISEL__PER 0x3 +#define BF_RCC_D1CCIPR_QSPISEL(v) (((v) & 0x3) << 4) +#define BFM_RCC_D1CCIPR_QSPISEL(v) BM_RCC_D1CCIPR_QSPISEL +#define BF_RCC_D1CCIPR_QSPISEL_V(e) BF_RCC_D1CCIPR_QSPISEL(BV_RCC_D1CCIPR_QSPISEL__##e) +#define BFM_RCC_D1CCIPR_QSPISEL_V(v) BM_RCC_D1CCIPR_QSPISEL +#define BP_RCC_D1CCIPR_FMCSEL 0 +#define BM_RCC_D1CCIPR_FMCSEL 0x3 +#define BV_RCC_D1CCIPR_FMCSEL__AHB 0x0 +#define BV_RCC_D1CCIPR_FMCSEL__PLL1Q 0x1 +#define BV_RCC_D1CCIPR_FMCSEL__PLL2R 0x2 +#define BV_RCC_D1CCIPR_FMCSEL__PER 0x3 +#define BF_RCC_D1CCIPR_FMCSEL(v) (((v) & 0x3) << 0) +#define BFM_RCC_D1CCIPR_FMCSEL(v) BM_RCC_D1CCIPR_FMCSEL +#define BF_RCC_D1CCIPR_FMCSEL_V(e) BF_RCC_D1CCIPR_FMCSEL(BV_RCC_D1CCIPR_FMCSEL__##e) +#define BFM_RCC_D1CCIPR_FMCSEL_V(v) BM_RCC_D1CCIPR_FMCSEL +#define BP_RCC_D1CCIPR_SDMMCSEL 16 +#define BM_RCC_D1CCIPR_SDMMCSEL 0x10000 +#define BV_RCC_D1CCIPR_SDMMCSEL__PLL1Q 0x0 +#define BV_RCC_D1CCIPR_SDMMCSEL__PLL2R 0x1 +#define BF_RCC_D1CCIPR_SDMMCSEL(v) (((v) & 0x1) << 16) +#define BFM_RCC_D1CCIPR_SDMMCSEL(v) BM_RCC_D1CCIPR_SDMMCSEL +#define BF_RCC_D1CCIPR_SDMMCSEL_V(e) BF_RCC_D1CCIPR_SDMMCSEL(BV_RCC_D1CCIPR_SDMMCSEL__##e) +#define BFM_RCC_D1CCIPR_SDMMCSEL_V(v) BM_RCC_D1CCIPR_SDMMCSEL + +#define REG_RCC_D2CCIP1R st_reg(RCC_D2CCIP1R) +#define STA_RCC_D2CCIP1R (0x58024400 + 0x50) +#define STO_RCC_D2CCIP1R (0x50) +#define STT_RCC_D2CCIP1R STIO_32_RW +#define STN_RCC_D2CCIP1R RCC_D2CCIP1R +#define BP_RCC_D2CCIP1R_FDCANSEL 28 +#define BM_RCC_D2CCIP1R_FDCANSEL 0x30000000 +#define BV_RCC_D2CCIP1R_FDCANSEL__HSE 0x0 +#define BV_RCC_D2CCIP1R_FDCANSEL__PLL1Q 0x1 +#define BV_RCC_D2CCIP1R_FDCANSEL__PLL2Q 0x1 +#define BF_RCC_D2CCIP1R_FDCANSEL(v) (((v) & 0x3) << 28) +#define BFM_RCC_D2CCIP1R_FDCANSEL(v) BM_RCC_D2CCIP1R_FDCANSEL +#define BF_RCC_D2CCIP1R_FDCANSEL_V(e) BF_RCC_D2CCIP1R_FDCANSEL(BV_RCC_D2CCIP1R_FDCANSEL__##e) +#define BFM_RCC_D2CCIP1R_FDCANSEL_V(v) BM_RCC_D2CCIP1R_FDCANSEL +#define BP_RCC_D2CCIP1R_SPDIFSEL 20 +#define BM_RCC_D2CCIP1R_SPDIFSEL 0x300000 +#define BV_RCC_D2CCIP1R_SPDIFSEL__PLL1Q 0x0 +#define BV_RCC_D2CCIP1R_SPDIFSEL__PLL2R 0x1 +#define BV_RCC_D2CCIP1R_SPDIFSEL__PLL3R 0x2 +#define BV_RCC_D2CCIP1R_SPDIFSEL__HSI 0x3 +#define BF_RCC_D2CCIP1R_SPDIFSEL(v) (((v) & 0x3) << 20) +#define BFM_RCC_D2CCIP1R_SPDIFSEL(v) BM_RCC_D2CCIP1R_SPDIFSEL +#define BF_RCC_D2CCIP1R_SPDIFSEL_V(e) BF_RCC_D2CCIP1R_SPDIFSEL(BV_RCC_D2CCIP1R_SPDIFSEL__##e) +#define BFM_RCC_D2CCIP1R_SPDIFSEL_V(v) BM_RCC_D2CCIP1R_SPDIFSEL +#define BP_RCC_D2CCIP1R_SPI45SEL 16 +#define BM_RCC_D2CCIP1R_SPI45SEL 0x70000 +#define BV_RCC_D2CCIP1R_SPI45SEL__APB2 0x0 +#define BV_RCC_D2CCIP1R_SPI45SEL__PLL2Q 0x1 +#define BV_RCC_D2CCIP1R_SPI45SEL__PLL3Q 0x2 +#define BV_RCC_D2CCIP1R_SPI45SEL__HSI 0x3 +#define BV_RCC_D2CCIP1R_SPI45SEL__CSI 0x4 +#define BV_RCC_D2CCIP1R_SPI45SEL__HSE 0x5 +#define BF_RCC_D2CCIP1R_SPI45SEL(v) (((v) & 0x7) << 16) +#define BFM_RCC_D2CCIP1R_SPI45SEL(v) BM_RCC_D2CCIP1R_SPI45SEL +#define BF_RCC_D2CCIP1R_SPI45SEL_V(e) BF_RCC_D2CCIP1R_SPI45SEL(BV_RCC_D2CCIP1R_SPI45SEL__##e) +#define BFM_RCC_D2CCIP1R_SPI45SEL_V(v) BM_RCC_D2CCIP1R_SPI45SEL +#define BP_RCC_D2CCIP1R_SPI123SEL 12 +#define BM_RCC_D2CCIP1R_SPI123SEL 0x7000 +#define BV_RCC_D2CCIP1R_SPI123SEL__PLL1Q 0x0 +#define BV_RCC_D2CCIP1R_SPI123SEL__PLL2P 0x1 +#define BV_RCC_D2CCIP1R_SPI123SEL__PLL3P 0x2 +#define BV_RCC_D2CCIP1R_SPI123SEL__I2SCKIN 0x3 +#define BV_RCC_D2CCIP1R_SPI123SEL__PER 0x4 +#define BF_RCC_D2CCIP1R_SPI123SEL(v) (((v) & 0x7) << 12) +#define BFM_RCC_D2CCIP1R_SPI123SEL(v) BM_RCC_D2CCIP1R_SPI123SEL +#define BF_RCC_D2CCIP1R_SPI123SEL_V(e) BF_RCC_D2CCIP1R_SPI123SEL(BV_RCC_D2CCIP1R_SPI123SEL__##e) +#define BFM_RCC_D2CCIP1R_SPI123SEL_V(v) BM_RCC_D2CCIP1R_SPI123SEL +#define BP_RCC_D2CCIP1R_SAI23SEL 6 +#define BM_RCC_D2CCIP1R_SAI23SEL 0x1c0 +#define BV_RCC_D2CCIP1R_SAI23SEL__PLL1Q 0x0 +#define BV_RCC_D2CCIP1R_SAI23SEL__PLL2P 0x1 +#define BV_RCC_D2CCIP1R_SAI23SEL__PLL3P 0x2 +#define BV_RCC_D2CCIP1R_SAI23SEL__I2SCKIN 0x4 +#define BV_RCC_D2CCIP1R_SAI23SEL__PER 0x4 +#define BF_RCC_D2CCIP1R_SAI23SEL(v) (((v) & 0x7) << 6) +#define BFM_RCC_D2CCIP1R_SAI23SEL(v) BM_RCC_D2CCIP1R_SAI23SEL +#define BF_RCC_D2CCIP1R_SAI23SEL_V(e) BF_RCC_D2CCIP1R_SAI23SEL(BV_RCC_D2CCIP1R_SAI23SEL__##e) +#define BFM_RCC_D2CCIP1R_SAI23SEL_V(v) BM_RCC_D2CCIP1R_SAI23SEL +#define BP_RCC_D2CCIP1R_SAI1SEL 0 +#define BM_RCC_D2CCIP1R_SAI1SEL 0x7 +#define BV_RCC_D2CCIP1R_SAI1SEL__PLL1Q 0x0 +#define BV_RCC_D2CCIP1R_SAI1SEL__PLL2P 0x1 +#define BV_RCC_D2CCIP1R_SAI1SEL__PLL3P 0x2 +#define BV_RCC_D2CCIP1R_SAI1SEL__I2SCKIN 0x4 +#define BV_RCC_D2CCIP1R_SAI1SEL__PER 0x4 +#define BF_RCC_D2CCIP1R_SAI1SEL(v) (((v) & 0x7) << 0) +#define BFM_RCC_D2CCIP1R_SAI1SEL(v) BM_RCC_D2CCIP1R_SAI1SEL +#define BF_RCC_D2CCIP1R_SAI1SEL_V(e) BF_RCC_D2CCIP1R_SAI1SEL(BV_RCC_D2CCIP1R_SAI1SEL__##e) +#define BFM_RCC_D2CCIP1R_SAI1SEL_V(v) BM_RCC_D2CCIP1R_SAI1SEL +#define BP_RCC_D2CCIP1R_SWPSEL 31 +#define BM_RCC_D2CCIP1R_SWPSEL 0x80000000 +#define BV_RCC_D2CCIP1R_SWPSEL__APB1 0x0 +#define BV_RCC_D2CCIP1R_SWPSEL__HSI 0x1 +#define BF_RCC_D2CCIP1R_SWPSEL(v) (((v) & 0x1) << 31) +#define BFM_RCC_D2CCIP1R_SWPSEL(v) BM_RCC_D2CCIP1R_SWPSEL +#define BF_RCC_D2CCIP1R_SWPSEL_V(e) BF_RCC_D2CCIP1R_SWPSEL(BV_RCC_D2CCIP1R_SWPSEL__##e) +#define BFM_RCC_D2CCIP1R_SWPSEL_V(v) BM_RCC_D2CCIP1R_SWPSEL +#define BP_RCC_D2CCIP1R_DFSDM1SEL 24 +#define BM_RCC_D2CCIP1R_DFSDM1SEL 0x1000000 +#define BV_RCC_D2CCIP1R_DFSDM1SEL__APB2 0x0 +#define BV_RCC_D2CCIP1R_DFSDM1SEL__SYSCLK 0x1 +#define BF_RCC_D2CCIP1R_DFSDM1SEL(v) (((v) & 0x1) << 24) +#define BFM_RCC_D2CCIP1R_DFSDM1SEL(v) BM_RCC_D2CCIP1R_DFSDM1SEL +#define BF_RCC_D2CCIP1R_DFSDM1SEL_V(e) BF_RCC_D2CCIP1R_DFSDM1SEL(BV_RCC_D2CCIP1R_DFSDM1SEL__##e) +#define BFM_RCC_D2CCIP1R_DFSDM1SEL_V(v) BM_RCC_D2CCIP1R_DFSDM1SEL + +#define REG_RCC_D2CCIP2R st_reg(RCC_D2CCIP2R) +#define STA_RCC_D2CCIP2R (0x58024400 + 0x54) +#define STO_RCC_D2CCIP2R (0x54) +#define STT_RCC_D2CCIP2R STIO_32_RW +#define STN_RCC_D2CCIP2R RCC_D2CCIP2R +#define BP_RCC_D2CCIP2R_LPTIM1SEL 28 +#define BM_RCC_D2CCIP2R_LPTIM1SEL 0x70000000 +#define BV_RCC_D2CCIP2R_LPTIM1SEL__APB1 0x0 +#define BV_RCC_D2CCIP2R_LPTIM1SEL__PLL2P 0x1 +#define BV_RCC_D2CCIP2R_LPTIM1SEL__PLL3R 0x2 +#define BV_RCC_D2CCIP2R_LPTIM1SEL__LSE 0x3 +#define BV_RCC_D2CCIP2R_LPTIM1SEL__LSI 0x4 +#define BV_RCC_D2CCIP2R_LPTIM1SEL__PER 0x5 +#define BF_RCC_D2CCIP2R_LPTIM1SEL(v) (((v) & 0x7) << 28) +#define BFM_RCC_D2CCIP2R_LPTIM1SEL(v) BM_RCC_D2CCIP2R_LPTIM1SEL +#define BF_RCC_D2CCIP2R_LPTIM1SEL_V(e) BF_RCC_D2CCIP2R_LPTIM1SEL(BV_RCC_D2CCIP2R_LPTIM1SEL__##e) +#define BFM_RCC_D2CCIP2R_LPTIM1SEL_V(v) BM_RCC_D2CCIP2R_LPTIM1SEL +#define BP_RCC_D2CCIP2R_CECSEL 22 +#define BM_RCC_D2CCIP2R_CECSEL 0xc00000 +#define BV_RCC_D2CCIP2R_CECSEL__LSE 0x0 +#define BV_RCC_D2CCIP2R_CECSEL__LSI 0x1 +#define BV_RCC_D2CCIP2R_CECSEL__CSI 0x2 +#define BF_RCC_D2CCIP2R_CECSEL(v) (((v) & 0x3) << 22) +#define BFM_RCC_D2CCIP2R_CECSEL(v) BM_RCC_D2CCIP2R_CECSEL +#define BF_RCC_D2CCIP2R_CECSEL_V(e) BF_RCC_D2CCIP2R_CECSEL(BV_RCC_D2CCIP2R_CECSEL__##e) +#define BFM_RCC_D2CCIP2R_CECSEL_V(v) BM_RCC_D2CCIP2R_CECSEL +#define BP_RCC_D2CCIP2R_USBSEL 20 +#define BM_RCC_D2CCIP2R_USBSEL 0x300000 +#define BV_RCC_D2CCIP2R_USBSEL__DISABLE 0x0 +#define BV_RCC_D2CCIP2R_USBSEL__PLL1Q 0x1 +#define BV_RCC_D2CCIP2R_USBSEL__PLL3Q 0x2 +#define BV_RCC_D2CCIP2R_USBSEL__HSI48 0x3 +#define BF_RCC_D2CCIP2R_USBSEL(v) (((v) & 0x3) << 20) +#define BFM_RCC_D2CCIP2R_USBSEL(v) BM_RCC_D2CCIP2R_USBSEL +#define BF_RCC_D2CCIP2R_USBSEL_V(e) BF_RCC_D2CCIP2R_USBSEL(BV_RCC_D2CCIP2R_USBSEL__##e) +#define BFM_RCC_D2CCIP2R_USBSEL_V(v) BM_RCC_D2CCIP2R_USBSEL +#define BP_RCC_D2CCIP2R_I2C123SEL 12 +#define BM_RCC_D2CCIP2R_I2C123SEL 0x3000 +#define BV_RCC_D2CCIP2R_I2C123SEL__APB1 0x0 +#define BV_RCC_D2CCIP2R_I2C123SEL__PLL3R 0x1 +#define BV_RCC_D2CCIP2R_I2C123SEL__HSI 0x2 +#define BV_RCC_D2CCIP2R_I2C123SEL__CSI 0x3 +#define BF_RCC_D2CCIP2R_I2C123SEL(v) (((v) & 0x3) << 12) +#define BFM_RCC_D2CCIP2R_I2C123SEL(v) BM_RCC_D2CCIP2R_I2C123SEL +#define BF_RCC_D2CCIP2R_I2C123SEL_V(e) BF_RCC_D2CCIP2R_I2C123SEL(BV_RCC_D2CCIP2R_I2C123SEL__##e) +#define BFM_RCC_D2CCIP2R_I2C123SEL_V(v) BM_RCC_D2CCIP2R_I2C123SEL +#define BP_RCC_D2CCIP2R_RNGSEL 8 +#define BM_RCC_D2CCIP2R_RNGSEL 0x300 +#define BV_RCC_D2CCIP2R_RNGSEL__HSI 0x0 +#define BV_RCC_D2CCIP2R_RNGSEL__PLL1Q 0x1 +#define BV_RCC_D2CCIP2R_RNGSEL__LSE 0x2 +#define BV_RCC_D2CCIP2R_RNGSEL__LSI 0x3 +#define BF_RCC_D2CCIP2R_RNGSEL(v) (((v) & 0x3) << 8) +#define BFM_RCC_D2CCIP2R_RNGSEL(v) BM_RCC_D2CCIP2R_RNGSEL +#define BF_RCC_D2CCIP2R_RNGSEL_V(e) BF_RCC_D2CCIP2R_RNGSEL(BV_RCC_D2CCIP2R_RNGSEL__##e) +#define BFM_RCC_D2CCIP2R_RNGSEL_V(v) BM_RCC_D2CCIP2R_RNGSEL +#define BP_RCC_D2CCIP2R_USART16SEL 3 +#define BM_RCC_D2CCIP2R_USART16SEL 0x38 +#define BV_RCC_D2CCIP2R_USART16SEL__APB2 0x0 +#define BV_RCC_D2CCIP2R_USART16SEL__PLL2Q 0x1 +#define BV_RCC_D2CCIP2R_USART16SEL__PLL3Q 0x2 +#define BV_RCC_D2CCIP2R_USART16SEL__HSI 0x3 +#define BV_RCC_D2CCIP2R_USART16SEL__CSI 0x4 +#define BV_RCC_D2CCIP2R_USART16SEL__LSE 0x5 +#define BF_RCC_D2CCIP2R_USART16SEL(v) (((v) & 0x7) << 3) +#define BFM_RCC_D2CCIP2R_USART16SEL(v) BM_RCC_D2CCIP2R_USART16SEL +#define BF_RCC_D2CCIP2R_USART16SEL_V(e) BF_RCC_D2CCIP2R_USART16SEL(BV_RCC_D2CCIP2R_USART16SEL__##e) +#define BFM_RCC_D2CCIP2R_USART16SEL_V(v) BM_RCC_D2CCIP2R_USART16SEL +#define BP_RCC_D2CCIP2R_USART234578SEL 0 +#define BM_RCC_D2CCIP2R_USART234578SEL 0x7 +#define BV_RCC_D2CCIP2R_USART234578SEL__APB1 0x0 +#define BV_RCC_D2CCIP2R_USART234578SEL__PLL2Q 0x1 +#define BV_RCC_D2CCIP2R_USART234578SEL__PLL3Q 0x2 +#define BV_RCC_D2CCIP2R_USART234578SEL__HSI 0x3 +#define BV_RCC_D2CCIP2R_USART234578SEL__CSI 0x4 +#define BV_RCC_D2CCIP2R_USART234578SEL__LSE 0x5 +#define BF_RCC_D2CCIP2R_USART234578SEL(v) (((v) & 0x7) << 0) +#define BFM_RCC_D2CCIP2R_USART234578SEL(v) BM_RCC_D2CCIP2R_USART234578SEL +#define BF_RCC_D2CCIP2R_USART234578SEL_V(e) BF_RCC_D2CCIP2R_USART234578SEL(BV_RCC_D2CCIP2R_USART234578SEL__##e) +#define BFM_RCC_D2CCIP2R_USART234578SEL_V(v) BM_RCC_D2CCIP2R_USART234578SEL + +#define REG_RCC_D3CCIPR st_reg(RCC_D3CCIPR) +#define STA_RCC_D3CCIPR (0x58024400 + 0x58) +#define STO_RCC_D3CCIPR (0x58) +#define STT_RCC_D3CCIPR STIO_32_RW +#define STN_RCC_D3CCIPR RCC_D3CCIPR +#define BP_RCC_D3CCIPR_SPI6SEL 28 +#define BM_RCC_D3CCIPR_SPI6SEL 0x70000000 +#define BV_RCC_D3CCIPR_SPI6SEL__APB4 0x0 +#define BV_RCC_D3CCIPR_SPI6SEL__PLL2Q 0x1 +#define BV_RCC_D3CCIPR_SPI6SEL__PLL3Q 0x2 +#define BV_RCC_D3CCIPR_SPI6SEL__HSI 0x3 +#define BV_RCC_D3CCIPR_SPI6SEL__CSI 0x4 +#define BV_RCC_D3CCIPR_SPI6SEL__HSE 0x5 +#define BF_RCC_D3CCIPR_SPI6SEL(v) (((v) & 0x7) << 28) +#define BFM_RCC_D3CCIPR_SPI6SEL(v) BM_RCC_D3CCIPR_SPI6SEL +#define BF_RCC_D3CCIPR_SPI6SEL_V(e) BF_RCC_D3CCIPR_SPI6SEL(BV_RCC_D3CCIPR_SPI6SEL__##e) +#define BFM_RCC_D3CCIPR_SPI6SEL_V(v) BM_RCC_D3CCIPR_SPI6SEL +#define BP_RCC_D3CCIPR_SAI4BSEL 24 +#define BM_RCC_D3CCIPR_SAI4BSEL 0x7000000 +#define BV_RCC_D3CCIPR_SAI4BSEL__PLL1Q 0x0 +#define BV_RCC_D3CCIPR_SAI4BSEL__PLL2P 0x1 +#define BV_RCC_D3CCIPR_SAI4BSEL__PLL3P 0x2 +#define BV_RCC_D3CCIPR_SAI4BSEL__I2S_CKIN 0x3 +#define BV_RCC_D3CCIPR_SAI4BSEL__PER 0x4 +#define BF_RCC_D3CCIPR_SAI4BSEL(v) (((v) & 0x7) << 24) +#define BFM_RCC_D3CCIPR_SAI4BSEL(v) BM_RCC_D3CCIPR_SAI4BSEL +#define BF_RCC_D3CCIPR_SAI4BSEL_V(e) BF_RCC_D3CCIPR_SAI4BSEL(BV_RCC_D3CCIPR_SAI4BSEL__##e) +#define BFM_RCC_D3CCIPR_SAI4BSEL_V(v) BM_RCC_D3CCIPR_SAI4BSEL +#define BP_RCC_D3CCIPR_SAI4ASEL 21 +#define BM_RCC_D3CCIPR_SAI4ASEL 0xe00000 +#define BV_RCC_D3CCIPR_SAI4ASEL__PLL1Q 0x0 +#define BV_RCC_D3CCIPR_SAI4ASEL__PLL2P 0x1 +#define BV_RCC_D3CCIPR_SAI4ASEL__PLL3P 0x2 +#define BV_RCC_D3CCIPR_SAI4ASEL__I2S_CKIN 0x3 +#define BV_RCC_D3CCIPR_SAI4ASEL__PER 0x4 +#define BF_RCC_D3CCIPR_SAI4ASEL(v) (((v) & 0x7) << 21) +#define BFM_RCC_D3CCIPR_SAI4ASEL(v) BM_RCC_D3CCIPR_SAI4ASEL +#define BF_RCC_D3CCIPR_SAI4ASEL_V(e) BF_RCC_D3CCIPR_SAI4ASEL(BV_RCC_D3CCIPR_SAI4ASEL__##e) +#define BFM_RCC_D3CCIPR_SAI4ASEL_V(v) BM_RCC_D3CCIPR_SAI4ASEL +#define BP_RCC_D3CCIPR_ADCSEL 16 +#define BM_RCC_D3CCIPR_ADCSEL 0x30000 +#define BV_RCC_D3CCIPR_ADCSEL__PLL2P 0x0 +#define BV_RCC_D3CCIPR_ADCSEL__PLL3R 0x1 +#define BV_RCC_D3CCIPR_ADCSEL__PER 0x2 +#define BF_RCC_D3CCIPR_ADCSEL(v) (((v) & 0x3) << 16) +#define BFM_RCC_D3CCIPR_ADCSEL(v) BM_RCC_D3CCIPR_ADCSEL +#define BF_RCC_D3CCIPR_ADCSEL_V(e) BF_RCC_D3CCIPR_ADCSEL(BV_RCC_D3CCIPR_ADCSEL__##e) +#define BFM_RCC_D3CCIPR_ADCSEL_V(v) BM_RCC_D3CCIPR_ADCSEL +#define BP_RCC_D3CCIPR_LPTIM345SEL 13 +#define BM_RCC_D3CCIPR_LPTIM345SEL 0xe000 +#define BV_RCC_D3CCIPR_LPTIM345SEL__APB4 0x0 +#define BV_RCC_D3CCIPR_LPTIM345SEL__PLL2P 0x1 +#define BV_RCC_D3CCIPR_LPTIM345SEL__PLL3R 0x2 +#define BV_RCC_D3CCIPR_LPTIM345SEL__LSE 0x3 +#define BV_RCC_D3CCIPR_LPTIM345SEL__LSI 0x4 +#define BV_RCC_D3CCIPR_LPTIM345SEL__PER 0x5 +#define BF_RCC_D3CCIPR_LPTIM345SEL(v) (((v) & 0x7) << 13) +#define BFM_RCC_D3CCIPR_LPTIM345SEL(v) BM_RCC_D3CCIPR_LPTIM345SEL +#define BF_RCC_D3CCIPR_LPTIM345SEL_V(e) BF_RCC_D3CCIPR_LPTIM345SEL(BV_RCC_D3CCIPR_LPTIM345SEL__##e) +#define BFM_RCC_D3CCIPR_LPTIM345SEL_V(v) BM_RCC_D3CCIPR_LPTIM345SEL +#define BP_RCC_D3CCIPR_LPTIM2SEL 10 +#define BM_RCC_D3CCIPR_LPTIM2SEL 0x1c00 +#define BV_RCC_D3CCIPR_LPTIM2SEL__APB4 0x0 +#define BV_RCC_D3CCIPR_LPTIM2SEL__PLL2P 0x1 +#define BV_RCC_D3CCIPR_LPTIM2SEL__PLL3R 0x2 +#define BV_RCC_D3CCIPR_LPTIM2SEL__LSE 0x3 +#define BV_RCC_D3CCIPR_LPTIM2SEL__LSI 0x4 +#define BV_RCC_D3CCIPR_LPTIM2SEL__PER 0x5 +#define BF_RCC_D3CCIPR_LPTIM2SEL(v) (((v) & 0x7) << 10) +#define BFM_RCC_D3CCIPR_LPTIM2SEL(v) BM_RCC_D3CCIPR_LPTIM2SEL +#define BF_RCC_D3CCIPR_LPTIM2SEL_V(e) BF_RCC_D3CCIPR_LPTIM2SEL(BV_RCC_D3CCIPR_LPTIM2SEL__##e) +#define BFM_RCC_D3CCIPR_LPTIM2SEL_V(v) BM_RCC_D3CCIPR_LPTIM2SEL +#define BP_RCC_D3CCIPR_I2C4SEL 8 +#define BM_RCC_D3CCIPR_I2C4SEL 0x300 +#define BV_RCC_D3CCIPR_I2C4SEL__APB4 0x0 +#define BV_RCC_D3CCIPR_I2C4SEL__PLL3R 0x1 +#define BV_RCC_D3CCIPR_I2C4SEL__HSI 0x2 +#define BV_RCC_D3CCIPR_I2C4SEL__CSI 0x3 +#define BF_RCC_D3CCIPR_I2C4SEL(v) (((v) & 0x3) << 8) +#define BFM_RCC_D3CCIPR_I2C4SEL(v) BM_RCC_D3CCIPR_I2C4SEL +#define BF_RCC_D3CCIPR_I2C4SEL_V(e) BF_RCC_D3CCIPR_I2C4SEL(BV_RCC_D3CCIPR_I2C4SEL__##e) +#define BFM_RCC_D3CCIPR_I2C4SEL_V(v) BM_RCC_D3CCIPR_I2C4SEL +#define BP_RCC_D3CCIPR_LPUART1SEL 0 +#define BM_RCC_D3CCIPR_LPUART1SEL 0x7 +#define BV_RCC_D3CCIPR_LPUART1SEL__APB4 0x0 +#define BV_RCC_D3CCIPR_LPUART1SEL__PLL2Q 0x1 +#define BV_RCC_D3CCIPR_LPUART1SEL__PLL3Q 0x2 +#define BV_RCC_D3CCIPR_LPUART1SEL__HSI 0x3 +#define BV_RCC_D3CCIPR_LPUART1SEL__CSI 0x4 +#define BV_RCC_D3CCIPR_LPUART1SEL__LSE 0x5 +#define BF_RCC_D3CCIPR_LPUART1SEL(v) (((v) & 0x7) << 0) +#define BFM_RCC_D3CCIPR_LPUART1SEL(v) BM_RCC_D3CCIPR_LPUART1SEL +#define BF_RCC_D3CCIPR_LPUART1SEL_V(e) BF_RCC_D3CCIPR_LPUART1SEL(BV_RCC_D3CCIPR_LPUART1SEL__##e) +#define BFM_RCC_D3CCIPR_LPUART1SEL_V(v) BM_RCC_D3CCIPR_LPUART1SEL + +#define REG_RCC_BDCR st_reg(RCC_BDCR) +#define STA_RCC_BDCR (0x58024400 + 0x70) +#define STO_RCC_BDCR (0x70) +#define STT_RCC_BDCR STIO_32_RW +#define STN_RCC_BDCR RCC_BDCR +#define BP_RCC_BDCR_RTCSEL 8 +#define BM_RCC_BDCR_RTCSEL 0x300 +#define BV_RCC_BDCR_RTCSEL__NONE 0x0 +#define BV_RCC_BDCR_RTCSEL__LSE 0x1 +#define BV_RCC_BDCR_RTCSEL__LSI 0x2 +#define BV_RCC_BDCR_RTCSEL__HSE 0x3 +#define BF_RCC_BDCR_RTCSEL(v) (((v) & 0x3) << 8) +#define BFM_RCC_BDCR_RTCSEL(v) BM_RCC_BDCR_RTCSEL +#define BF_RCC_BDCR_RTCSEL_V(e) BF_RCC_BDCR_RTCSEL(BV_RCC_BDCR_RTCSEL__##e) +#define BFM_RCC_BDCR_RTCSEL_V(v) BM_RCC_BDCR_RTCSEL +#define BP_RCC_BDCR_LSEDRV 3 +#define BM_RCC_BDCR_LSEDRV 0x18 +#define BV_RCC_BDCR_LSEDRV__LOW 0x0 +#define BV_RCC_BDCR_LSEDRV__MED_LOW 0x1 +#define BV_RCC_BDCR_LSEDRV__MED_HIGH 0x2 +#define BV_RCC_BDCR_LSEDRV__HIGH 0x3 +#define BF_RCC_BDCR_LSEDRV(v) (((v) & 0x3) << 3) +#define BFM_RCC_BDCR_LSEDRV(v) BM_RCC_BDCR_LSEDRV +#define BF_RCC_BDCR_LSEDRV_V(e) BF_RCC_BDCR_LSEDRV(BV_RCC_BDCR_LSEDRV__##e) +#define BFM_RCC_BDCR_LSEDRV_V(v) BM_RCC_BDCR_LSEDRV +#define BP_RCC_BDCR_BDRST 16 +#define BM_RCC_BDCR_BDRST 0x10000 +#define BF_RCC_BDCR_BDRST(v) (((v) & 0x1) << 16) +#define BFM_RCC_BDCR_BDRST(v) BM_RCC_BDCR_BDRST +#define BF_RCC_BDCR_BDRST_V(e) BF_RCC_BDCR_BDRST(BV_RCC_BDCR_BDRST__##e) +#define BFM_RCC_BDCR_BDRST_V(v) BM_RCC_BDCR_BDRST +#define BP_RCC_BDCR_RTCEN 15 +#define BM_RCC_BDCR_RTCEN 0x8000 +#define BF_RCC_BDCR_RTCEN(v) (((v) & 0x1) << 15) +#define BFM_RCC_BDCR_RTCEN(v) BM_RCC_BDCR_RTCEN +#define BF_RCC_BDCR_RTCEN_V(e) BF_RCC_BDCR_RTCEN(BV_RCC_BDCR_RTCEN__##e) +#define BFM_RCC_BDCR_RTCEN_V(v) BM_RCC_BDCR_RTCEN +#define BP_RCC_BDCR_LSECSSD 6 +#define BM_RCC_BDCR_LSECSSD 0x40 +#define BF_RCC_BDCR_LSECSSD(v) (((v) & 0x1) << 6) +#define BFM_RCC_BDCR_LSECSSD(v) BM_RCC_BDCR_LSECSSD +#define BF_RCC_BDCR_LSECSSD_V(e) BF_RCC_BDCR_LSECSSD(BV_RCC_BDCR_LSECSSD__##e) +#define BFM_RCC_BDCR_LSECSSD_V(v) BM_RCC_BDCR_LSECSSD +#define BP_RCC_BDCR_LSECSSON 5 +#define BM_RCC_BDCR_LSECSSON 0x20 +#define BF_RCC_BDCR_LSECSSON(v) (((v) & 0x1) << 5) +#define BFM_RCC_BDCR_LSECSSON(v) BM_RCC_BDCR_LSECSSON +#define BF_RCC_BDCR_LSECSSON_V(e) BF_RCC_BDCR_LSECSSON(BV_RCC_BDCR_LSECSSON__##e) +#define BFM_RCC_BDCR_LSECSSON_V(v) BM_RCC_BDCR_LSECSSON +#define BP_RCC_BDCR_LSEBYP 2 +#define BM_RCC_BDCR_LSEBYP 0x4 +#define BF_RCC_BDCR_LSEBYP(v) (((v) & 0x1) << 2) +#define BFM_RCC_BDCR_LSEBYP(v) BM_RCC_BDCR_LSEBYP +#define BF_RCC_BDCR_LSEBYP_V(e) BF_RCC_BDCR_LSEBYP(BV_RCC_BDCR_LSEBYP__##e) +#define BFM_RCC_BDCR_LSEBYP_V(v) BM_RCC_BDCR_LSEBYP +#define BP_RCC_BDCR_LSERDY 1 +#define BM_RCC_BDCR_LSERDY 0x2 +#define BF_RCC_BDCR_LSERDY(v) (((v) & 0x1) << 1) +#define BFM_RCC_BDCR_LSERDY(v) BM_RCC_BDCR_LSERDY +#define BF_RCC_BDCR_LSERDY_V(e) BF_RCC_BDCR_LSERDY(BV_RCC_BDCR_LSERDY__##e) +#define BFM_RCC_BDCR_LSERDY_V(v) BM_RCC_BDCR_LSERDY +#define BP_RCC_BDCR_LSEON 0 +#define BM_RCC_BDCR_LSEON 0x1 +#define BF_RCC_BDCR_LSEON(v) (((v) & 0x1) << 0) +#define BFM_RCC_BDCR_LSEON(v) BM_RCC_BDCR_LSEON +#define BF_RCC_BDCR_LSEON_V(e) BF_RCC_BDCR_LSEON(BV_RCC_BDCR_LSEON__##e) +#define BFM_RCC_BDCR_LSEON_V(v) BM_RCC_BDCR_LSEON + +#define REG_RCC_CSR st_reg(RCC_CSR) +#define STA_RCC_CSR (0x58024400 + 0x74) +#define STO_RCC_CSR (0x74) +#define STT_RCC_CSR STIO_32_RW +#define STN_RCC_CSR RCC_CSR +#define BP_RCC_CSR_LSIRDY 1 +#define BM_RCC_CSR_LSIRDY 0x2 +#define BF_RCC_CSR_LSIRDY(v) (((v) & 0x1) << 1) +#define BFM_RCC_CSR_LSIRDY(v) BM_RCC_CSR_LSIRDY +#define BF_RCC_CSR_LSIRDY_V(e) BF_RCC_CSR_LSIRDY(BV_RCC_CSR_LSIRDY__##e) +#define BFM_RCC_CSR_LSIRDY_V(v) BM_RCC_CSR_LSIRDY +#define BP_RCC_CSR_LSION 0 +#define BM_RCC_CSR_LSION 0x1 +#define BF_RCC_CSR_LSION(v) (((v) & 0x1) << 0) +#define BFM_RCC_CSR_LSION(v) BM_RCC_CSR_LSION +#define BF_RCC_CSR_LSION_V(e) BF_RCC_CSR_LSION(BV_RCC_CSR_LSION__##e) +#define BFM_RCC_CSR_LSION_V(v) BM_RCC_CSR_LSION + +#define REG_RCC_AHB3ENR st_reg(RCC_AHB3ENR) +#define STA_RCC_AHB3ENR (0x58024400 + 0xd4) +#define STO_RCC_AHB3ENR (0xd4) +#define STT_RCC_AHB3ENR STIO_32_RW +#define STN_RCC_AHB3ENR RCC_AHB3ENR +#define BP_RCC_AHB3ENR_AXISRAMEN 31 +#define BM_RCC_AHB3ENR_AXISRAMEN 0x80000000 +#define BF_RCC_AHB3ENR_AXISRAMEN(v) (((v) & 0x1) << 31) +#define BFM_RCC_AHB3ENR_AXISRAMEN(v) BM_RCC_AHB3ENR_AXISRAMEN +#define BF_RCC_AHB3ENR_AXISRAMEN_V(e) BF_RCC_AHB3ENR_AXISRAMEN(BV_RCC_AHB3ENR_AXISRAMEN__##e) +#define BFM_RCC_AHB3ENR_AXISRAMEN_V(v) BM_RCC_AHB3ENR_AXISRAMEN +#define BP_RCC_AHB3ENR_ITCMEN 30 +#define BM_RCC_AHB3ENR_ITCMEN 0x40000000 +#define BF_RCC_AHB3ENR_ITCMEN(v) (((v) & 0x1) << 30) +#define BFM_RCC_AHB3ENR_ITCMEN(v) BM_RCC_AHB3ENR_ITCMEN +#define BF_RCC_AHB3ENR_ITCMEN_V(e) BF_RCC_AHB3ENR_ITCMEN(BV_RCC_AHB3ENR_ITCMEN__##e) +#define BFM_RCC_AHB3ENR_ITCMEN_V(v) BM_RCC_AHB3ENR_ITCMEN +#define BP_RCC_AHB3ENR_DTCM2EN 29 +#define BM_RCC_AHB3ENR_DTCM2EN 0x20000000 +#define BF_RCC_AHB3ENR_DTCM2EN(v) (((v) & 0x1) << 29) +#define BFM_RCC_AHB3ENR_DTCM2EN(v) BM_RCC_AHB3ENR_DTCM2EN +#define BF_RCC_AHB3ENR_DTCM2EN_V(e) BF_RCC_AHB3ENR_DTCM2EN(BV_RCC_AHB3ENR_DTCM2EN__##e) +#define BFM_RCC_AHB3ENR_DTCM2EN_V(v) BM_RCC_AHB3ENR_DTCM2EN +#define BP_RCC_AHB3ENR_D1DTCM1EN 28 +#define BM_RCC_AHB3ENR_D1DTCM1EN 0x10000000 +#define BF_RCC_AHB3ENR_D1DTCM1EN(v) (((v) & 0x1) << 28) +#define BFM_RCC_AHB3ENR_D1DTCM1EN(v) BM_RCC_AHB3ENR_D1DTCM1EN +#define BF_RCC_AHB3ENR_D1DTCM1EN_V(e) BF_RCC_AHB3ENR_D1DTCM1EN(BV_RCC_AHB3ENR_D1DTCM1EN__##e) +#define BFM_RCC_AHB3ENR_D1DTCM1EN_V(v) BM_RCC_AHB3ENR_D1DTCM1EN +#define BP_RCC_AHB3ENR_SDMMC1EN 16 +#define BM_RCC_AHB3ENR_SDMMC1EN 0x10000 +#define BF_RCC_AHB3ENR_SDMMC1EN(v) (((v) & 0x1) << 16) +#define BFM_RCC_AHB3ENR_SDMMC1EN(v) BM_RCC_AHB3ENR_SDMMC1EN +#define BF_RCC_AHB3ENR_SDMMC1EN_V(e) BF_RCC_AHB3ENR_SDMMC1EN(BV_RCC_AHB3ENR_SDMMC1EN__##e) +#define BFM_RCC_AHB3ENR_SDMMC1EN_V(v) BM_RCC_AHB3ENR_SDMMC1EN +#define BP_RCC_AHB3ENR_QSPIEN 14 +#define BM_RCC_AHB3ENR_QSPIEN 0x4000 +#define BF_RCC_AHB3ENR_QSPIEN(v) (((v) & 0x1) << 14) +#define BFM_RCC_AHB3ENR_QSPIEN(v) BM_RCC_AHB3ENR_QSPIEN +#define BF_RCC_AHB3ENR_QSPIEN_V(e) BF_RCC_AHB3ENR_QSPIEN(BV_RCC_AHB3ENR_QSPIEN__##e) +#define BFM_RCC_AHB3ENR_QSPIEN_V(v) BM_RCC_AHB3ENR_QSPIEN +#define BP_RCC_AHB3ENR_FMCEN 12 +#define BM_RCC_AHB3ENR_FMCEN 0x1000 +#define BF_RCC_AHB3ENR_FMCEN(v) (((v) & 0x1) << 12) +#define BFM_RCC_AHB3ENR_FMCEN(v) BM_RCC_AHB3ENR_FMCEN +#define BF_RCC_AHB3ENR_FMCEN_V(e) BF_RCC_AHB3ENR_FMCEN(BV_RCC_AHB3ENR_FMCEN__##e) +#define BFM_RCC_AHB3ENR_FMCEN_V(v) BM_RCC_AHB3ENR_FMCEN +#define BP_RCC_AHB3ENR_FLASHEN 8 +#define BM_RCC_AHB3ENR_FLASHEN 0x100 +#define BF_RCC_AHB3ENR_FLASHEN(v) (((v) & 0x1) << 8) +#define BFM_RCC_AHB3ENR_FLASHEN(v) BM_RCC_AHB3ENR_FLASHEN +#define BF_RCC_AHB3ENR_FLASHEN_V(e) BF_RCC_AHB3ENR_FLASHEN(BV_RCC_AHB3ENR_FLASHEN__##e) +#define BFM_RCC_AHB3ENR_FLASHEN_V(v) BM_RCC_AHB3ENR_FLASHEN +#define BP_RCC_AHB3ENR_JPEGDECEN 5 +#define BM_RCC_AHB3ENR_JPEGDECEN 0x20 +#define BF_RCC_AHB3ENR_JPEGDECEN(v) (((v) & 0x1) << 5) +#define BFM_RCC_AHB3ENR_JPEGDECEN(v) BM_RCC_AHB3ENR_JPEGDECEN +#define BF_RCC_AHB3ENR_JPEGDECEN_V(e) BF_RCC_AHB3ENR_JPEGDECEN(BV_RCC_AHB3ENR_JPEGDECEN__##e) +#define BFM_RCC_AHB3ENR_JPEGDECEN_V(v) BM_RCC_AHB3ENR_JPEGDECEN +#define BP_RCC_AHB3ENR_DMA2DEN 4 +#define BM_RCC_AHB3ENR_DMA2DEN 0x10 +#define BF_RCC_AHB3ENR_DMA2DEN(v) (((v) & 0x1) << 4) +#define BFM_RCC_AHB3ENR_DMA2DEN(v) BM_RCC_AHB3ENR_DMA2DEN +#define BF_RCC_AHB3ENR_DMA2DEN_V(e) BF_RCC_AHB3ENR_DMA2DEN(BV_RCC_AHB3ENR_DMA2DEN__##e) +#define BFM_RCC_AHB3ENR_DMA2DEN_V(v) BM_RCC_AHB3ENR_DMA2DEN +#define BP_RCC_AHB3ENR_MDMAEN 0 +#define BM_RCC_AHB3ENR_MDMAEN 0x1 +#define BF_RCC_AHB3ENR_MDMAEN(v) (((v) & 0x1) << 0) +#define BFM_RCC_AHB3ENR_MDMAEN(v) BM_RCC_AHB3ENR_MDMAEN +#define BF_RCC_AHB3ENR_MDMAEN_V(e) BF_RCC_AHB3ENR_MDMAEN(BV_RCC_AHB3ENR_MDMAEN__##e) +#define BFM_RCC_AHB3ENR_MDMAEN_V(v) BM_RCC_AHB3ENR_MDMAEN + +#define REG_RCC_AHB3LPENR st_reg(RCC_AHB3LPENR) +#define STA_RCC_AHB3LPENR (0x58024400 + 0xfc) +#define STO_RCC_AHB3LPENR (0xfc) +#define STT_RCC_AHB3LPENR STIO_32_RW +#define STN_RCC_AHB3LPENR RCC_AHB3LPENR +#define BP_RCC_AHB3LPENR_AXISRAMEN 31 +#define BM_RCC_AHB3LPENR_AXISRAMEN 0x80000000 +#define BF_RCC_AHB3LPENR_AXISRAMEN(v) (((v) & 0x1) << 31) +#define BFM_RCC_AHB3LPENR_AXISRAMEN(v) BM_RCC_AHB3LPENR_AXISRAMEN +#define BF_RCC_AHB3LPENR_AXISRAMEN_V(e) BF_RCC_AHB3LPENR_AXISRAMEN(BV_RCC_AHB3LPENR_AXISRAMEN__##e) +#define BFM_RCC_AHB3LPENR_AXISRAMEN_V(v) BM_RCC_AHB3LPENR_AXISRAMEN +#define BP_RCC_AHB3LPENR_ITCMEN 30 +#define BM_RCC_AHB3LPENR_ITCMEN 0x40000000 +#define BF_RCC_AHB3LPENR_ITCMEN(v) (((v) & 0x1) << 30) +#define BFM_RCC_AHB3LPENR_ITCMEN(v) BM_RCC_AHB3LPENR_ITCMEN +#define BF_RCC_AHB3LPENR_ITCMEN_V(e) BF_RCC_AHB3LPENR_ITCMEN(BV_RCC_AHB3LPENR_ITCMEN__##e) +#define BFM_RCC_AHB3LPENR_ITCMEN_V(v) BM_RCC_AHB3LPENR_ITCMEN +#define BP_RCC_AHB3LPENR_DTCM2EN 29 +#define BM_RCC_AHB3LPENR_DTCM2EN 0x20000000 +#define BF_RCC_AHB3LPENR_DTCM2EN(v) (((v) & 0x1) << 29) +#define BFM_RCC_AHB3LPENR_DTCM2EN(v) BM_RCC_AHB3LPENR_DTCM2EN +#define BF_RCC_AHB3LPENR_DTCM2EN_V(e) BF_RCC_AHB3LPENR_DTCM2EN(BV_RCC_AHB3LPENR_DTCM2EN__##e) +#define BFM_RCC_AHB3LPENR_DTCM2EN_V(v) BM_RCC_AHB3LPENR_DTCM2EN +#define BP_RCC_AHB3LPENR_D1DTCM1EN 28 +#define BM_RCC_AHB3LPENR_D1DTCM1EN 0x10000000 +#define BF_RCC_AHB3LPENR_D1DTCM1EN(v) (((v) & 0x1) << 28) +#define BFM_RCC_AHB3LPENR_D1DTCM1EN(v) BM_RCC_AHB3LPENR_D1DTCM1EN +#define BF_RCC_AHB3LPENR_D1DTCM1EN_V(e) BF_RCC_AHB3LPENR_D1DTCM1EN(BV_RCC_AHB3LPENR_D1DTCM1EN__##e) +#define BFM_RCC_AHB3LPENR_D1DTCM1EN_V(v) BM_RCC_AHB3LPENR_D1DTCM1EN +#define BP_RCC_AHB3LPENR_SDMMC1EN 16 +#define BM_RCC_AHB3LPENR_SDMMC1EN 0x10000 +#define BF_RCC_AHB3LPENR_SDMMC1EN(v) (((v) & 0x1) << 16) +#define BFM_RCC_AHB3LPENR_SDMMC1EN(v) BM_RCC_AHB3LPENR_SDMMC1EN +#define BF_RCC_AHB3LPENR_SDMMC1EN_V(e) BF_RCC_AHB3LPENR_SDMMC1EN(BV_RCC_AHB3LPENR_SDMMC1EN__##e) +#define BFM_RCC_AHB3LPENR_SDMMC1EN_V(v) BM_RCC_AHB3LPENR_SDMMC1EN +#define BP_RCC_AHB3LPENR_QSPIEN 14 +#define BM_RCC_AHB3LPENR_QSPIEN 0x4000 +#define BF_RCC_AHB3LPENR_QSPIEN(v) (((v) & 0x1) << 14) +#define BFM_RCC_AHB3LPENR_QSPIEN(v) BM_RCC_AHB3LPENR_QSPIEN +#define BF_RCC_AHB3LPENR_QSPIEN_V(e) BF_RCC_AHB3LPENR_QSPIEN(BV_RCC_AHB3LPENR_QSPIEN__##e) +#define BFM_RCC_AHB3LPENR_QSPIEN_V(v) BM_RCC_AHB3LPENR_QSPIEN +#define BP_RCC_AHB3LPENR_FMCEN 12 +#define BM_RCC_AHB3LPENR_FMCEN 0x1000 +#define BF_RCC_AHB3LPENR_FMCEN(v) (((v) & 0x1) << 12) +#define BFM_RCC_AHB3LPENR_FMCEN(v) BM_RCC_AHB3LPENR_FMCEN +#define BF_RCC_AHB3LPENR_FMCEN_V(e) BF_RCC_AHB3LPENR_FMCEN(BV_RCC_AHB3LPENR_FMCEN__##e) +#define BFM_RCC_AHB3LPENR_FMCEN_V(v) BM_RCC_AHB3LPENR_FMCEN +#define BP_RCC_AHB3LPENR_FLASHEN 8 +#define BM_RCC_AHB3LPENR_FLASHEN 0x100 +#define BF_RCC_AHB3LPENR_FLASHEN(v) (((v) & 0x1) << 8) +#define BFM_RCC_AHB3LPENR_FLASHEN(v) BM_RCC_AHB3LPENR_FLASHEN +#define BF_RCC_AHB3LPENR_FLASHEN_V(e) BF_RCC_AHB3LPENR_FLASHEN(BV_RCC_AHB3LPENR_FLASHEN__##e) +#define BFM_RCC_AHB3LPENR_FLASHEN_V(v) BM_RCC_AHB3LPENR_FLASHEN +#define BP_RCC_AHB3LPENR_JPEGDECEN 5 +#define BM_RCC_AHB3LPENR_JPEGDECEN 0x20 +#define BF_RCC_AHB3LPENR_JPEGDECEN(v) (((v) & 0x1) << 5) +#define BFM_RCC_AHB3LPENR_JPEGDECEN(v) BM_RCC_AHB3LPENR_JPEGDECEN +#define BF_RCC_AHB3LPENR_JPEGDECEN_V(e) BF_RCC_AHB3LPENR_JPEGDECEN(BV_RCC_AHB3LPENR_JPEGDECEN__##e) +#define BFM_RCC_AHB3LPENR_JPEGDECEN_V(v) BM_RCC_AHB3LPENR_JPEGDECEN +#define BP_RCC_AHB3LPENR_DMA2DEN 4 +#define BM_RCC_AHB3LPENR_DMA2DEN 0x10 +#define BF_RCC_AHB3LPENR_DMA2DEN(v) (((v) & 0x1) << 4) +#define BFM_RCC_AHB3LPENR_DMA2DEN(v) BM_RCC_AHB3LPENR_DMA2DEN +#define BF_RCC_AHB3LPENR_DMA2DEN_V(e) BF_RCC_AHB3LPENR_DMA2DEN(BV_RCC_AHB3LPENR_DMA2DEN__##e) +#define BFM_RCC_AHB3LPENR_DMA2DEN_V(v) BM_RCC_AHB3LPENR_DMA2DEN +#define BP_RCC_AHB3LPENR_MDMAEN 0 +#define BM_RCC_AHB3LPENR_MDMAEN 0x1 +#define BF_RCC_AHB3LPENR_MDMAEN(v) (((v) & 0x1) << 0) +#define BFM_RCC_AHB3LPENR_MDMAEN(v) BM_RCC_AHB3LPENR_MDMAEN +#define BF_RCC_AHB3LPENR_MDMAEN_V(e) BF_RCC_AHB3LPENR_MDMAEN(BV_RCC_AHB3LPENR_MDMAEN__##e) +#define BFM_RCC_AHB3LPENR_MDMAEN_V(v) BM_RCC_AHB3LPENR_MDMAEN + +#define REG_RCC_AHB4ENR st_reg(RCC_AHB4ENR) +#define STA_RCC_AHB4ENR (0x58024400 + 0xe0) +#define STO_RCC_AHB4ENR (0xe0) +#define STT_RCC_AHB4ENR STIO_32_RW +#define STN_RCC_AHB4ENR RCC_AHB4ENR +#define BP_RCC_AHB4ENR_SRAM4EN 29 +#define BM_RCC_AHB4ENR_SRAM4EN 0x20000000 +#define BF_RCC_AHB4ENR_SRAM4EN(v) (((v) & 0x1) << 29) +#define BFM_RCC_AHB4ENR_SRAM4EN(v) BM_RCC_AHB4ENR_SRAM4EN +#define BF_RCC_AHB4ENR_SRAM4EN_V(e) BF_RCC_AHB4ENR_SRAM4EN(BV_RCC_AHB4ENR_SRAM4EN__##e) +#define BFM_RCC_AHB4ENR_SRAM4EN_V(v) BM_RCC_AHB4ENR_SRAM4EN +#define BP_RCC_AHB4ENR_BKPRAMEN 28 +#define BM_RCC_AHB4ENR_BKPRAMEN 0x10000000 +#define BF_RCC_AHB4ENR_BKPRAMEN(v) (((v) & 0x1) << 28) +#define BFM_RCC_AHB4ENR_BKPRAMEN(v) BM_RCC_AHB4ENR_BKPRAMEN +#define BF_RCC_AHB4ENR_BKPRAMEN_V(e) BF_RCC_AHB4ENR_BKPRAMEN(BV_RCC_AHB4ENR_BKPRAMEN__##e) +#define BFM_RCC_AHB4ENR_BKPRAMEN_V(v) BM_RCC_AHB4ENR_BKPRAMEN +#define BP_RCC_AHB4ENR_HSEMEN 25 +#define BM_RCC_AHB4ENR_HSEMEN 0x2000000 +#define BF_RCC_AHB4ENR_HSEMEN(v) (((v) & 0x1) << 25) +#define BFM_RCC_AHB4ENR_HSEMEN(v) BM_RCC_AHB4ENR_HSEMEN +#define BF_RCC_AHB4ENR_HSEMEN_V(e) BF_RCC_AHB4ENR_HSEMEN(BV_RCC_AHB4ENR_HSEMEN__##e) +#define BFM_RCC_AHB4ENR_HSEMEN_V(v) BM_RCC_AHB4ENR_HSEMEN +#define BP_RCC_AHB4ENR_ADC3EN 24 +#define BM_RCC_AHB4ENR_ADC3EN 0x1000000 +#define BF_RCC_AHB4ENR_ADC3EN(v) (((v) & 0x1) << 24) +#define BFM_RCC_AHB4ENR_ADC3EN(v) BM_RCC_AHB4ENR_ADC3EN +#define BF_RCC_AHB4ENR_ADC3EN_V(e) BF_RCC_AHB4ENR_ADC3EN(BV_RCC_AHB4ENR_ADC3EN__##e) +#define BFM_RCC_AHB4ENR_ADC3EN_V(v) BM_RCC_AHB4ENR_ADC3EN +#define BP_RCC_AHB4ENR_BDMAEN 21 +#define BM_RCC_AHB4ENR_BDMAEN 0x200000 +#define BF_RCC_AHB4ENR_BDMAEN(v) (((v) & 0x1) << 21) +#define BFM_RCC_AHB4ENR_BDMAEN(v) BM_RCC_AHB4ENR_BDMAEN +#define BF_RCC_AHB4ENR_BDMAEN_V(e) BF_RCC_AHB4ENR_BDMAEN(BV_RCC_AHB4ENR_BDMAEN__##e) +#define BFM_RCC_AHB4ENR_BDMAEN_V(v) BM_RCC_AHB4ENR_BDMAEN +#define BP_RCC_AHB4ENR_CRCEN 19 +#define BM_RCC_AHB4ENR_CRCEN 0x80000 +#define BF_RCC_AHB4ENR_CRCEN(v) (((v) & 0x1) << 19) +#define BFM_RCC_AHB4ENR_CRCEN(v) BM_RCC_AHB4ENR_CRCEN +#define BF_RCC_AHB4ENR_CRCEN_V(e) BF_RCC_AHB4ENR_CRCEN(BV_RCC_AHB4ENR_CRCEN__##e) +#define BFM_RCC_AHB4ENR_CRCEN_V(v) BM_RCC_AHB4ENR_CRCEN +#define BP_RCC_AHB4ENR_GPIOKEN 10 +#define BM_RCC_AHB4ENR_GPIOKEN 0x400 +#define BF_RCC_AHB4ENR_GPIOKEN(v) (((v) & 0x1) << 10) +#define BFM_RCC_AHB4ENR_GPIOKEN(v) BM_RCC_AHB4ENR_GPIOKEN +#define BF_RCC_AHB4ENR_GPIOKEN_V(e) BF_RCC_AHB4ENR_GPIOKEN(BV_RCC_AHB4ENR_GPIOKEN__##e) +#define BFM_RCC_AHB4ENR_GPIOKEN_V(v) BM_RCC_AHB4ENR_GPIOKEN +#define BP_RCC_AHB4ENR_GPIOJEN 9 +#define BM_RCC_AHB4ENR_GPIOJEN 0x200 +#define BF_RCC_AHB4ENR_GPIOJEN(v) (((v) & 0x1) << 9) +#define BFM_RCC_AHB4ENR_GPIOJEN(v) BM_RCC_AHB4ENR_GPIOJEN +#define BF_RCC_AHB4ENR_GPIOJEN_V(e) BF_RCC_AHB4ENR_GPIOJEN(BV_RCC_AHB4ENR_GPIOJEN__##e) +#define BFM_RCC_AHB4ENR_GPIOJEN_V(v) BM_RCC_AHB4ENR_GPIOJEN +#define BP_RCC_AHB4ENR_GPIOIEN 8 +#define BM_RCC_AHB4ENR_GPIOIEN 0x100 +#define BF_RCC_AHB4ENR_GPIOIEN(v) (((v) & 0x1) << 8) +#define BFM_RCC_AHB4ENR_GPIOIEN(v) BM_RCC_AHB4ENR_GPIOIEN +#define BF_RCC_AHB4ENR_GPIOIEN_V(e) BF_RCC_AHB4ENR_GPIOIEN(BV_RCC_AHB4ENR_GPIOIEN__##e) +#define BFM_RCC_AHB4ENR_GPIOIEN_V(v) BM_RCC_AHB4ENR_GPIOIEN +#define BP_RCC_AHB4ENR_GPIOHEN 7 +#define BM_RCC_AHB4ENR_GPIOHEN 0x80 +#define BF_RCC_AHB4ENR_GPIOHEN(v) (((v) & 0x1) << 7) +#define BFM_RCC_AHB4ENR_GPIOHEN(v) BM_RCC_AHB4ENR_GPIOHEN +#define BF_RCC_AHB4ENR_GPIOHEN_V(e) BF_RCC_AHB4ENR_GPIOHEN(BV_RCC_AHB4ENR_GPIOHEN__##e) +#define BFM_RCC_AHB4ENR_GPIOHEN_V(v) BM_RCC_AHB4ENR_GPIOHEN +#define BP_RCC_AHB4ENR_GPIOGEN 6 +#define BM_RCC_AHB4ENR_GPIOGEN 0x40 +#define BF_RCC_AHB4ENR_GPIOGEN(v) (((v) & 0x1) << 6) +#define BFM_RCC_AHB4ENR_GPIOGEN(v) BM_RCC_AHB4ENR_GPIOGEN +#define BF_RCC_AHB4ENR_GPIOGEN_V(e) BF_RCC_AHB4ENR_GPIOGEN(BV_RCC_AHB4ENR_GPIOGEN__##e) +#define BFM_RCC_AHB4ENR_GPIOGEN_V(v) BM_RCC_AHB4ENR_GPIOGEN +#define BP_RCC_AHB4ENR_GPIOFEN 5 +#define BM_RCC_AHB4ENR_GPIOFEN 0x20 +#define BF_RCC_AHB4ENR_GPIOFEN(v) (((v) & 0x1) << 5) +#define BFM_RCC_AHB4ENR_GPIOFEN(v) BM_RCC_AHB4ENR_GPIOFEN +#define BF_RCC_AHB4ENR_GPIOFEN_V(e) BF_RCC_AHB4ENR_GPIOFEN(BV_RCC_AHB4ENR_GPIOFEN__##e) +#define BFM_RCC_AHB4ENR_GPIOFEN_V(v) BM_RCC_AHB4ENR_GPIOFEN +#define BP_RCC_AHB4ENR_GPIOEEN 4 +#define BM_RCC_AHB4ENR_GPIOEEN 0x10 +#define BF_RCC_AHB4ENR_GPIOEEN(v) (((v) & 0x1) << 4) +#define BFM_RCC_AHB4ENR_GPIOEEN(v) BM_RCC_AHB4ENR_GPIOEEN +#define BF_RCC_AHB4ENR_GPIOEEN_V(e) BF_RCC_AHB4ENR_GPIOEEN(BV_RCC_AHB4ENR_GPIOEEN__##e) +#define BFM_RCC_AHB4ENR_GPIOEEN_V(v) BM_RCC_AHB4ENR_GPIOEEN +#define BP_RCC_AHB4ENR_GPIODEN 3 +#define BM_RCC_AHB4ENR_GPIODEN 0x8 +#define BF_RCC_AHB4ENR_GPIODEN(v) (((v) & 0x1) << 3) +#define BFM_RCC_AHB4ENR_GPIODEN(v) BM_RCC_AHB4ENR_GPIODEN +#define BF_RCC_AHB4ENR_GPIODEN_V(e) BF_RCC_AHB4ENR_GPIODEN(BV_RCC_AHB4ENR_GPIODEN__##e) +#define BFM_RCC_AHB4ENR_GPIODEN_V(v) BM_RCC_AHB4ENR_GPIODEN +#define BP_RCC_AHB4ENR_GPIOCEN 2 +#define BM_RCC_AHB4ENR_GPIOCEN 0x4 +#define BF_RCC_AHB4ENR_GPIOCEN(v) (((v) & 0x1) << 2) +#define BFM_RCC_AHB4ENR_GPIOCEN(v) BM_RCC_AHB4ENR_GPIOCEN +#define BF_RCC_AHB4ENR_GPIOCEN_V(e) BF_RCC_AHB4ENR_GPIOCEN(BV_RCC_AHB4ENR_GPIOCEN__##e) +#define BFM_RCC_AHB4ENR_GPIOCEN_V(v) BM_RCC_AHB4ENR_GPIOCEN +#define BP_RCC_AHB4ENR_GPIOBEN 1 +#define BM_RCC_AHB4ENR_GPIOBEN 0x2 +#define BF_RCC_AHB4ENR_GPIOBEN(v) (((v) & 0x1) << 1) +#define BFM_RCC_AHB4ENR_GPIOBEN(v) BM_RCC_AHB4ENR_GPIOBEN +#define BF_RCC_AHB4ENR_GPIOBEN_V(e) BF_RCC_AHB4ENR_GPIOBEN(BV_RCC_AHB4ENR_GPIOBEN__##e) +#define BFM_RCC_AHB4ENR_GPIOBEN_V(v) BM_RCC_AHB4ENR_GPIOBEN +#define BP_RCC_AHB4ENR_GPIOAEN 0 +#define BM_RCC_AHB4ENR_GPIOAEN 0x1 +#define BF_RCC_AHB4ENR_GPIOAEN(v) (((v) & 0x1) << 0) +#define BFM_RCC_AHB4ENR_GPIOAEN(v) BM_RCC_AHB4ENR_GPIOAEN +#define BF_RCC_AHB4ENR_GPIOAEN_V(e) BF_RCC_AHB4ENR_GPIOAEN(BV_RCC_AHB4ENR_GPIOAEN__##e) +#define BFM_RCC_AHB4ENR_GPIOAEN_V(v) BM_RCC_AHB4ENR_GPIOAEN + +#define REG_RCC_AHB4LPENR st_reg(RCC_AHB4LPENR) +#define STA_RCC_AHB4LPENR (0x58024400 + 0x108) +#define STO_RCC_AHB4LPENR (0x108) +#define STT_RCC_AHB4LPENR STIO_32_RW +#define STN_RCC_AHB4LPENR RCC_AHB4LPENR +#define BP_RCC_AHB4LPENR_SRAM4EN 29 +#define BM_RCC_AHB4LPENR_SRAM4EN 0x20000000 +#define BF_RCC_AHB4LPENR_SRAM4EN(v) (((v) & 0x1) << 29) +#define BFM_RCC_AHB4LPENR_SRAM4EN(v) BM_RCC_AHB4LPENR_SRAM4EN +#define BF_RCC_AHB4LPENR_SRAM4EN_V(e) BF_RCC_AHB4LPENR_SRAM4EN(BV_RCC_AHB4LPENR_SRAM4EN__##e) +#define BFM_RCC_AHB4LPENR_SRAM4EN_V(v) BM_RCC_AHB4LPENR_SRAM4EN +#define BP_RCC_AHB4LPENR_BKPRAMEN 28 +#define BM_RCC_AHB4LPENR_BKPRAMEN 0x10000000 +#define BF_RCC_AHB4LPENR_BKPRAMEN(v) (((v) & 0x1) << 28) +#define BFM_RCC_AHB4LPENR_BKPRAMEN(v) BM_RCC_AHB4LPENR_BKPRAMEN +#define BF_RCC_AHB4LPENR_BKPRAMEN_V(e) BF_RCC_AHB4LPENR_BKPRAMEN(BV_RCC_AHB4LPENR_BKPRAMEN__##e) +#define BFM_RCC_AHB4LPENR_BKPRAMEN_V(v) BM_RCC_AHB4LPENR_BKPRAMEN +#define BP_RCC_AHB4LPENR_HSEMEN 25 +#define BM_RCC_AHB4LPENR_HSEMEN 0x2000000 +#define BF_RCC_AHB4LPENR_HSEMEN(v) (((v) & 0x1) << 25) +#define BFM_RCC_AHB4LPENR_HSEMEN(v) BM_RCC_AHB4LPENR_HSEMEN +#define BF_RCC_AHB4LPENR_HSEMEN_V(e) BF_RCC_AHB4LPENR_HSEMEN(BV_RCC_AHB4LPENR_HSEMEN__##e) +#define BFM_RCC_AHB4LPENR_HSEMEN_V(v) BM_RCC_AHB4LPENR_HSEMEN +#define BP_RCC_AHB4LPENR_ADC3EN 24 +#define BM_RCC_AHB4LPENR_ADC3EN 0x1000000 +#define BF_RCC_AHB4LPENR_ADC3EN(v) (((v) & 0x1) << 24) +#define BFM_RCC_AHB4LPENR_ADC3EN(v) BM_RCC_AHB4LPENR_ADC3EN +#define BF_RCC_AHB4LPENR_ADC3EN_V(e) BF_RCC_AHB4LPENR_ADC3EN(BV_RCC_AHB4LPENR_ADC3EN__##e) +#define BFM_RCC_AHB4LPENR_ADC3EN_V(v) BM_RCC_AHB4LPENR_ADC3EN +#define BP_RCC_AHB4LPENR_BDMAEN 21 +#define BM_RCC_AHB4LPENR_BDMAEN 0x200000 +#define BF_RCC_AHB4LPENR_BDMAEN(v) (((v) & 0x1) << 21) +#define BFM_RCC_AHB4LPENR_BDMAEN(v) BM_RCC_AHB4LPENR_BDMAEN +#define BF_RCC_AHB4LPENR_BDMAEN_V(e) BF_RCC_AHB4LPENR_BDMAEN(BV_RCC_AHB4LPENR_BDMAEN__##e) +#define BFM_RCC_AHB4LPENR_BDMAEN_V(v) BM_RCC_AHB4LPENR_BDMAEN +#define BP_RCC_AHB4LPENR_CRCEN 19 +#define BM_RCC_AHB4LPENR_CRCEN 0x80000 +#define BF_RCC_AHB4LPENR_CRCEN(v) (((v) & 0x1) << 19) +#define BFM_RCC_AHB4LPENR_CRCEN(v) BM_RCC_AHB4LPENR_CRCEN +#define BF_RCC_AHB4LPENR_CRCEN_V(e) BF_RCC_AHB4LPENR_CRCEN(BV_RCC_AHB4LPENR_CRCEN__##e) +#define BFM_RCC_AHB4LPENR_CRCEN_V(v) BM_RCC_AHB4LPENR_CRCEN +#define BP_RCC_AHB4LPENR_GPIOKEN 10 +#define BM_RCC_AHB4LPENR_GPIOKEN 0x400 +#define BF_RCC_AHB4LPENR_GPIOKEN(v) (((v) & 0x1) << 10) +#define BFM_RCC_AHB4LPENR_GPIOKEN(v) BM_RCC_AHB4LPENR_GPIOKEN +#define BF_RCC_AHB4LPENR_GPIOKEN_V(e) BF_RCC_AHB4LPENR_GPIOKEN(BV_RCC_AHB4LPENR_GPIOKEN__##e) +#define BFM_RCC_AHB4LPENR_GPIOKEN_V(v) BM_RCC_AHB4LPENR_GPIOKEN +#define BP_RCC_AHB4LPENR_GPIOJEN 9 +#define BM_RCC_AHB4LPENR_GPIOJEN 0x200 +#define BF_RCC_AHB4LPENR_GPIOJEN(v) (((v) & 0x1) << 9) +#define BFM_RCC_AHB4LPENR_GPIOJEN(v) BM_RCC_AHB4LPENR_GPIOJEN +#define BF_RCC_AHB4LPENR_GPIOJEN_V(e) BF_RCC_AHB4LPENR_GPIOJEN(BV_RCC_AHB4LPENR_GPIOJEN__##e) +#define BFM_RCC_AHB4LPENR_GPIOJEN_V(v) BM_RCC_AHB4LPENR_GPIOJEN +#define BP_RCC_AHB4LPENR_GPIOIEN 8 +#define BM_RCC_AHB4LPENR_GPIOIEN 0x100 +#define BF_RCC_AHB4LPENR_GPIOIEN(v) (((v) & 0x1) << 8) +#define BFM_RCC_AHB4LPENR_GPIOIEN(v) BM_RCC_AHB4LPENR_GPIOIEN +#define BF_RCC_AHB4LPENR_GPIOIEN_V(e) BF_RCC_AHB4LPENR_GPIOIEN(BV_RCC_AHB4LPENR_GPIOIEN__##e) +#define BFM_RCC_AHB4LPENR_GPIOIEN_V(v) BM_RCC_AHB4LPENR_GPIOIEN +#define BP_RCC_AHB4LPENR_GPIOHEN 7 +#define BM_RCC_AHB4LPENR_GPIOHEN 0x80 +#define BF_RCC_AHB4LPENR_GPIOHEN(v) (((v) & 0x1) << 7) +#define BFM_RCC_AHB4LPENR_GPIOHEN(v) BM_RCC_AHB4LPENR_GPIOHEN +#define BF_RCC_AHB4LPENR_GPIOHEN_V(e) BF_RCC_AHB4LPENR_GPIOHEN(BV_RCC_AHB4LPENR_GPIOHEN__##e) +#define BFM_RCC_AHB4LPENR_GPIOHEN_V(v) BM_RCC_AHB4LPENR_GPIOHEN +#define BP_RCC_AHB4LPENR_GPIOGEN 6 +#define BM_RCC_AHB4LPENR_GPIOGEN 0x40 +#define BF_RCC_AHB4LPENR_GPIOGEN(v) (((v) & 0x1) << 6) +#define BFM_RCC_AHB4LPENR_GPIOGEN(v) BM_RCC_AHB4LPENR_GPIOGEN +#define BF_RCC_AHB4LPENR_GPIOGEN_V(e) BF_RCC_AHB4LPENR_GPIOGEN(BV_RCC_AHB4LPENR_GPIOGEN__##e) +#define BFM_RCC_AHB4LPENR_GPIOGEN_V(v) BM_RCC_AHB4LPENR_GPIOGEN +#define BP_RCC_AHB4LPENR_GPIOFEN 5 +#define BM_RCC_AHB4LPENR_GPIOFEN 0x20 +#define BF_RCC_AHB4LPENR_GPIOFEN(v) (((v) & 0x1) << 5) +#define BFM_RCC_AHB4LPENR_GPIOFEN(v) BM_RCC_AHB4LPENR_GPIOFEN +#define BF_RCC_AHB4LPENR_GPIOFEN_V(e) BF_RCC_AHB4LPENR_GPIOFEN(BV_RCC_AHB4LPENR_GPIOFEN__##e) +#define BFM_RCC_AHB4LPENR_GPIOFEN_V(v) BM_RCC_AHB4LPENR_GPIOFEN +#define BP_RCC_AHB4LPENR_GPIOEEN 4 +#define BM_RCC_AHB4LPENR_GPIOEEN 0x10 +#define BF_RCC_AHB4LPENR_GPIOEEN(v) (((v) & 0x1) << 4) +#define BFM_RCC_AHB4LPENR_GPIOEEN(v) BM_RCC_AHB4LPENR_GPIOEEN +#define BF_RCC_AHB4LPENR_GPIOEEN_V(e) BF_RCC_AHB4LPENR_GPIOEEN(BV_RCC_AHB4LPENR_GPIOEEN__##e) +#define BFM_RCC_AHB4LPENR_GPIOEEN_V(v) BM_RCC_AHB4LPENR_GPIOEEN +#define BP_RCC_AHB4LPENR_GPIODEN 3 +#define BM_RCC_AHB4LPENR_GPIODEN 0x8 +#define BF_RCC_AHB4LPENR_GPIODEN(v) (((v) & 0x1) << 3) +#define BFM_RCC_AHB4LPENR_GPIODEN(v) BM_RCC_AHB4LPENR_GPIODEN +#define BF_RCC_AHB4LPENR_GPIODEN_V(e) BF_RCC_AHB4LPENR_GPIODEN(BV_RCC_AHB4LPENR_GPIODEN__##e) +#define BFM_RCC_AHB4LPENR_GPIODEN_V(v) BM_RCC_AHB4LPENR_GPIODEN +#define BP_RCC_AHB4LPENR_GPIOCEN 2 +#define BM_RCC_AHB4LPENR_GPIOCEN 0x4 +#define BF_RCC_AHB4LPENR_GPIOCEN(v) (((v) & 0x1) << 2) +#define BFM_RCC_AHB4LPENR_GPIOCEN(v) BM_RCC_AHB4LPENR_GPIOCEN +#define BF_RCC_AHB4LPENR_GPIOCEN_V(e) BF_RCC_AHB4LPENR_GPIOCEN(BV_RCC_AHB4LPENR_GPIOCEN__##e) +#define BFM_RCC_AHB4LPENR_GPIOCEN_V(v) BM_RCC_AHB4LPENR_GPIOCEN +#define BP_RCC_AHB4LPENR_GPIOBEN 1 +#define BM_RCC_AHB4LPENR_GPIOBEN 0x2 +#define BF_RCC_AHB4LPENR_GPIOBEN(v) (((v) & 0x1) << 1) +#define BFM_RCC_AHB4LPENR_GPIOBEN(v) BM_RCC_AHB4LPENR_GPIOBEN +#define BF_RCC_AHB4LPENR_GPIOBEN_V(e) BF_RCC_AHB4LPENR_GPIOBEN(BV_RCC_AHB4LPENR_GPIOBEN__##e) +#define BFM_RCC_AHB4LPENR_GPIOBEN_V(v) BM_RCC_AHB4LPENR_GPIOBEN +#define BP_RCC_AHB4LPENR_GPIOAEN 0 +#define BM_RCC_AHB4LPENR_GPIOAEN 0x1 +#define BF_RCC_AHB4LPENR_GPIOAEN(v) (((v) & 0x1) << 0) +#define BFM_RCC_AHB4LPENR_GPIOAEN(v) BM_RCC_AHB4LPENR_GPIOAEN +#define BF_RCC_AHB4LPENR_GPIOAEN_V(e) BF_RCC_AHB4LPENR_GPIOAEN(BV_RCC_AHB4LPENR_GPIOAEN__##e) +#define BFM_RCC_AHB4LPENR_GPIOAEN_V(v) BM_RCC_AHB4LPENR_GPIOAEN + +#define REG_RCC_APB3ENR st_reg(RCC_APB3ENR) +#define STA_RCC_APB3ENR (0x58024400 + 0xe4) +#define STO_RCC_APB3ENR (0xe4) +#define STT_RCC_APB3ENR STIO_32_RW +#define STN_RCC_APB3ENR RCC_APB3ENR +#define BP_RCC_APB3ENR_WWDG1EN 6 +#define BM_RCC_APB3ENR_WWDG1EN 0x40 +#define BF_RCC_APB3ENR_WWDG1EN(v) (((v) & 0x1) << 6) +#define BFM_RCC_APB3ENR_WWDG1EN(v) BM_RCC_APB3ENR_WWDG1EN +#define BF_RCC_APB3ENR_WWDG1EN_V(e) BF_RCC_APB3ENR_WWDG1EN(BV_RCC_APB3ENR_WWDG1EN__##e) +#define BFM_RCC_APB3ENR_WWDG1EN_V(v) BM_RCC_APB3ENR_WWDG1EN +#define BP_RCC_APB3ENR_LTDCEN 3 +#define BM_RCC_APB3ENR_LTDCEN 0x8 +#define BF_RCC_APB3ENR_LTDCEN(v) (((v) & 0x1) << 3) +#define BFM_RCC_APB3ENR_LTDCEN(v) BM_RCC_APB3ENR_LTDCEN +#define BF_RCC_APB3ENR_LTDCEN_V(e) BF_RCC_APB3ENR_LTDCEN(BV_RCC_APB3ENR_LTDCEN__##e) +#define BFM_RCC_APB3ENR_LTDCEN_V(v) BM_RCC_APB3ENR_LTDCEN + +#define REG_RCC_APB3LPENR st_reg(RCC_APB3LPENR) +#define STA_RCC_APB3LPENR (0x58024400 + 0x10c) +#define STO_RCC_APB3LPENR (0x10c) +#define STT_RCC_APB3LPENR STIO_32_RW +#define STN_RCC_APB3LPENR RCC_APB3LPENR +#define BP_RCC_APB3LPENR_WWDG1EN 6 +#define BM_RCC_APB3LPENR_WWDG1EN 0x40 +#define BF_RCC_APB3LPENR_WWDG1EN(v) (((v) & 0x1) << 6) +#define BFM_RCC_APB3LPENR_WWDG1EN(v) BM_RCC_APB3LPENR_WWDG1EN +#define BF_RCC_APB3LPENR_WWDG1EN_V(e) BF_RCC_APB3LPENR_WWDG1EN(BV_RCC_APB3LPENR_WWDG1EN__##e) +#define BFM_RCC_APB3LPENR_WWDG1EN_V(v) BM_RCC_APB3LPENR_WWDG1EN +#define BP_RCC_APB3LPENR_LTDCEN 3 +#define BM_RCC_APB3LPENR_LTDCEN 0x8 +#define BF_RCC_APB3LPENR_LTDCEN(v) (((v) & 0x1) << 3) +#define BFM_RCC_APB3LPENR_LTDCEN(v) BM_RCC_APB3LPENR_LTDCEN +#define BF_RCC_APB3LPENR_LTDCEN_V(e) BF_RCC_APB3LPENR_LTDCEN(BV_RCC_APB3LPENR_LTDCEN__##e) +#define BFM_RCC_APB3LPENR_LTDCEN_V(v) BM_RCC_APB3LPENR_LTDCEN + +#define REG_RCC_APB1LENR st_reg(RCC_APB1LENR) +#define STA_RCC_APB1LENR (0x58024400 + 0xe8) +#define STO_RCC_APB1LENR (0xe8) +#define STT_RCC_APB1LENR STIO_32_RW +#define STN_RCC_APB1LENR RCC_APB1LENR +#define BP_RCC_APB1LENR_UART8EN 31 +#define BM_RCC_APB1LENR_UART8EN 0x80000000 +#define BF_RCC_APB1LENR_UART8EN(v) (((v) & 0x1) << 31) +#define BFM_RCC_APB1LENR_UART8EN(v) BM_RCC_APB1LENR_UART8EN +#define BF_RCC_APB1LENR_UART8EN_V(e) BF_RCC_APB1LENR_UART8EN(BV_RCC_APB1LENR_UART8EN__##e) +#define BFM_RCC_APB1LENR_UART8EN_V(v) BM_RCC_APB1LENR_UART8EN +#define BP_RCC_APB1LENR_UART7EN 30 +#define BM_RCC_APB1LENR_UART7EN 0x40000000 +#define BF_RCC_APB1LENR_UART7EN(v) (((v) & 0x1) << 30) +#define BFM_RCC_APB1LENR_UART7EN(v) BM_RCC_APB1LENR_UART7EN +#define BF_RCC_APB1LENR_UART7EN_V(e) BF_RCC_APB1LENR_UART7EN(BV_RCC_APB1LENR_UART7EN__##e) +#define BFM_RCC_APB1LENR_UART7EN_V(v) BM_RCC_APB1LENR_UART7EN +#define BP_RCC_APB1LENR_DAC12EN 29 +#define BM_RCC_APB1LENR_DAC12EN 0x20000000 +#define BF_RCC_APB1LENR_DAC12EN(v) (((v) & 0x1) << 29) +#define BFM_RCC_APB1LENR_DAC12EN(v) BM_RCC_APB1LENR_DAC12EN +#define BF_RCC_APB1LENR_DAC12EN_V(e) BF_RCC_APB1LENR_DAC12EN(BV_RCC_APB1LENR_DAC12EN__##e) +#define BFM_RCC_APB1LENR_DAC12EN_V(v) BM_RCC_APB1LENR_DAC12EN +#define BP_RCC_APB1LENR_CECEN 27 +#define BM_RCC_APB1LENR_CECEN 0x8000000 +#define BF_RCC_APB1LENR_CECEN(v) (((v) & 0x1) << 27) +#define BFM_RCC_APB1LENR_CECEN(v) BM_RCC_APB1LENR_CECEN +#define BF_RCC_APB1LENR_CECEN_V(e) BF_RCC_APB1LENR_CECEN(BV_RCC_APB1LENR_CECEN__##e) +#define BFM_RCC_APB1LENR_CECEN_V(v) BM_RCC_APB1LENR_CECEN +#define BP_RCC_APB1LENR_I2C3EN 23 +#define BM_RCC_APB1LENR_I2C3EN 0x800000 +#define BF_RCC_APB1LENR_I2C3EN(v) (((v) & 0x1) << 23) +#define BFM_RCC_APB1LENR_I2C3EN(v) BM_RCC_APB1LENR_I2C3EN +#define BF_RCC_APB1LENR_I2C3EN_V(e) BF_RCC_APB1LENR_I2C3EN(BV_RCC_APB1LENR_I2C3EN__##e) +#define BFM_RCC_APB1LENR_I2C3EN_V(v) BM_RCC_APB1LENR_I2C3EN +#define BP_RCC_APB1LENR_I2C2EN 22 +#define BM_RCC_APB1LENR_I2C2EN 0x400000 +#define BF_RCC_APB1LENR_I2C2EN(v) (((v) & 0x1) << 22) +#define BFM_RCC_APB1LENR_I2C2EN(v) BM_RCC_APB1LENR_I2C2EN +#define BF_RCC_APB1LENR_I2C2EN_V(e) BF_RCC_APB1LENR_I2C2EN(BV_RCC_APB1LENR_I2C2EN__##e) +#define BFM_RCC_APB1LENR_I2C2EN_V(v) BM_RCC_APB1LENR_I2C2EN +#define BP_RCC_APB1LENR_I2C1EN 21 +#define BM_RCC_APB1LENR_I2C1EN 0x200000 +#define BF_RCC_APB1LENR_I2C1EN(v) (((v) & 0x1) << 21) +#define BFM_RCC_APB1LENR_I2C1EN(v) BM_RCC_APB1LENR_I2C1EN +#define BF_RCC_APB1LENR_I2C1EN_V(e) BF_RCC_APB1LENR_I2C1EN(BV_RCC_APB1LENR_I2C1EN__##e) +#define BFM_RCC_APB1LENR_I2C1EN_V(v) BM_RCC_APB1LENR_I2C1EN +#define BP_RCC_APB1LENR_UART5EN 20 +#define BM_RCC_APB1LENR_UART5EN 0x100000 +#define BF_RCC_APB1LENR_UART5EN(v) (((v) & 0x1) << 20) +#define BFM_RCC_APB1LENR_UART5EN(v) BM_RCC_APB1LENR_UART5EN +#define BF_RCC_APB1LENR_UART5EN_V(e) BF_RCC_APB1LENR_UART5EN(BV_RCC_APB1LENR_UART5EN__##e) +#define BFM_RCC_APB1LENR_UART5EN_V(v) BM_RCC_APB1LENR_UART5EN +#define BP_RCC_APB1LENR_UART4EN 19 +#define BM_RCC_APB1LENR_UART4EN 0x80000 +#define BF_RCC_APB1LENR_UART4EN(v) (((v) & 0x1) << 19) +#define BFM_RCC_APB1LENR_UART4EN(v) BM_RCC_APB1LENR_UART4EN +#define BF_RCC_APB1LENR_UART4EN_V(e) BF_RCC_APB1LENR_UART4EN(BV_RCC_APB1LENR_UART4EN__##e) +#define BFM_RCC_APB1LENR_UART4EN_V(v) BM_RCC_APB1LENR_UART4EN +#define BP_RCC_APB1LENR_USART3EN 18 +#define BM_RCC_APB1LENR_USART3EN 0x40000 +#define BF_RCC_APB1LENR_USART3EN(v) (((v) & 0x1) << 18) +#define BFM_RCC_APB1LENR_USART3EN(v) BM_RCC_APB1LENR_USART3EN +#define BF_RCC_APB1LENR_USART3EN_V(e) BF_RCC_APB1LENR_USART3EN(BV_RCC_APB1LENR_USART3EN__##e) +#define BFM_RCC_APB1LENR_USART3EN_V(v) BM_RCC_APB1LENR_USART3EN +#define BP_RCC_APB1LENR_USART2EN 17 +#define BM_RCC_APB1LENR_USART2EN 0x20000 +#define BF_RCC_APB1LENR_USART2EN(v) (((v) & 0x1) << 17) +#define BFM_RCC_APB1LENR_USART2EN(v) BM_RCC_APB1LENR_USART2EN +#define BF_RCC_APB1LENR_USART2EN_V(e) BF_RCC_APB1LENR_USART2EN(BV_RCC_APB1LENR_USART2EN__##e) +#define BFM_RCC_APB1LENR_USART2EN_V(v) BM_RCC_APB1LENR_USART2EN +#define BP_RCC_APB1LENR_SPDIFRXEN 16 +#define BM_RCC_APB1LENR_SPDIFRXEN 0x10000 +#define BF_RCC_APB1LENR_SPDIFRXEN(v) (((v) & 0x1) << 16) +#define BFM_RCC_APB1LENR_SPDIFRXEN(v) BM_RCC_APB1LENR_SPDIFRXEN +#define BF_RCC_APB1LENR_SPDIFRXEN_V(e) BF_RCC_APB1LENR_SPDIFRXEN(BV_RCC_APB1LENR_SPDIFRXEN__##e) +#define BFM_RCC_APB1LENR_SPDIFRXEN_V(v) BM_RCC_APB1LENR_SPDIFRXEN +#define BP_RCC_APB1LENR_SPI3EN 15 +#define BM_RCC_APB1LENR_SPI3EN 0x8000 +#define BF_RCC_APB1LENR_SPI3EN(v) (((v) & 0x1) << 15) +#define BFM_RCC_APB1LENR_SPI3EN(v) BM_RCC_APB1LENR_SPI3EN +#define BF_RCC_APB1LENR_SPI3EN_V(e) BF_RCC_APB1LENR_SPI3EN(BV_RCC_APB1LENR_SPI3EN__##e) +#define BFM_RCC_APB1LENR_SPI3EN_V(v) BM_RCC_APB1LENR_SPI3EN +#define BP_RCC_APB1LENR_SPI2EN 14 +#define BM_RCC_APB1LENR_SPI2EN 0x4000 +#define BF_RCC_APB1LENR_SPI2EN(v) (((v) & 0x1) << 14) +#define BFM_RCC_APB1LENR_SPI2EN(v) BM_RCC_APB1LENR_SPI2EN +#define BF_RCC_APB1LENR_SPI2EN_V(e) BF_RCC_APB1LENR_SPI2EN(BV_RCC_APB1LENR_SPI2EN__##e) +#define BFM_RCC_APB1LENR_SPI2EN_V(v) BM_RCC_APB1LENR_SPI2EN +#define BP_RCC_APB1LENR_LPTIM1EN 9 +#define BM_RCC_APB1LENR_LPTIM1EN 0x200 +#define BF_RCC_APB1LENR_LPTIM1EN(v) (((v) & 0x1) << 9) +#define BFM_RCC_APB1LENR_LPTIM1EN(v) BM_RCC_APB1LENR_LPTIM1EN +#define BF_RCC_APB1LENR_LPTIM1EN_V(e) BF_RCC_APB1LENR_LPTIM1EN(BV_RCC_APB1LENR_LPTIM1EN__##e) +#define BFM_RCC_APB1LENR_LPTIM1EN_V(v) BM_RCC_APB1LENR_LPTIM1EN +#define BP_RCC_APB1LENR_TIM14EN 8 +#define BM_RCC_APB1LENR_TIM14EN 0x100 +#define BF_RCC_APB1LENR_TIM14EN(v) (((v) & 0x1) << 8) +#define BFM_RCC_APB1LENR_TIM14EN(v) BM_RCC_APB1LENR_TIM14EN +#define BF_RCC_APB1LENR_TIM14EN_V(e) BF_RCC_APB1LENR_TIM14EN(BV_RCC_APB1LENR_TIM14EN__##e) +#define BFM_RCC_APB1LENR_TIM14EN_V(v) BM_RCC_APB1LENR_TIM14EN +#define BP_RCC_APB1LENR_TIM13EN 7 +#define BM_RCC_APB1LENR_TIM13EN 0x80 +#define BF_RCC_APB1LENR_TIM13EN(v) (((v) & 0x1) << 7) +#define BFM_RCC_APB1LENR_TIM13EN(v) BM_RCC_APB1LENR_TIM13EN +#define BF_RCC_APB1LENR_TIM13EN_V(e) BF_RCC_APB1LENR_TIM13EN(BV_RCC_APB1LENR_TIM13EN__##e) +#define BFM_RCC_APB1LENR_TIM13EN_V(v) BM_RCC_APB1LENR_TIM13EN +#define BP_RCC_APB1LENR_TIM12EN 6 +#define BM_RCC_APB1LENR_TIM12EN 0x40 +#define BF_RCC_APB1LENR_TIM12EN(v) (((v) & 0x1) << 6) +#define BFM_RCC_APB1LENR_TIM12EN(v) BM_RCC_APB1LENR_TIM12EN +#define BF_RCC_APB1LENR_TIM12EN_V(e) BF_RCC_APB1LENR_TIM12EN(BV_RCC_APB1LENR_TIM12EN__##e) +#define BFM_RCC_APB1LENR_TIM12EN_V(v) BM_RCC_APB1LENR_TIM12EN +#define BP_RCC_APB1LENR_TIM7EN 5 +#define BM_RCC_APB1LENR_TIM7EN 0x20 +#define BF_RCC_APB1LENR_TIM7EN(v) (((v) & 0x1) << 5) +#define BFM_RCC_APB1LENR_TIM7EN(v) BM_RCC_APB1LENR_TIM7EN +#define BF_RCC_APB1LENR_TIM7EN_V(e) BF_RCC_APB1LENR_TIM7EN(BV_RCC_APB1LENR_TIM7EN__##e) +#define BFM_RCC_APB1LENR_TIM7EN_V(v) BM_RCC_APB1LENR_TIM7EN +#define BP_RCC_APB1LENR_TIM6EN 4 +#define BM_RCC_APB1LENR_TIM6EN 0x10 +#define BF_RCC_APB1LENR_TIM6EN(v) (((v) & 0x1) << 4) +#define BFM_RCC_APB1LENR_TIM6EN(v) BM_RCC_APB1LENR_TIM6EN +#define BF_RCC_APB1LENR_TIM6EN_V(e) BF_RCC_APB1LENR_TIM6EN(BV_RCC_APB1LENR_TIM6EN__##e) +#define BFM_RCC_APB1LENR_TIM6EN_V(v) BM_RCC_APB1LENR_TIM6EN +#define BP_RCC_APB1LENR_TIM5EN 3 +#define BM_RCC_APB1LENR_TIM5EN 0x8 +#define BF_RCC_APB1LENR_TIM5EN(v) (((v) & 0x1) << 3) +#define BFM_RCC_APB1LENR_TIM5EN(v) BM_RCC_APB1LENR_TIM5EN +#define BF_RCC_APB1LENR_TIM5EN_V(e) BF_RCC_APB1LENR_TIM5EN(BV_RCC_APB1LENR_TIM5EN__##e) +#define BFM_RCC_APB1LENR_TIM5EN_V(v) BM_RCC_APB1LENR_TIM5EN +#define BP_RCC_APB1LENR_TIM4EN 2 +#define BM_RCC_APB1LENR_TIM4EN 0x4 +#define BF_RCC_APB1LENR_TIM4EN(v) (((v) & 0x1) << 2) +#define BFM_RCC_APB1LENR_TIM4EN(v) BM_RCC_APB1LENR_TIM4EN +#define BF_RCC_APB1LENR_TIM4EN_V(e) BF_RCC_APB1LENR_TIM4EN(BV_RCC_APB1LENR_TIM4EN__##e) +#define BFM_RCC_APB1LENR_TIM4EN_V(v) BM_RCC_APB1LENR_TIM4EN +#define BP_RCC_APB1LENR_TIM3EN 1 +#define BM_RCC_APB1LENR_TIM3EN 0x2 +#define BF_RCC_APB1LENR_TIM3EN(v) (((v) & 0x1) << 1) +#define BFM_RCC_APB1LENR_TIM3EN(v) BM_RCC_APB1LENR_TIM3EN +#define BF_RCC_APB1LENR_TIM3EN_V(e) BF_RCC_APB1LENR_TIM3EN(BV_RCC_APB1LENR_TIM3EN__##e) +#define BFM_RCC_APB1LENR_TIM3EN_V(v) BM_RCC_APB1LENR_TIM3EN +#define BP_RCC_APB1LENR_TIM2EN 0 +#define BM_RCC_APB1LENR_TIM2EN 0x1 +#define BF_RCC_APB1LENR_TIM2EN(v) (((v) & 0x1) << 0) +#define BFM_RCC_APB1LENR_TIM2EN(v) BM_RCC_APB1LENR_TIM2EN +#define BF_RCC_APB1LENR_TIM2EN_V(e) BF_RCC_APB1LENR_TIM2EN(BV_RCC_APB1LENR_TIM2EN__##e) +#define BFM_RCC_APB1LENR_TIM2EN_V(v) BM_RCC_APB1LENR_TIM2EN + +#define REG_RCC_APB1LLPENR st_reg(RCC_APB1LLPENR) +#define STA_RCC_APB1LLPENR (0x58024400 + 0x110) +#define STO_RCC_APB1LLPENR (0x110) +#define STT_RCC_APB1LLPENR STIO_32_RW +#define STN_RCC_APB1LLPENR RCC_APB1LLPENR +#define BP_RCC_APB1LLPENR_UART8EN 31 +#define BM_RCC_APB1LLPENR_UART8EN 0x80000000 +#define BF_RCC_APB1LLPENR_UART8EN(v) (((v) & 0x1) << 31) +#define BFM_RCC_APB1LLPENR_UART8EN(v) BM_RCC_APB1LLPENR_UART8EN +#define BF_RCC_APB1LLPENR_UART8EN_V(e) BF_RCC_APB1LLPENR_UART8EN(BV_RCC_APB1LLPENR_UART8EN__##e) +#define BFM_RCC_APB1LLPENR_UART8EN_V(v) BM_RCC_APB1LLPENR_UART8EN +#define BP_RCC_APB1LLPENR_UART7EN 30 +#define BM_RCC_APB1LLPENR_UART7EN 0x40000000 +#define BF_RCC_APB1LLPENR_UART7EN(v) (((v) & 0x1) << 30) +#define BFM_RCC_APB1LLPENR_UART7EN(v) BM_RCC_APB1LLPENR_UART7EN +#define BF_RCC_APB1LLPENR_UART7EN_V(e) BF_RCC_APB1LLPENR_UART7EN(BV_RCC_APB1LLPENR_UART7EN__##e) +#define BFM_RCC_APB1LLPENR_UART7EN_V(v) BM_RCC_APB1LLPENR_UART7EN +#define BP_RCC_APB1LLPENR_DAC12EN 29 +#define BM_RCC_APB1LLPENR_DAC12EN 0x20000000 +#define BF_RCC_APB1LLPENR_DAC12EN(v) (((v) & 0x1) << 29) +#define BFM_RCC_APB1LLPENR_DAC12EN(v) BM_RCC_APB1LLPENR_DAC12EN +#define BF_RCC_APB1LLPENR_DAC12EN_V(e) BF_RCC_APB1LLPENR_DAC12EN(BV_RCC_APB1LLPENR_DAC12EN__##e) +#define BFM_RCC_APB1LLPENR_DAC12EN_V(v) BM_RCC_APB1LLPENR_DAC12EN +#define BP_RCC_APB1LLPENR_CECEN 27 +#define BM_RCC_APB1LLPENR_CECEN 0x8000000 +#define BF_RCC_APB1LLPENR_CECEN(v) (((v) & 0x1) << 27) +#define BFM_RCC_APB1LLPENR_CECEN(v) BM_RCC_APB1LLPENR_CECEN +#define BF_RCC_APB1LLPENR_CECEN_V(e) BF_RCC_APB1LLPENR_CECEN(BV_RCC_APB1LLPENR_CECEN__##e) +#define BFM_RCC_APB1LLPENR_CECEN_V(v) BM_RCC_APB1LLPENR_CECEN +#define BP_RCC_APB1LLPENR_I2C3EN 23 +#define BM_RCC_APB1LLPENR_I2C3EN 0x800000 +#define BF_RCC_APB1LLPENR_I2C3EN(v) (((v) & 0x1) << 23) +#define BFM_RCC_APB1LLPENR_I2C3EN(v) BM_RCC_APB1LLPENR_I2C3EN +#define BF_RCC_APB1LLPENR_I2C3EN_V(e) BF_RCC_APB1LLPENR_I2C3EN(BV_RCC_APB1LLPENR_I2C3EN__##e) +#define BFM_RCC_APB1LLPENR_I2C3EN_V(v) BM_RCC_APB1LLPENR_I2C3EN +#define BP_RCC_APB1LLPENR_I2C2EN 22 +#define BM_RCC_APB1LLPENR_I2C2EN 0x400000 +#define BF_RCC_APB1LLPENR_I2C2EN(v) (((v) & 0x1) << 22) +#define BFM_RCC_APB1LLPENR_I2C2EN(v) BM_RCC_APB1LLPENR_I2C2EN +#define BF_RCC_APB1LLPENR_I2C2EN_V(e) BF_RCC_APB1LLPENR_I2C2EN(BV_RCC_APB1LLPENR_I2C2EN__##e) +#define BFM_RCC_APB1LLPENR_I2C2EN_V(v) BM_RCC_APB1LLPENR_I2C2EN +#define BP_RCC_APB1LLPENR_I2C1EN 21 +#define BM_RCC_APB1LLPENR_I2C1EN 0x200000 +#define BF_RCC_APB1LLPENR_I2C1EN(v) (((v) & 0x1) << 21) +#define BFM_RCC_APB1LLPENR_I2C1EN(v) BM_RCC_APB1LLPENR_I2C1EN +#define BF_RCC_APB1LLPENR_I2C1EN_V(e) BF_RCC_APB1LLPENR_I2C1EN(BV_RCC_APB1LLPENR_I2C1EN__##e) +#define BFM_RCC_APB1LLPENR_I2C1EN_V(v) BM_RCC_APB1LLPENR_I2C1EN +#define BP_RCC_APB1LLPENR_UART5EN 20 +#define BM_RCC_APB1LLPENR_UART5EN 0x100000 +#define BF_RCC_APB1LLPENR_UART5EN(v) (((v) & 0x1) << 20) +#define BFM_RCC_APB1LLPENR_UART5EN(v) BM_RCC_APB1LLPENR_UART5EN +#define BF_RCC_APB1LLPENR_UART5EN_V(e) BF_RCC_APB1LLPENR_UART5EN(BV_RCC_APB1LLPENR_UART5EN__##e) +#define BFM_RCC_APB1LLPENR_UART5EN_V(v) BM_RCC_APB1LLPENR_UART5EN +#define BP_RCC_APB1LLPENR_UART4EN 19 +#define BM_RCC_APB1LLPENR_UART4EN 0x80000 +#define BF_RCC_APB1LLPENR_UART4EN(v) (((v) & 0x1) << 19) +#define BFM_RCC_APB1LLPENR_UART4EN(v) BM_RCC_APB1LLPENR_UART4EN +#define BF_RCC_APB1LLPENR_UART4EN_V(e) BF_RCC_APB1LLPENR_UART4EN(BV_RCC_APB1LLPENR_UART4EN__##e) +#define BFM_RCC_APB1LLPENR_UART4EN_V(v) BM_RCC_APB1LLPENR_UART4EN +#define BP_RCC_APB1LLPENR_USART3EN 18 +#define BM_RCC_APB1LLPENR_USART3EN 0x40000 +#define BF_RCC_APB1LLPENR_USART3EN(v) (((v) & 0x1) << 18) +#define BFM_RCC_APB1LLPENR_USART3EN(v) BM_RCC_APB1LLPENR_USART3EN +#define BF_RCC_APB1LLPENR_USART3EN_V(e) BF_RCC_APB1LLPENR_USART3EN(BV_RCC_APB1LLPENR_USART3EN__##e) +#define BFM_RCC_APB1LLPENR_USART3EN_V(v) BM_RCC_APB1LLPENR_USART3EN +#define BP_RCC_APB1LLPENR_USART2EN 17 +#define BM_RCC_APB1LLPENR_USART2EN 0x20000 +#define BF_RCC_APB1LLPENR_USART2EN(v) (((v) & 0x1) << 17) +#define BFM_RCC_APB1LLPENR_USART2EN(v) BM_RCC_APB1LLPENR_USART2EN +#define BF_RCC_APB1LLPENR_USART2EN_V(e) BF_RCC_APB1LLPENR_USART2EN(BV_RCC_APB1LLPENR_USART2EN__##e) +#define BFM_RCC_APB1LLPENR_USART2EN_V(v) BM_RCC_APB1LLPENR_USART2EN +#define BP_RCC_APB1LLPENR_SPDIFRXEN 16 +#define BM_RCC_APB1LLPENR_SPDIFRXEN 0x10000 +#define BF_RCC_APB1LLPENR_SPDIFRXEN(v) (((v) & 0x1) << 16) +#define BFM_RCC_APB1LLPENR_SPDIFRXEN(v) BM_RCC_APB1LLPENR_SPDIFRXEN +#define BF_RCC_APB1LLPENR_SPDIFRXEN_V(e) BF_RCC_APB1LLPENR_SPDIFRXEN(BV_RCC_APB1LLPENR_SPDIFRXEN__##e) +#define BFM_RCC_APB1LLPENR_SPDIFRXEN_V(v) BM_RCC_APB1LLPENR_SPDIFRXEN +#define BP_RCC_APB1LLPENR_SPI3EN 15 +#define BM_RCC_APB1LLPENR_SPI3EN 0x8000 +#define BF_RCC_APB1LLPENR_SPI3EN(v) (((v) & 0x1) << 15) +#define BFM_RCC_APB1LLPENR_SPI3EN(v) BM_RCC_APB1LLPENR_SPI3EN +#define BF_RCC_APB1LLPENR_SPI3EN_V(e) BF_RCC_APB1LLPENR_SPI3EN(BV_RCC_APB1LLPENR_SPI3EN__##e) +#define BFM_RCC_APB1LLPENR_SPI3EN_V(v) BM_RCC_APB1LLPENR_SPI3EN +#define BP_RCC_APB1LLPENR_SPI2EN 14 +#define BM_RCC_APB1LLPENR_SPI2EN 0x4000 +#define BF_RCC_APB1LLPENR_SPI2EN(v) (((v) & 0x1) << 14) +#define BFM_RCC_APB1LLPENR_SPI2EN(v) BM_RCC_APB1LLPENR_SPI2EN +#define BF_RCC_APB1LLPENR_SPI2EN_V(e) BF_RCC_APB1LLPENR_SPI2EN(BV_RCC_APB1LLPENR_SPI2EN__##e) +#define BFM_RCC_APB1LLPENR_SPI2EN_V(v) BM_RCC_APB1LLPENR_SPI2EN +#define BP_RCC_APB1LLPENR_LPTIM1EN 9 +#define BM_RCC_APB1LLPENR_LPTIM1EN 0x200 +#define BF_RCC_APB1LLPENR_LPTIM1EN(v) (((v) & 0x1) << 9) +#define BFM_RCC_APB1LLPENR_LPTIM1EN(v) BM_RCC_APB1LLPENR_LPTIM1EN +#define BF_RCC_APB1LLPENR_LPTIM1EN_V(e) BF_RCC_APB1LLPENR_LPTIM1EN(BV_RCC_APB1LLPENR_LPTIM1EN__##e) +#define BFM_RCC_APB1LLPENR_LPTIM1EN_V(v) BM_RCC_APB1LLPENR_LPTIM1EN +#define BP_RCC_APB1LLPENR_TIM14EN 8 +#define BM_RCC_APB1LLPENR_TIM14EN 0x100 +#define BF_RCC_APB1LLPENR_TIM14EN(v) (((v) & 0x1) << 8) +#define BFM_RCC_APB1LLPENR_TIM14EN(v) BM_RCC_APB1LLPENR_TIM14EN +#define BF_RCC_APB1LLPENR_TIM14EN_V(e) BF_RCC_APB1LLPENR_TIM14EN(BV_RCC_APB1LLPENR_TIM14EN__##e) +#define BFM_RCC_APB1LLPENR_TIM14EN_V(v) BM_RCC_APB1LLPENR_TIM14EN +#define BP_RCC_APB1LLPENR_TIM13EN 7 +#define BM_RCC_APB1LLPENR_TIM13EN 0x80 +#define BF_RCC_APB1LLPENR_TIM13EN(v) (((v) & 0x1) << 7) +#define BFM_RCC_APB1LLPENR_TIM13EN(v) BM_RCC_APB1LLPENR_TIM13EN +#define BF_RCC_APB1LLPENR_TIM13EN_V(e) BF_RCC_APB1LLPENR_TIM13EN(BV_RCC_APB1LLPENR_TIM13EN__##e) +#define BFM_RCC_APB1LLPENR_TIM13EN_V(v) BM_RCC_APB1LLPENR_TIM13EN +#define BP_RCC_APB1LLPENR_TIM12EN 6 +#define BM_RCC_APB1LLPENR_TIM12EN 0x40 +#define BF_RCC_APB1LLPENR_TIM12EN(v) (((v) & 0x1) << 6) +#define BFM_RCC_APB1LLPENR_TIM12EN(v) BM_RCC_APB1LLPENR_TIM12EN +#define BF_RCC_APB1LLPENR_TIM12EN_V(e) BF_RCC_APB1LLPENR_TIM12EN(BV_RCC_APB1LLPENR_TIM12EN__##e) +#define BFM_RCC_APB1LLPENR_TIM12EN_V(v) BM_RCC_APB1LLPENR_TIM12EN +#define BP_RCC_APB1LLPENR_TIM7EN 5 +#define BM_RCC_APB1LLPENR_TIM7EN 0x20 +#define BF_RCC_APB1LLPENR_TIM7EN(v) (((v) & 0x1) << 5) +#define BFM_RCC_APB1LLPENR_TIM7EN(v) BM_RCC_APB1LLPENR_TIM7EN +#define BF_RCC_APB1LLPENR_TIM7EN_V(e) BF_RCC_APB1LLPENR_TIM7EN(BV_RCC_APB1LLPENR_TIM7EN__##e) +#define BFM_RCC_APB1LLPENR_TIM7EN_V(v) BM_RCC_APB1LLPENR_TIM7EN +#define BP_RCC_APB1LLPENR_TIM6EN 4 +#define BM_RCC_APB1LLPENR_TIM6EN 0x10 +#define BF_RCC_APB1LLPENR_TIM6EN(v) (((v) & 0x1) << 4) +#define BFM_RCC_APB1LLPENR_TIM6EN(v) BM_RCC_APB1LLPENR_TIM6EN +#define BF_RCC_APB1LLPENR_TIM6EN_V(e) BF_RCC_APB1LLPENR_TIM6EN(BV_RCC_APB1LLPENR_TIM6EN__##e) +#define BFM_RCC_APB1LLPENR_TIM6EN_V(v) BM_RCC_APB1LLPENR_TIM6EN +#define BP_RCC_APB1LLPENR_TIM5EN 3 +#define BM_RCC_APB1LLPENR_TIM5EN 0x8 +#define BF_RCC_APB1LLPENR_TIM5EN(v) (((v) & 0x1) << 3) +#define BFM_RCC_APB1LLPENR_TIM5EN(v) BM_RCC_APB1LLPENR_TIM5EN +#define BF_RCC_APB1LLPENR_TIM5EN_V(e) BF_RCC_APB1LLPENR_TIM5EN(BV_RCC_APB1LLPENR_TIM5EN__##e) +#define BFM_RCC_APB1LLPENR_TIM5EN_V(v) BM_RCC_APB1LLPENR_TIM5EN +#define BP_RCC_APB1LLPENR_TIM4EN 2 +#define BM_RCC_APB1LLPENR_TIM4EN 0x4 +#define BF_RCC_APB1LLPENR_TIM4EN(v) (((v) & 0x1) << 2) +#define BFM_RCC_APB1LLPENR_TIM4EN(v) BM_RCC_APB1LLPENR_TIM4EN +#define BF_RCC_APB1LLPENR_TIM4EN_V(e) BF_RCC_APB1LLPENR_TIM4EN(BV_RCC_APB1LLPENR_TIM4EN__##e) +#define BFM_RCC_APB1LLPENR_TIM4EN_V(v) BM_RCC_APB1LLPENR_TIM4EN +#define BP_RCC_APB1LLPENR_TIM3EN 1 +#define BM_RCC_APB1LLPENR_TIM3EN 0x2 +#define BF_RCC_APB1LLPENR_TIM3EN(v) (((v) & 0x1) << 1) +#define BFM_RCC_APB1LLPENR_TIM3EN(v) BM_RCC_APB1LLPENR_TIM3EN +#define BF_RCC_APB1LLPENR_TIM3EN_V(e) BF_RCC_APB1LLPENR_TIM3EN(BV_RCC_APB1LLPENR_TIM3EN__##e) +#define BFM_RCC_APB1LLPENR_TIM3EN_V(v) BM_RCC_APB1LLPENR_TIM3EN +#define BP_RCC_APB1LLPENR_TIM2EN 0 +#define BM_RCC_APB1LLPENR_TIM2EN 0x1 +#define BF_RCC_APB1LLPENR_TIM2EN(v) (((v) & 0x1) << 0) +#define BFM_RCC_APB1LLPENR_TIM2EN(v) BM_RCC_APB1LLPENR_TIM2EN +#define BF_RCC_APB1LLPENR_TIM2EN_V(e) BF_RCC_APB1LLPENR_TIM2EN(BV_RCC_APB1LLPENR_TIM2EN__##e) +#define BFM_RCC_APB1LLPENR_TIM2EN_V(v) BM_RCC_APB1LLPENR_TIM2EN + +#define REG_RCC_APB1HENR st_reg(RCC_APB1HENR) +#define STA_RCC_APB1HENR (0x58024400 + 0xec) +#define STO_RCC_APB1HENR (0xec) +#define STT_RCC_APB1HENR STIO_32_RW +#define STN_RCC_APB1HENR RCC_APB1HENR +#define BP_RCC_APB1HENR_FDCANEN 8 +#define BM_RCC_APB1HENR_FDCANEN 0x100 +#define BF_RCC_APB1HENR_FDCANEN(v) (((v) & 0x1) << 8) +#define BFM_RCC_APB1HENR_FDCANEN(v) BM_RCC_APB1HENR_FDCANEN +#define BF_RCC_APB1HENR_FDCANEN_V(e) BF_RCC_APB1HENR_FDCANEN(BV_RCC_APB1HENR_FDCANEN__##e) +#define BFM_RCC_APB1HENR_FDCANEN_V(v) BM_RCC_APB1HENR_FDCANEN +#define BP_RCC_APB1HENR_MDIOSEN 5 +#define BM_RCC_APB1HENR_MDIOSEN 0x20 +#define BF_RCC_APB1HENR_MDIOSEN(v) (((v) & 0x1) << 5) +#define BFM_RCC_APB1HENR_MDIOSEN(v) BM_RCC_APB1HENR_MDIOSEN +#define BF_RCC_APB1HENR_MDIOSEN_V(e) BF_RCC_APB1HENR_MDIOSEN(BV_RCC_APB1HENR_MDIOSEN__##e) +#define BFM_RCC_APB1HENR_MDIOSEN_V(v) BM_RCC_APB1HENR_MDIOSEN +#define BP_RCC_APB1HENR_OPAMPEN 4 +#define BM_RCC_APB1HENR_OPAMPEN 0x10 +#define BF_RCC_APB1HENR_OPAMPEN(v) (((v) & 0x1) << 4) +#define BFM_RCC_APB1HENR_OPAMPEN(v) BM_RCC_APB1HENR_OPAMPEN +#define BF_RCC_APB1HENR_OPAMPEN_V(e) BF_RCC_APB1HENR_OPAMPEN(BV_RCC_APB1HENR_OPAMPEN__##e) +#define BFM_RCC_APB1HENR_OPAMPEN_V(v) BM_RCC_APB1HENR_OPAMPEN +#define BP_RCC_APB1HENR_SWPEN 2 +#define BM_RCC_APB1HENR_SWPEN 0x4 +#define BF_RCC_APB1HENR_SWPEN(v) (((v) & 0x1) << 2) +#define BFM_RCC_APB1HENR_SWPEN(v) BM_RCC_APB1HENR_SWPEN +#define BF_RCC_APB1HENR_SWPEN_V(e) BF_RCC_APB1HENR_SWPEN(BV_RCC_APB1HENR_SWPEN__##e) +#define BFM_RCC_APB1HENR_SWPEN_V(v) BM_RCC_APB1HENR_SWPEN +#define BP_RCC_APB1HENR_CRSEN 1 +#define BM_RCC_APB1HENR_CRSEN 0x2 +#define BF_RCC_APB1HENR_CRSEN(v) (((v) & 0x1) << 1) +#define BFM_RCC_APB1HENR_CRSEN(v) BM_RCC_APB1HENR_CRSEN +#define BF_RCC_APB1HENR_CRSEN_V(e) BF_RCC_APB1HENR_CRSEN(BV_RCC_APB1HENR_CRSEN__##e) +#define BFM_RCC_APB1HENR_CRSEN_V(v) BM_RCC_APB1HENR_CRSEN + +#define REG_RCC_APB1HLPENR st_reg(RCC_APB1HLPENR) +#define STA_RCC_APB1HLPENR (0x58024400 + 0x114) +#define STO_RCC_APB1HLPENR (0x114) +#define STT_RCC_APB1HLPENR STIO_32_RW +#define STN_RCC_APB1HLPENR RCC_APB1HLPENR +#define BP_RCC_APB1HLPENR_FDCANEN 8 +#define BM_RCC_APB1HLPENR_FDCANEN 0x100 +#define BF_RCC_APB1HLPENR_FDCANEN(v) (((v) & 0x1) << 8) +#define BFM_RCC_APB1HLPENR_FDCANEN(v) BM_RCC_APB1HLPENR_FDCANEN +#define BF_RCC_APB1HLPENR_FDCANEN_V(e) BF_RCC_APB1HLPENR_FDCANEN(BV_RCC_APB1HLPENR_FDCANEN__##e) +#define BFM_RCC_APB1HLPENR_FDCANEN_V(v) BM_RCC_APB1HLPENR_FDCANEN +#define BP_RCC_APB1HLPENR_MDIOSEN 5 +#define BM_RCC_APB1HLPENR_MDIOSEN 0x20 +#define BF_RCC_APB1HLPENR_MDIOSEN(v) (((v) & 0x1) << 5) +#define BFM_RCC_APB1HLPENR_MDIOSEN(v) BM_RCC_APB1HLPENR_MDIOSEN +#define BF_RCC_APB1HLPENR_MDIOSEN_V(e) BF_RCC_APB1HLPENR_MDIOSEN(BV_RCC_APB1HLPENR_MDIOSEN__##e) +#define BFM_RCC_APB1HLPENR_MDIOSEN_V(v) BM_RCC_APB1HLPENR_MDIOSEN +#define BP_RCC_APB1HLPENR_OPAMPEN 4 +#define BM_RCC_APB1HLPENR_OPAMPEN 0x10 +#define BF_RCC_APB1HLPENR_OPAMPEN(v) (((v) & 0x1) << 4) +#define BFM_RCC_APB1HLPENR_OPAMPEN(v) BM_RCC_APB1HLPENR_OPAMPEN +#define BF_RCC_APB1HLPENR_OPAMPEN_V(e) BF_RCC_APB1HLPENR_OPAMPEN(BV_RCC_APB1HLPENR_OPAMPEN__##e) +#define BFM_RCC_APB1HLPENR_OPAMPEN_V(v) BM_RCC_APB1HLPENR_OPAMPEN +#define BP_RCC_APB1HLPENR_SWPEN 2 +#define BM_RCC_APB1HLPENR_SWPEN 0x4 +#define BF_RCC_APB1HLPENR_SWPEN(v) (((v) & 0x1) << 2) +#define BFM_RCC_APB1HLPENR_SWPEN(v) BM_RCC_APB1HLPENR_SWPEN +#define BF_RCC_APB1HLPENR_SWPEN_V(e) BF_RCC_APB1HLPENR_SWPEN(BV_RCC_APB1HLPENR_SWPEN__##e) +#define BFM_RCC_APB1HLPENR_SWPEN_V(v) BM_RCC_APB1HLPENR_SWPEN +#define BP_RCC_APB1HLPENR_CRSEN 1 +#define BM_RCC_APB1HLPENR_CRSEN 0x2 +#define BF_RCC_APB1HLPENR_CRSEN(v) (((v) & 0x1) << 1) +#define BFM_RCC_APB1HLPENR_CRSEN(v) BM_RCC_APB1HLPENR_CRSEN +#define BF_RCC_APB1HLPENR_CRSEN_V(e) BF_RCC_APB1HLPENR_CRSEN(BV_RCC_APB1HLPENR_CRSEN__##e) +#define BFM_RCC_APB1HLPENR_CRSEN_V(v) BM_RCC_APB1HLPENR_CRSEN + +#define REG_RCC_APB2ENR st_reg(RCC_APB2ENR) +#define STA_RCC_APB2ENR (0x58024400 + 0xf0) +#define STO_RCC_APB2ENR (0xf0) +#define STT_RCC_APB2ENR STIO_32_RW +#define STN_RCC_APB2ENR RCC_APB2ENR +#define BP_RCC_APB2ENR_HRTIMEN 29 +#define BM_RCC_APB2ENR_HRTIMEN 0x20000000 +#define BF_RCC_APB2ENR_HRTIMEN(v) (((v) & 0x1) << 29) +#define BFM_RCC_APB2ENR_HRTIMEN(v) BM_RCC_APB2ENR_HRTIMEN +#define BF_RCC_APB2ENR_HRTIMEN_V(e) BF_RCC_APB2ENR_HRTIMEN(BV_RCC_APB2ENR_HRTIMEN__##e) +#define BFM_RCC_APB2ENR_HRTIMEN_V(v) BM_RCC_APB2ENR_HRTIMEN +#define BP_RCC_APB2ENR_DFSDM1EN 28 +#define BM_RCC_APB2ENR_DFSDM1EN 0x10000000 +#define BF_RCC_APB2ENR_DFSDM1EN(v) (((v) & 0x1) << 28) +#define BFM_RCC_APB2ENR_DFSDM1EN(v) BM_RCC_APB2ENR_DFSDM1EN +#define BF_RCC_APB2ENR_DFSDM1EN_V(e) BF_RCC_APB2ENR_DFSDM1EN(BV_RCC_APB2ENR_DFSDM1EN__##e) +#define BFM_RCC_APB2ENR_DFSDM1EN_V(v) BM_RCC_APB2ENR_DFSDM1EN +#define BP_RCC_APB2ENR_SAI3EN 24 +#define BM_RCC_APB2ENR_SAI3EN 0x1000000 +#define BF_RCC_APB2ENR_SAI3EN(v) (((v) & 0x1) << 24) +#define BFM_RCC_APB2ENR_SAI3EN(v) BM_RCC_APB2ENR_SAI3EN +#define BF_RCC_APB2ENR_SAI3EN_V(e) BF_RCC_APB2ENR_SAI3EN(BV_RCC_APB2ENR_SAI3EN__##e) +#define BFM_RCC_APB2ENR_SAI3EN_V(v) BM_RCC_APB2ENR_SAI3EN +#define BP_RCC_APB2ENR_SAI2EN 23 +#define BM_RCC_APB2ENR_SAI2EN 0x800000 +#define BF_RCC_APB2ENR_SAI2EN(v) (((v) & 0x1) << 23) +#define BFM_RCC_APB2ENR_SAI2EN(v) BM_RCC_APB2ENR_SAI2EN +#define BF_RCC_APB2ENR_SAI2EN_V(e) BF_RCC_APB2ENR_SAI2EN(BV_RCC_APB2ENR_SAI2EN__##e) +#define BFM_RCC_APB2ENR_SAI2EN_V(v) BM_RCC_APB2ENR_SAI2EN +#define BP_RCC_APB2ENR_SAI1EN 22 +#define BM_RCC_APB2ENR_SAI1EN 0x400000 +#define BF_RCC_APB2ENR_SAI1EN(v) (((v) & 0x1) << 22) +#define BFM_RCC_APB2ENR_SAI1EN(v) BM_RCC_APB2ENR_SAI1EN +#define BF_RCC_APB2ENR_SAI1EN_V(e) BF_RCC_APB2ENR_SAI1EN(BV_RCC_APB2ENR_SAI1EN__##e) +#define BFM_RCC_APB2ENR_SAI1EN_V(v) BM_RCC_APB2ENR_SAI1EN +#define BP_RCC_APB2ENR_SPI5EN 20 +#define BM_RCC_APB2ENR_SPI5EN 0x100000 +#define BF_RCC_APB2ENR_SPI5EN(v) (((v) & 0x1) << 20) +#define BFM_RCC_APB2ENR_SPI5EN(v) BM_RCC_APB2ENR_SPI5EN +#define BF_RCC_APB2ENR_SPI5EN_V(e) BF_RCC_APB2ENR_SPI5EN(BV_RCC_APB2ENR_SPI5EN__##e) +#define BFM_RCC_APB2ENR_SPI5EN_V(v) BM_RCC_APB2ENR_SPI5EN +#define BP_RCC_APB2ENR_TIM17EN 18 +#define BM_RCC_APB2ENR_TIM17EN 0x40000 +#define BF_RCC_APB2ENR_TIM17EN(v) (((v) & 0x1) << 18) +#define BFM_RCC_APB2ENR_TIM17EN(v) BM_RCC_APB2ENR_TIM17EN +#define BF_RCC_APB2ENR_TIM17EN_V(e) BF_RCC_APB2ENR_TIM17EN(BV_RCC_APB2ENR_TIM17EN__##e) +#define BFM_RCC_APB2ENR_TIM17EN_V(v) BM_RCC_APB2ENR_TIM17EN +#define BP_RCC_APB2ENR_TIM16EN 17 +#define BM_RCC_APB2ENR_TIM16EN 0x20000 +#define BF_RCC_APB2ENR_TIM16EN(v) (((v) & 0x1) << 17) +#define BFM_RCC_APB2ENR_TIM16EN(v) BM_RCC_APB2ENR_TIM16EN +#define BF_RCC_APB2ENR_TIM16EN_V(e) BF_RCC_APB2ENR_TIM16EN(BV_RCC_APB2ENR_TIM16EN__##e) +#define BFM_RCC_APB2ENR_TIM16EN_V(v) BM_RCC_APB2ENR_TIM16EN +#define BP_RCC_APB2ENR_TIM15EN 16 +#define BM_RCC_APB2ENR_TIM15EN 0x10000 +#define BF_RCC_APB2ENR_TIM15EN(v) (((v) & 0x1) << 16) +#define BFM_RCC_APB2ENR_TIM15EN(v) BM_RCC_APB2ENR_TIM15EN +#define BF_RCC_APB2ENR_TIM15EN_V(e) BF_RCC_APB2ENR_TIM15EN(BV_RCC_APB2ENR_TIM15EN__##e) +#define BFM_RCC_APB2ENR_TIM15EN_V(v) BM_RCC_APB2ENR_TIM15EN +#define BP_RCC_APB2ENR_SPI4EN 13 +#define BM_RCC_APB2ENR_SPI4EN 0x2000 +#define BF_RCC_APB2ENR_SPI4EN(v) (((v) & 0x1) << 13) +#define BFM_RCC_APB2ENR_SPI4EN(v) BM_RCC_APB2ENR_SPI4EN +#define BF_RCC_APB2ENR_SPI4EN_V(e) BF_RCC_APB2ENR_SPI4EN(BV_RCC_APB2ENR_SPI4EN__##e) +#define BFM_RCC_APB2ENR_SPI4EN_V(v) BM_RCC_APB2ENR_SPI4EN +#define BP_RCC_APB2ENR_SPI1EN 12 +#define BM_RCC_APB2ENR_SPI1EN 0x1000 +#define BF_RCC_APB2ENR_SPI1EN(v) (((v) & 0x1) << 12) +#define BFM_RCC_APB2ENR_SPI1EN(v) BM_RCC_APB2ENR_SPI1EN +#define BF_RCC_APB2ENR_SPI1EN_V(e) BF_RCC_APB2ENR_SPI1EN(BV_RCC_APB2ENR_SPI1EN__##e) +#define BFM_RCC_APB2ENR_SPI1EN_V(v) BM_RCC_APB2ENR_SPI1EN +#define BP_RCC_APB2ENR_USART6EN 5 +#define BM_RCC_APB2ENR_USART6EN 0x20 +#define BF_RCC_APB2ENR_USART6EN(v) (((v) & 0x1) << 5) +#define BFM_RCC_APB2ENR_USART6EN(v) BM_RCC_APB2ENR_USART6EN +#define BF_RCC_APB2ENR_USART6EN_V(e) BF_RCC_APB2ENR_USART6EN(BV_RCC_APB2ENR_USART6EN__##e) +#define BFM_RCC_APB2ENR_USART6EN_V(v) BM_RCC_APB2ENR_USART6EN +#define BP_RCC_APB2ENR_USART1EN 4 +#define BM_RCC_APB2ENR_USART1EN 0x10 +#define BF_RCC_APB2ENR_USART1EN(v) (((v) & 0x1) << 4) +#define BFM_RCC_APB2ENR_USART1EN(v) BM_RCC_APB2ENR_USART1EN +#define BF_RCC_APB2ENR_USART1EN_V(e) BF_RCC_APB2ENR_USART1EN(BV_RCC_APB2ENR_USART1EN__##e) +#define BFM_RCC_APB2ENR_USART1EN_V(v) BM_RCC_APB2ENR_USART1EN +#define BP_RCC_APB2ENR_TIM8EN 1 +#define BM_RCC_APB2ENR_TIM8EN 0x2 +#define BF_RCC_APB2ENR_TIM8EN(v) (((v) & 0x1) << 1) +#define BFM_RCC_APB2ENR_TIM8EN(v) BM_RCC_APB2ENR_TIM8EN +#define BF_RCC_APB2ENR_TIM8EN_V(e) BF_RCC_APB2ENR_TIM8EN(BV_RCC_APB2ENR_TIM8EN__##e) +#define BFM_RCC_APB2ENR_TIM8EN_V(v) BM_RCC_APB2ENR_TIM8EN +#define BP_RCC_APB2ENR_TIM1EN 0 +#define BM_RCC_APB2ENR_TIM1EN 0x1 +#define BF_RCC_APB2ENR_TIM1EN(v) (((v) & 0x1) << 0) +#define BFM_RCC_APB2ENR_TIM1EN(v) BM_RCC_APB2ENR_TIM1EN +#define BF_RCC_APB2ENR_TIM1EN_V(e) BF_RCC_APB2ENR_TIM1EN(BV_RCC_APB2ENR_TIM1EN__##e) +#define BFM_RCC_APB2ENR_TIM1EN_V(v) BM_RCC_APB2ENR_TIM1EN + +#define REG_RCC_APB2LPENR st_reg(RCC_APB2LPENR) +#define STA_RCC_APB2LPENR (0x58024400 + 0x118) +#define STO_RCC_APB2LPENR (0x118) +#define STT_RCC_APB2LPENR STIO_32_RW +#define STN_RCC_APB2LPENR RCC_APB2LPENR +#define BP_RCC_APB2LPENR_HRTIMEN 29 +#define BM_RCC_APB2LPENR_HRTIMEN 0x20000000 +#define BF_RCC_APB2LPENR_HRTIMEN(v) (((v) & 0x1) << 29) +#define BFM_RCC_APB2LPENR_HRTIMEN(v) BM_RCC_APB2LPENR_HRTIMEN +#define BF_RCC_APB2LPENR_HRTIMEN_V(e) BF_RCC_APB2LPENR_HRTIMEN(BV_RCC_APB2LPENR_HRTIMEN__##e) +#define BFM_RCC_APB2LPENR_HRTIMEN_V(v) BM_RCC_APB2LPENR_HRTIMEN +#define BP_RCC_APB2LPENR_DFSDM1EN 28 +#define BM_RCC_APB2LPENR_DFSDM1EN 0x10000000 +#define BF_RCC_APB2LPENR_DFSDM1EN(v) (((v) & 0x1) << 28) +#define BFM_RCC_APB2LPENR_DFSDM1EN(v) BM_RCC_APB2LPENR_DFSDM1EN +#define BF_RCC_APB2LPENR_DFSDM1EN_V(e) BF_RCC_APB2LPENR_DFSDM1EN(BV_RCC_APB2LPENR_DFSDM1EN__##e) +#define BFM_RCC_APB2LPENR_DFSDM1EN_V(v) BM_RCC_APB2LPENR_DFSDM1EN +#define BP_RCC_APB2LPENR_SAI3EN 24 +#define BM_RCC_APB2LPENR_SAI3EN 0x1000000 +#define BF_RCC_APB2LPENR_SAI3EN(v) (((v) & 0x1) << 24) +#define BFM_RCC_APB2LPENR_SAI3EN(v) BM_RCC_APB2LPENR_SAI3EN +#define BF_RCC_APB2LPENR_SAI3EN_V(e) BF_RCC_APB2LPENR_SAI3EN(BV_RCC_APB2LPENR_SAI3EN__##e) +#define BFM_RCC_APB2LPENR_SAI3EN_V(v) BM_RCC_APB2LPENR_SAI3EN +#define BP_RCC_APB2LPENR_SAI2EN 23 +#define BM_RCC_APB2LPENR_SAI2EN 0x800000 +#define BF_RCC_APB2LPENR_SAI2EN(v) (((v) & 0x1) << 23) +#define BFM_RCC_APB2LPENR_SAI2EN(v) BM_RCC_APB2LPENR_SAI2EN +#define BF_RCC_APB2LPENR_SAI2EN_V(e) BF_RCC_APB2LPENR_SAI2EN(BV_RCC_APB2LPENR_SAI2EN__##e) +#define BFM_RCC_APB2LPENR_SAI2EN_V(v) BM_RCC_APB2LPENR_SAI2EN +#define BP_RCC_APB2LPENR_SAI1EN 22 +#define BM_RCC_APB2LPENR_SAI1EN 0x400000 +#define BF_RCC_APB2LPENR_SAI1EN(v) (((v) & 0x1) << 22) +#define BFM_RCC_APB2LPENR_SAI1EN(v) BM_RCC_APB2LPENR_SAI1EN +#define BF_RCC_APB2LPENR_SAI1EN_V(e) BF_RCC_APB2LPENR_SAI1EN(BV_RCC_APB2LPENR_SAI1EN__##e) +#define BFM_RCC_APB2LPENR_SAI1EN_V(v) BM_RCC_APB2LPENR_SAI1EN +#define BP_RCC_APB2LPENR_SPI5EN 20 +#define BM_RCC_APB2LPENR_SPI5EN 0x100000 +#define BF_RCC_APB2LPENR_SPI5EN(v) (((v) & 0x1) << 20) +#define BFM_RCC_APB2LPENR_SPI5EN(v) BM_RCC_APB2LPENR_SPI5EN +#define BF_RCC_APB2LPENR_SPI5EN_V(e) BF_RCC_APB2LPENR_SPI5EN(BV_RCC_APB2LPENR_SPI5EN__##e) +#define BFM_RCC_APB2LPENR_SPI5EN_V(v) BM_RCC_APB2LPENR_SPI5EN +#define BP_RCC_APB2LPENR_TIM17EN 18 +#define BM_RCC_APB2LPENR_TIM17EN 0x40000 +#define BF_RCC_APB2LPENR_TIM17EN(v) (((v) & 0x1) << 18) +#define BFM_RCC_APB2LPENR_TIM17EN(v) BM_RCC_APB2LPENR_TIM17EN +#define BF_RCC_APB2LPENR_TIM17EN_V(e) BF_RCC_APB2LPENR_TIM17EN(BV_RCC_APB2LPENR_TIM17EN__##e) +#define BFM_RCC_APB2LPENR_TIM17EN_V(v) BM_RCC_APB2LPENR_TIM17EN +#define BP_RCC_APB2LPENR_TIM16EN 17 +#define BM_RCC_APB2LPENR_TIM16EN 0x20000 +#define BF_RCC_APB2LPENR_TIM16EN(v) (((v) & 0x1) << 17) +#define BFM_RCC_APB2LPENR_TIM16EN(v) BM_RCC_APB2LPENR_TIM16EN +#define BF_RCC_APB2LPENR_TIM16EN_V(e) BF_RCC_APB2LPENR_TIM16EN(BV_RCC_APB2LPENR_TIM16EN__##e) +#define BFM_RCC_APB2LPENR_TIM16EN_V(v) BM_RCC_APB2LPENR_TIM16EN +#define BP_RCC_APB2LPENR_TIM15EN 16 +#define BM_RCC_APB2LPENR_TIM15EN 0x10000 +#define BF_RCC_APB2LPENR_TIM15EN(v) (((v) & 0x1) << 16) +#define BFM_RCC_APB2LPENR_TIM15EN(v) BM_RCC_APB2LPENR_TIM15EN +#define BF_RCC_APB2LPENR_TIM15EN_V(e) BF_RCC_APB2LPENR_TIM15EN(BV_RCC_APB2LPENR_TIM15EN__##e) +#define BFM_RCC_APB2LPENR_TIM15EN_V(v) BM_RCC_APB2LPENR_TIM15EN +#define BP_RCC_APB2LPENR_SPI4EN 13 +#define BM_RCC_APB2LPENR_SPI4EN 0x2000 +#define BF_RCC_APB2LPENR_SPI4EN(v) (((v) & 0x1) << 13) +#define BFM_RCC_APB2LPENR_SPI4EN(v) BM_RCC_APB2LPENR_SPI4EN +#define BF_RCC_APB2LPENR_SPI4EN_V(e) BF_RCC_APB2LPENR_SPI4EN(BV_RCC_APB2LPENR_SPI4EN__##e) +#define BFM_RCC_APB2LPENR_SPI4EN_V(v) BM_RCC_APB2LPENR_SPI4EN +#define BP_RCC_APB2LPENR_SPI1EN 12 +#define BM_RCC_APB2LPENR_SPI1EN 0x1000 +#define BF_RCC_APB2LPENR_SPI1EN(v) (((v) & 0x1) << 12) +#define BFM_RCC_APB2LPENR_SPI1EN(v) BM_RCC_APB2LPENR_SPI1EN +#define BF_RCC_APB2LPENR_SPI1EN_V(e) BF_RCC_APB2LPENR_SPI1EN(BV_RCC_APB2LPENR_SPI1EN__##e) +#define BFM_RCC_APB2LPENR_SPI1EN_V(v) BM_RCC_APB2LPENR_SPI1EN +#define BP_RCC_APB2LPENR_USART6EN 5 +#define BM_RCC_APB2LPENR_USART6EN 0x20 +#define BF_RCC_APB2LPENR_USART6EN(v) (((v) & 0x1) << 5) +#define BFM_RCC_APB2LPENR_USART6EN(v) BM_RCC_APB2LPENR_USART6EN +#define BF_RCC_APB2LPENR_USART6EN_V(e) BF_RCC_APB2LPENR_USART6EN(BV_RCC_APB2LPENR_USART6EN__##e) +#define BFM_RCC_APB2LPENR_USART6EN_V(v) BM_RCC_APB2LPENR_USART6EN +#define BP_RCC_APB2LPENR_USART1EN 4 +#define BM_RCC_APB2LPENR_USART1EN 0x10 +#define BF_RCC_APB2LPENR_USART1EN(v) (((v) & 0x1) << 4) +#define BFM_RCC_APB2LPENR_USART1EN(v) BM_RCC_APB2LPENR_USART1EN +#define BF_RCC_APB2LPENR_USART1EN_V(e) BF_RCC_APB2LPENR_USART1EN(BV_RCC_APB2LPENR_USART1EN__##e) +#define BFM_RCC_APB2LPENR_USART1EN_V(v) BM_RCC_APB2LPENR_USART1EN +#define BP_RCC_APB2LPENR_TIM8EN 1 +#define BM_RCC_APB2LPENR_TIM8EN 0x2 +#define BF_RCC_APB2LPENR_TIM8EN(v) (((v) & 0x1) << 1) +#define BFM_RCC_APB2LPENR_TIM8EN(v) BM_RCC_APB2LPENR_TIM8EN +#define BF_RCC_APB2LPENR_TIM8EN_V(e) BF_RCC_APB2LPENR_TIM8EN(BV_RCC_APB2LPENR_TIM8EN__##e) +#define BFM_RCC_APB2LPENR_TIM8EN_V(v) BM_RCC_APB2LPENR_TIM8EN +#define BP_RCC_APB2LPENR_TIM1EN 0 +#define BM_RCC_APB2LPENR_TIM1EN 0x1 +#define BF_RCC_APB2LPENR_TIM1EN(v) (((v) & 0x1) << 0) +#define BFM_RCC_APB2LPENR_TIM1EN(v) BM_RCC_APB2LPENR_TIM1EN +#define BF_RCC_APB2LPENR_TIM1EN_V(e) BF_RCC_APB2LPENR_TIM1EN(BV_RCC_APB2LPENR_TIM1EN__##e) +#define BFM_RCC_APB2LPENR_TIM1EN_V(v) BM_RCC_APB2LPENR_TIM1EN + +#define REG_RCC_APB4ENR st_reg(RCC_APB4ENR) +#define STA_RCC_APB4ENR (0x58024400 + 0xf4) +#define STO_RCC_APB4ENR (0xf4) +#define STT_RCC_APB4ENR STIO_32_RW +#define STN_RCC_APB4ENR RCC_APB4ENR +#define BP_RCC_APB4ENR_SAI4EN 21 +#define BM_RCC_APB4ENR_SAI4EN 0x200000 +#define BF_RCC_APB4ENR_SAI4EN(v) (((v) & 0x1) << 21) +#define BFM_RCC_APB4ENR_SAI4EN(v) BM_RCC_APB4ENR_SAI4EN +#define BF_RCC_APB4ENR_SAI4EN_V(e) BF_RCC_APB4ENR_SAI4EN(BV_RCC_APB4ENR_SAI4EN__##e) +#define BFM_RCC_APB4ENR_SAI4EN_V(v) BM_RCC_APB4ENR_SAI4EN +#define BP_RCC_APB4ENR_RTCAPBEN 16 +#define BM_RCC_APB4ENR_RTCAPBEN 0x10000 +#define BF_RCC_APB4ENR_RTCAPBEN(v) (((v) & 0x1) << 16) +#define BFM_RCC_APB4ENR_RTCAPBEN(v) BM_RCC_APB4ENR_RTCAPBEN +#define BF_RCC_APB4ENR_RTCAPBEN_V(e) BF_RCC_APB4ENR_RTCAPBEN(BV_RCC_APB4ENR_RTCAPBEN__##e) +#define BFM_RCC_APB4ENR_RTCAPBEN_V(v) BM_RCC_APB4ENR_RTCAPBEN +#define BP_RCC_APB4ENR_VREFEN 15 +#define BM_RCC_APB4ENR_VREFEN 0x8000 +#define BF_RCC_APB4ENR_VREFEN(v) (((v) & 0x1) << 15) +#define BFM_RCC_APB4ENR_VREFEN(v) BM_RCC_APB4ENR_VREFEN +#define BF_RCC_APB4ENR_VREFEN_V(e) BF_RCC_APB4ENR_VREFEN(BV_RCC_APB4ENR_VREFEN__##e) +#define BFM_RCC_APB4ENR_VREFEN_V(v) BM_RCC_APB4ENR_VREFEN +#define BP_RCC_APB4ENR_COMP12EN 14 +#define BM_RCC_APB4ENR_COMP12EN 0x4000 +#define BF_RCC_APB4ENR_COMP12EN(v) (((v) & 0x1) << 14) +#define BFM_RCC_APB4ENR_COMP12EN(v) BM_RCC_APB4ENR_COMP12EN +#define BF_RCC_APB4ENR_COMP12EN_V(e) BF_RCC_APB4ENR_COMP12EN(BV_RCC_APB4ENR_COMP12EN__##e) +#define BFM_RCC_APB4ENR_COMP12EN_V(v) BM_RCC_APB4ENR_COMP12EN +#define BP_RCC_APB4ENR_LPTIM5EN 12 +#define BM_RCC_APB4ENR_LPTIM5EN 0x1000 +#define BF_RCC_APB4ENR_LPTIM5EN(v) (((v) & 0x1) << 12) +#define BFM_RCC_APB4ENR_LPTIM5EN(v) BM_RCC_APB4ENR_LPTIM5EN +#define BF_RCC_APB4ENR_LPTIM5EN_V(e) BF_RCC_APB4ENR_LPTIM5EN(BV_RCC_APB4ENR_LPTIM5EN__##e) +#define BFM_RCC_APB4ENR_LPTIM5EN_V(v) BM_RCC_APB4ENR_LPTIM5EN +#define BP_RCC_APB4ENR_LPTIM4EN 11 +#define BM_RCC_APB4ENR_LPTIM4EN 0x800 +#define BF_RCC_APB4ENR_LPTIM4EN(v) (((v) & 0x1) << 11) +#define BFM_RCC_APB4ENR_LPTIM4EN(v) BM_RCC_APB4ENR_LPTIM4EN +#define BF_RCC_APB4ENR_LPTIM4EN_V(e) BF_RCC_APB4ENR_LPTIM4EN(BV_RCC_APB4ENR_LPTIM4EN__##e) +#define BFM_RCC_APB4ENR_LPTIM4EN_V(v) BM_RCC_APB4ENR_LPTIM4EN +#define BP_RCC_APB4ENR_LPTIM3EN 10 +#define BM_RCC_APB4ENR_LPTIM3EN 0x400 +#define BF_RCC_APB4ENR_LPTIM3EN(v) (((v) & 0x1) << 10) +#define BFM_RCC_APB4ENR_LPTIM3EN(v) BM_RCC_APB4ENR_LPTIM3EN +#define BF_RCC_APB4ENR_LPTIM3EN_V(e) BF_RCC_APB4ENR_LPTIM3EN(BV_RCC_APB4ENR_LPTIM3EN__##e) +#define BFM_RCC_APB4ENR_LPTIM3EN_V(v) BM_RCC_APB4ENR_LPTIM3EN +#define BP_RCC_APB4ENR_LPTIM2EN 9 +#define BM_RCC_APB4ENR_LPTIM2EN 0x200 +#define BF_RCC_APB4ENR_LPTIM2EN(v) (((v) & 0x1) << 9) +#define BFM_RCC_APB4ENR_LPTIM2EN(v) BM_RCC_APB4ENR_LPTIM2EN +#define BF_RCC_APB4ENR_LPTIM2EN_V(e) BF_RCC_APB4ENR_LPTIM2EN(BV_RCC_APB4ENR_LPTIM2EN__##e) +#define BFM_RCC_APB4ENR_LPTIM2EN_V(v) BM_RCC_APB4ENR_LPTIM2EN +#define BP_RCC_APB4ENR_I2C4EN 7 +#define BM_RCC_APB4ENR_I2C4EN 0x80 +#define BF_RCC_APB4ENR_I2C4EN(v) (((v) & 0x1) << 7) +#define BFM_RCC_APB4ENR_I2C4EN(v) BM_RCC_APB4ENR_I2C4EN +#define BF_RCC_APB4ENR_I2C4EN_V(e) BF_RCC_APB4ENR_I2C4EN(BV_RCC_APB4ENR_I2C4EN__##e) +#define BFM_RCC_APB4ENR_I2C4EN_V(v) BM_RCC_APB4ENR_I2C4EN +#define BP_RCC_APB4ENR_SPI6EN 5 +#define BM_RCC_APB4ENR_SPI6EN 0x20 +#define BF_RCC_APB4ENR_SPI6EN(v) (((v) & 0x1) << 5) +#define BFM_RCC_APB4ENR_SPI6EN(v) BM_RCC_APB4ENR_SPI6EN +#define BF_RCC_APB4ENR_SPI6EN_V(e) BF_RCC_APB4ENR_SPI6EN(BV_RCC_APB4ENR_SPI6EN__##e) +#define BFM_RCC_APB4ENR_SPI6EN_V(v) BM_RCC_APB4ENR_SPI6EN +#define BP_RCC_APB4ENR_LPUART1EN 3 +#define BM_RCC_APB4ENR_LPUART1EN 0x8 +#define BF_RCC_APB4ENR_LPUART1EN(v) (((v) & 0x1) << 3) +#define BFM_RCC_APB4ENR_LPUART1EN(v) BM_RCC_APB4ENR_LPUART1EN +#define BF_RCC_APB4ENR_LPUART1EN_V(e) BF_RCC_APB4ENR_LPUART1EN(BV_RCC_APB4ENR_LPUART1EN__##e) +#define BFM_RCC_APB4ENR_LPUART1EN_V(v) BM_RCC_APB4ENR_LPUART1EN +#define BP_RCC_APB4ENR_SYSCFGEN 1 +#define BM_RCC_APB4ENR_SYSCFGEN 0x2 +#define BF_RCC_APB4ENR_SYSCFGEN(v) (((v) & 0x1) << 1) +#define BFM_RCC_APB4ENR_SYSCFGEN(v) BM_RCC_APB4ENR_SYSCFGEN +#define BF_RCC_APB4ENR_SYSCFGEN_V(e) BF_RCC_APB4ENR_SYSCFGEN(BV_RCC_APB4ENR_SYSCFGEN__##e) +#define BFM_RCC_APB4ENR_SYSCFGEN_V(v) BM_RCC_APB4ENR_SYSCFGEN + +#define REG_RCC_APB4LPENR st_reg(RCC_APB4LPENR) +#define STA_RCC_APB4LPENR (0x58024400 + 0x11c) +#define STO_RCC_APB4LPENR (0x11c) +#define STT_RCC_APB4LPENR STIO_32_RW +#define STN_RCC_APB4LPENR RCC_APB4LPENR +#define BP_RCC_APB4LPENR_SAI4EN 21 +#define BM_RCC_APB4LPENR_SAI4EN 0x200000 +#define BF_RCC_APB4LPENR_SAI4EN(v) (((v) & 0x1) << 21) +#define BFM_RCC_APB4LPENR_SAI4EN(v) BM_RCC_APB4LPENR_SAI4EN +#define BF_RCC_APB4LPENR_SAI4EN_V(e) BF_RCC_APB4LPENR_SAI4EN(BV_RCC_APB4LPENR_SAI4EN__##e) +#define BFM_RCC_APB4LPENR_SAI4EN_V(v) BM_RCC_APB4LPENR_SAI4EN +#define BP_RCC_APB4LPENR_RTCAPBEN 16 +#define BM_RCC_APB4LPENR_RTCAPBEN 0x10000 +#define BF_RCC_APB4LPENR_RTCAPBEN(v) (((v) & 0x1) << 16) +#define BFM_RCC_APB4LPENR_RTCAPBEN(v) BM_RCC_APB4LPENR_RTCAPBEN +#define BF_RCC_APB4LPENR_RTCAPBEN_V(e) BF_RCC_APB4LPENR_RTCAPBEN(BV_RCC_APB4LPENR_RTCAPBEN__##e) +#define BFM_RCC_APB4LPENR_RTCAPBEN_V(v) BM_RCC_APB4LPENR_RTCAPBEN +#define BP_RCC_APB4LPENR_VREFEN 15 +#define BM_RCC_APB4LPENR_VREFEN 0x8000 +#define BF_RCC_APB4LPENR_VREFEN(v) (((v) & 0x1) << 15) +#define BFM_RCC_APB4LPENR_VREFEN(v) BM_RCC_APB4LPENR_VREFEN +#define BF_RCC_APB4LPENR_VREFEN_V(e) BF_RCC_APB4LPENR_VREFEN(BV_RCC_APB4LPENR_VREFEN__##e) +#define BFM_RCC_APB4LPENR_VREFEN_V(v) BM_RCC_APB4LPENR_VREFEN +#define BP_RCC_APB4LPENR_COMP12EN 14 +#define BM_RCC_APB4LPENR_COMP12EN 0x4000 +#define BF_RCC_APB4LPENR_COMP12EN(v) (((v) & 0x1) << 14) +#define BFM_RCC_APB4LPENR_COMP12EN(v) BM_RCC_APB4LPENR_COMP12EN +#define BF_RCC_APB4LPENR_COMP12EN_V(e) BF_RCC_APB4LPENR_COMP12EN(BV_RCC_APB4LPENR_COMP12EN__##e) +#define BFM_RCC_APB4LPENR_COMP12EN_V(v) BM_RCC_APB4LPENR_COMP12EN +#define BP_RCC_APB4LPENR_LPTIM5EN 12 +#define BM_RCC_APB4LPENR_LPTIM5EN 0x1000 +#define BF_RCC_APB4LPENR_LPTIM5EN(v) (((v) & 0x1) << 12) +#define BFM_RCC_APB4LPENR_LPTIM5EN(v) BM_RCC_APB4LPENR_LPTIM5EN +#define BF_RCC_APB4LPENR_LPTIM5EN_V(e) BF_RCC_APB4LPENR_LPTIM5EN(BV_RCC_APB4LPENR_LPTIM5EN__##e) +#define BFM_RCC_APB4LPENR_LPTIM5EN_V(v) BM_RCC_APB4LPENR_LPTIM5EN +#define BP_RCC_APB4LPENR_LPTIM4EN 11 +#define BM_RCC_APB4LPENR_LPTIM4EN 0x800 +#define BF_RCC_APB4LPENR_LPTIM4EN(v) (((v) & 0x1) << 11) +#define BFM_RCC_APB4LPENR_LPTIM4EN(v) BM_RCC_APB4LPENR_LPTIM4EN +#define BF_RCC_APB4LPENR_LPTIM4EN_V(e) BF_RCC_APB4LPENR_LPTIM4EN(BV_RCC_APB4LPENR_LPTIM4EN__##e) +#define BFM_RCC_APB4LPENR_LPTIM4EN_V(v) BM_RCC_APB4LPENR_LPTIM4EN +#define BP_RCC_APB4LPENR_LPTIM3EN 10 +#define BM_RCC_APB4LPENR_LPTIM3EN 0x400 +#define BF_RCC_APB4LPENR_LPTIM3EN(v) (((v) & 0x1) << 10) +#define BFM_RCC_APB4LPENR_LPTIM3EN(v) BM_RCC_APB4LPENR_LPTIM3EN +#define BF_RCC_APB4LPENR_LPTIM3EN_V(e) BF_RCC_APB4LPENR_LPTIM3EN(BV_RCC_APB4LPENR_LPTIM3EN__##e) +#define BFM_RCC_APB4LPENR_LPTIM3EN_V(v) BM_RCC_APB4LPENR_LPTIM3EN +#define BP_RCC_APB4LPENR_LPTIM2EN 9 +#define BM_RCC_APB4LPENR_LPTIM2EN 0x200 +#define BF_RCC_APB4LPENR_LPTIM2EN(v) (((v) & 0x1) << 9) +#define BFM_RCC_APB4LPENR_LPTIM2EN(v) BM_RCC_APB4LPENR_LPTIM2EN +#define BF_RCC_APB4LPENR_LPTIM2EN_V(e) BF_RCC_APB4LPENR_LPTIM2EN(BV_RCC_APB4LPENR_LPTIM2EN__##e) +#define BFM_RCC_APB4LPENR_LPTIM2EN_V(v) BM_RCC_APB4LPENR_LPTIM2EN +#define BP_RCC_APB4LPENR_I2C4EN 7 +#define BM_RCC_APB4LPENR_I2C4EN 0x80 +#define BF_RCC_APB4LPENR_I2C4EN(v) (((v) & 0x1) << 7) +#define BFM_RCC_APB4LPENR_I2C4EN(v) BM_RCC_APB4LPENR_I2C4EN +#define BF_RCC_APB4LPENR_I2C4EN_V(e) BF_RCC_APB4LPENR_I2C4EN(BV_RCC_APB4LPENR_I2C4EN__##e) +#define BFM_RCC_APB4LPENR_I2C4EN_V(v) BM_RCC_APB4LPENR_I2C4EN +#define BP_RCC_APB4LPENR_SPI6EN 5 +#define BM_RCC_APB4LPENR_SPI6EN 0x20 +#define BF_RCC_APB4LPENR_SPI6EN(v) (((v) & 0x1) << 5) +#define BFM_RCC_APB4LPENR_SPI6EN(v) BM_RCC_APB4LPENR_SPI6EN +#define BF_RCC_APB4LPENR_SPI6EN_V(e) BF_RCC_APB4LPENR_SPI6EN(BV_RCC_APB4LPENR_SPI6EN__##e) +#define BFM_RCC_APB4LPENR_SPI6EN_V(v) BM_RCC_APB4LPENR_SPI6EN +#define BP_RCC_APB4LPENR_LPUART1EN 3 +#define BM_RCC_APB4LPENR_LPUART1EN 0x8 +#define BF_RCC_APB4LPENR_LPUART1EN(v) (((v) & 0x1) << 3) +#define BFM_RCC_APB4LPENR_LPUART1EN(v) BM_RCC_APB4LPENR_LPUART1EN +#define BF_RCC_APB4LPENR_LPUART1EN_V(e) BF_RCC_APB4LPENR_LPUART1EN(BV_RCC_APB4LPENR_LPUART1EN__##e) +#define BFM_RCC_APB4LPENR_LPUART1EN_V(v) BM_RCC_APB4LPENR_LPUART1EN +#define BP_RCC_APB4LPENR_SYSCFGEN 1 +#define BM_RCC_APB4LPENR_SYSCFGEN 0x2 +#define BF_RCC_APB4LPENR_SYSCFGEN(v) (((v) & 0x1) << 1) +#define BFM_RCC_APB4LPENR_SYSCFGEN(v) BM_RCC_APB4LPENR_SYSCFGEN +#define BF_RCC_APB4LPENR_SYSCFGEN_V(e) BF_RCC_APB4LPENR_SYSCFGEN(BV_RCC_APB4LPENR_SYSCFGEN__##e) +#define BFM_RCC_APB4LPENR_SYSCFGEN_V(v) BM_RCC_APB4LPENR_SYSCFGEN + +#endif /* __HEADERGEN_RCC_H__*/ diff --git a/firmware/target/arm/stm32/stm32h7/rtc.h b/firmware/target/arm/stm32/stm32h7/rtc.h new file mode 100644 index 0000000000..a44aa5d27e --- /dev/null +++ b/firmware/target/arm/stm32/stm32h7/rtc.h @@ -0,0 +1,561 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * stm32h743 version: 1.0 + * stm32h743 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_RTC_H__ +#define __HEADERGEN_RTC_H__ + +#include "macro.h" + +#define STA_RTC (0x58004000) + +#define REG_RTC_TR st_reg(RTC_TR) +#define STA_RTC_TR (0x58004000 + 0x0) +#define STO_RTC_TR (0x0) +#define STT_RTC_TR STIO_32_RW +#define STN_RTC_TR RTC_TR +#define BP_RTC_TR_HT 20 +#define BM_RTC_TR_HT 0x300000 +#define BF_RTC_TR_HT(v) (((v) & 0x3) << 20) +#define BFM_RTC_TR_HT(v) BM_RTC_TR_HT +#define BF_RTC_TR_HT_V(e) BF_RTC_TR_HT(BV_RTC_TR_HT__##e) +#define BFM_RTC_TR_HT_V(v) BM_RTC_TR_HT +#define BP_RTC_TR_HU 16 +#define BM_RTC_TR_HU 0xf0000 +#define BF_RTC_TR_HU(v) (((v) & 0xf) << 16) +#define BFM_RTC_TR_HU(v) BM_RTC_TR_HU +#define BF_RTC_TR_HU_V(e) BF_RTC_TR_HU(BV_RTC_TR_HU__##e) +#define BFM_RTC_TR_HU_V(v) BM_RTC_TR_HU +#define BP_RTC_TR_MNT 12 +#define BM_RTC_TR_MNT 0x7000 +#define BF_RTC_TR_MNT(v) (((v) & 0x7) << 12) +#define BFM_RTC_TR_MNT(v) BM_RTC_TR_MNT +#define BF_RTC_TR_MNT_V(e) BF_RTC_TR_MNT(BV_RTC_TR_MNT__##e) +#define BFM_RTC_TR_MNT_V(v) BM_RTC_TR_MNT +#define BP_RTC_TR_MNU 8 +#define BM_RTC_TR_MNU 0xf00 +#define BF_RTC_TR_MNU(v) (((v) & 0xf) << 8) +#define BFM_RTC_TR_MNU(v) BM_RTC_TR_MNU +#define BF_RTC_TR_MNU_V(e) BF_RTC_TR_MNU(BV_RTC_TR_MNU__##e) +#define BFM_RTC_TR_MNU_V(v) BM_RTC_TR_MNU +#define BP_RTC_TR_ST 4 +#define BM_RTC_TR_ST 0x70 +#define BF_RTC_TR_ST(v) (((v) & 0x7) << 4) +#define BFM_RTC_TR_ST(v) BM_RTC_TR_ST +#define BF_RTC_TR_ST_V(e) BF_RTC_TR_ST(BV_RTC_TR_ST__##e) +#define BFM_RTC_TR_ST_V(v) BM_RTC_TR_ST +#define BP_RTC_TR_SU 0 +#define BM_RTC_TR_SU 0xf +#define BF_RTC_TR_SU(v) (((v) & 0xf) << 0) +#define BFM_RTC_TR_SU(v) BM_RTC_TR_SU +#define BF_RTC_TR_SU_V(e) BF_RTC_TR_SU(BV_RTC_TR_SU__##e) +#define BFM_RTC_TR_SU_V(v) BM_RTC_TR_SU +#define BP_RTC_TR_PM 22 +#define BM_RTC_TR_PM 0x400000 +#define BF_RTC_TR_PM(v) (((v) & 0x1) << 22) +#define BFM_RTC_TR_PM(v) BM_RTC_TR_PM +#define BF_RTC_TR_PM_V(e) BF_RTC_TR_PM(BV_RTC_TR_PM__##e) +#define BFM_RTC_TR_PM_V(v) BM_RTC_TR_PM + +#define REG_RTC_TSTR st_reg(RTC_TSTR) +#define STA_RTC_TSTR (0x58004000 + 0x30) +#define STO_RTC_TSTR (0x30) +#define STT_RTC_TSTR STIO_32_RW +#define STN_RTC_TSTR RTC_TSTR +#define BP_RTC_TSTR_HT 20 +#define BM_RTC_TSTR_HT 0x300000 +#define BF_RTC_TSTR_HT(v) (((v) & 0x3) << 20) +#define BFM_RTC_TSTR_HT(v) BM_RTC_TSTR_HT +#define BF_RTC_TSTR_HT_V(e) BF_RTC_TSTR_HT(BV_RTC_TSTR_HT__##e) +#define BFM_RTC_TSTR_HT_V(v) BM_RTC_TSTR_HT +#define BP_RTC_TSTR_HU 16 +#define BM_RTC_TSTR_HU 0xf0000 +#define BF_RTC_TSTR_HU(v) (((v) & 0xf) << 16) +#define BFM_RTC_TSTR_HU(v) BM_RTC_TSTR_HU +#define BF_RTC_TSTR_HU_V(e) BF_RTC_TSTR_HU(BV_RTC_TSTR_HU__##e) +#define BFM_RTC_TSTR_HU_V(v) BM_RTC_TSTR_HU +#define BP_RTC_TSTR_MNT 12 +#define BM_RTC_TSTR_MNT 0x7000 +#define BF_RTC_TSTR_MNT(v) (((v) & 0x7) << 12) +#define BFM_RTC_TSTR_MNT(v) BM_RTC_TSTR_MNT +#define BF_RTC_TSTR_MNT_V(e) BF_RTC_TSTR_MNT(BV_RTC_TSTR_MNT__##e) +#define BFM_RTC_TSTR_MNT_V(v) BM_RTC_TSTR_MNT +#define BP_RTC_TSTR_MNU 8 +#define BM_RTC_TSTR_MNU 0xf00 +#define BF_RTC_TSTR_MNU(v) (((v) & 0xf) << 8) +#define BFM_RTC_TSTR_MNU(v) BM_RTC_TSTR_MNU +#define BF_RTC_TSTR_MNU_V(e) BF_RTC_TSTR_MNU(BV_RTC_TSTR_MNU__##e) +#define BFM_RTC_TSTR_MNU_V(v) BM_RTC_TSTR_MNU +#define BP_RTC_TSTR_ST 4 +#define BM_RTC_TSTR_ST 0x70 +#define BF_RTC_TSTR_ST(v) (((v) & 0x7) << 4) +#define BFM_RTC_TSTR_ST(v) BM_RTC_TSTR_ST +#define BF_RTC_TSTR_ST_V(e) BF_RTC_TSTR_ST(BV_RTC_TSTR_ST__##e) +#define BFM_RTC_TSTR_ST_V(v) BM_RTC_TSTR_ST +#define BP_RTC_TSTR_SU 0 +#define BM_RTC_TSTR_SU 0xf +#define BF_RTC_TSTR_SU(v) (((v) & 0xf) << 0) +#define BFM_RTC_TSTR_SU(v) BM_RTC_TSTR_SU +#define BF_RTC_TSTR_SU_V(e) BF_RTC_TSTR_SU(BV_RTC_TSTR_SU__##e) +#define BFM_RTC_TSTR_SU_V(v) BM_RTC_TSTR_SU +#define BP_RTC_TSTR_PM 22 +#define BM_RTC_TSTR_PM 0x400000 +#define BF_RTC_TSTR_PM(v) (((v) & 0x1) << 22) +#define BFM_RTC_TSTR_PM(v) BM_RTC_TSTR_PM +#define BF_RTC_TSTR_PM_V(e) BF_RTC_TSTR_PM(BV_RTC_TSTR_PM__##e) +#define BFM_RTC_TSTR_PM_V(v) BM_RTC_TSTR_PM + +#define REG_RTC_DR st_reg(RTC_DR) +#define STA_RTC_DR (0x58004000 + 0x4) +#define STO_RTC_DR (0x4) +#define STT_RTC_DR STIO_32_RW +#define STN_RTC_DR RTC_DR +#define BP_RTC_DR_YT 20 +#define BM_RTC_DR_YT 0xf00000 +#define BF_RTC_DR_YT(v) (((v) & 0xf) << 20) +#define BFM_RTC_DR_YT(v) BM_RTC_DR_YT +#define BF_RTC_DR_YT_V(e) BF_RTC_DR_YT(BV_RTC_DR_YT__##e) +#define BFM_RTC_DR_YT_V(v) BM_RTC_DR_YT +#define BP_RTC_DR_YU 16 +#define BM_RTC_DR_YU 0xf0000 +#define BF_RTC_DR_YU(v) (((v) & 0xf) << 16) +#define BFM_RTC_DR_YU(v) BM_RTC_DR_YU +#define BF_RTC_DR_YU_V(e) BF_RTC_DR_YU(BV_RTC_DR_YU__##e) +#define BFM_RTC_DR_YU_V(v) BM_RTC_DR_YU +#define BP_RTC_DR_WDU 13 +#define BM_RTC_DR_WDU 0xe000 +#define BF_RTC_DR_WDU(v) (((v) & 0x7) << 13) +#define BFM_RTC_DR_WDU(v) BM_RTC_DR_WDU +#define BF_RTC_DR_WDU_V(e) BF_RTC_DR_WDU(BV_RTC_DR_WDU__##e) +#define BFM_RTC_DR_WDU_V(v) BM_RTC_DR_WDU +#define BP_RTC_DR_MU 8 +#define BM_RTC_DR_MU 0xf00 +#define BF_RTC_DR_MU(v) (((v) & 0xf) << 8) +#define BFM_RTC_DR_MU(v) BM_RTC_DR_MU +#define BF_RTC_DR_MU_V(e) BF_RTC_DR_MU(BV_RTC_DR_MU__##e) +#define BFM_RTC_DR_MU_V(v) BM_RTC_DR_MU +#define BP_RTC_DR_DT 4 +#define BM_RTC_DR_DT 0x30 +#define BF_RTC_DR_DT(v) (((v) & 0x3) << 4) +#define BFM_RTC_DR_DT(v) BM_RTC_DR_DT +#define BF_RTC_DR_DT_V(e) BF_RTC_DR_DT(BV_RTC_DR_DT__##e) +#define BFM_RTC_DR_DT_V(v) BM_RTC_DR_DT +#define BP_RTC_DR_DU 0 +#define BM_RTC_DR_DU 0xf +#define BF_RTC_DR_DU(v) (((v) & 0xf) << 0) +#define BFM_RTC_DR_DU(v) BM_RTC_DR_DU +#define BF_RTC_DR_DU_V(e) BF_RTC_DR_DU(BV_RTC_DR_DU__##e) +#define BFM_RTC_DR_DU_V(v) BM_RTC_DR_DU +#define BP_RTC_DR_MT 12 +#define BM_RTC_DR_MT 0x1000 +#define BF_RTC_DR_MT(v) (((v) & 0x1) << 12) +#define BFM_RTC_DR_MT(v) BM_RTC_DR_MT +#define BF_RTC_DR_MT_V(e) BF_RTC_DR_MT(BV_RTC_DR_MT__##e) +#define BFM_RTC_DR_MT_V(v) BM_RTC_DR_MT + +#define REG_RTC_DRTR st_reg(RTC_DRTR) +#define STA_RTC_DRTR (0x58004000 + 0x34) +#define STO_RTC_DRTR (0x34) +#define STT_RTC_DRTR STIO_32_RW +#define STN_RTC_DRTR RTC_DRTR +#define BP_RTC_DRTR_YT 20 +#define BM_RTC_DRTR_YT 0xf00000 +#define BF_RTC_DRTR_YT(v) (((v) & 0xf) << 20) +#define BFM_RTC_DRTR_YT(v) BM_RTC_DRTR_YT +#define BF_RTC_DRTR_YT_V(e) BF_RTC_DRTR_YT(BV_RTC_DRTR_YT__##e) +#define BFM_RTC_DRTR_YT_V(v) BM_RTC_DRTR_YT +#define BP_RTC_DRTR_YU 16 +#define BM_RTC_DRTR_YU 0xf0000 +#define BF_RTC_DRTR_YU(v) (((v) & 0xf) << 16) +#define BFM_RTC_DRTR_YU(v) BM_RTC_DRTR_YU +#define BF_RTC_DRTR_YU_V(e) BF_RTC_DRTR_YU(BV_RTC_DRTR_YU__##e) +#define BFM_RTC_DRTR_YU_V(v) BM_RTC_DRTR_YU +#define BP_RTC_DRTR_WDU 13 +#define BM_RTC_DRTR_WDU 0xe000 +#define BF_RTC_DRTR_WDU(v) (((v) & 0x7) << 13) +#define BFM_RTC_DRTR_WDU(v) BM_RTC_DRTR_WDU +#define BF_RTC_DRTR_WDU_V(e) BF_RTC_DRTR_WDU(BV_RTC_DRTR_WDU__##e) +#define BFM_RTC_DRTR_WDU_V(v) BM_RTC_DRTR_WDU +#define BP_RTC_DRTR_MU 8 +#define BM_RTC_DRTR_MU 0xf00 +#define BF_RTC_DRTR_MU(v) (((v) & 0xf) << 8) +#define BFM_RTC_DRTR_MU(v) BM_RTC_DRTR_MU +#define BF_RTC_DRTR_MU_V(e) BF_RTC_DRTR_MU(BV_RTC_DRTR_MU__##e) +#define BFM_RTC_DRTR_MU_V(v) BM_RTC_DRTR_MU +#define BP_RTC_DRTR_DT 4 +#define BM_RTC_DRTR_DT 0x30 +#define BF_RTC_DRTR_DT(v) (((v) & 0x3) << 4) +#define BFM_RTC_DRTR_DT(v) BM_RTC_DRTR_DT +#define BF_RTC_DRTR_DT_V(e) BF_RTC_DRTR_DT(BV_RTC_DRTR_DT__##e) +#define BFM_RTC_DRTR_DT_V(v) BM_RTC_DRTR_DT +#define BP_RTC_DRTR_DU 0 +#define BM_RTC_DRTR_DU 0xf +#define BF_RTC_DRTR_DU(v) (((v) & 0xf) << 0) +#define BFM_RTC_DRTR_DU(v) BM_RTC_DRTR_DU +#define BF_RTC_DRTR_DU_V(e) BF_RTC_DRTR_DU(BV_RTC_DRTR_DU__##e) +#define BFM_RTC_DRTR_DU_V(v) BM_RTC_DRTR_DU +#define BP_RTC_DRTR_MT 12 +#define BM_RTC_DRTR_MT 0x1000 +#define BF_RTC_DRTR_MT(v) (((v) & 0x1) << 12) +#define BFM_RTC_DRTR_MT(v) BM_RTC_DRTR_MT +#define BF_RTC_DRTR_MT_V(e) BF_RTC_DRTR_MT(BV_RTC_DRTR_MT__##e) +#define BFM_RTC_DRTR_MT_V(v) BM_RTC_DRTR_MT + +#define REG_RTC_CR st_reg(RTC_CR) +#define STA_RTC_CR (0x58004000 + 0x8) +#define STO_RTC_CR (0x8) +#define STT_RTC_CR STIO_32_RW +#define STN_RTC_CR RTC_CR +#define BP_RTC_CR_OSEL 21 +#define BM_RTC_CR_OSEL 0x600000 +#define BV_RTC_CR_OSEL__DISABLED 0x0 +#define BV_RTC_CR_OSEL__ALARM_A 0x1 +#define BV_RTC_CR_OSEL__ALARM_B 0x2 +#define BV_RTC_CR_OSEL__WAKEUP 0x3 +#define BF_RTC_CR_OSEL(v) (((v) & 0x3) << 21) +#define BFM_RTC_CR_OSEL(v) BM_RTC_CR_OSEL +#define BF_RTC_CR_OSEL_V(e) BF_RTC_CR_OSEL(BV_RTC_CR_OSEL__##e) +#define BFM_RTC_CR_OSEL_V(v) BM_RTC_CR_OSEL +#define BP_RTC_CR_ITSE 24 +#define BM_RTC_CR_ITSE 0x1000000 +#define BF_RTC_CR_ITSE(v) (((v) & 0x1) << 24) +#define BFM_RTC_CR_ITSE(v) BM_RTC_CR_ITSE +#define BF_RTC_CR_ITSE_V(e) BF_RTC_CR_ITSE(BV_RTC_CR_ITSE__##e) +#define BFM_RTC_CR_ITSE_V(v) BM_RTC_CR_ITSE +#define BP_RTC_CR_COE 23 +#define BM_RTC_CR_COE 0x800000 +#define BF_RTC_CR_COE(v) (((v) & 0x1) << 23) +#define BFM_RTC_CR_COE(v) BM_RTC_CR_COE +#define BF_RTC_CR_COE_V(e) BF_RTC_CR_COE(BV_RTC_CR_COE__##e) +#define BFM_RTC_CR_COE_V(v) BM_RTC_CR_COE +#define BP_RTC_CR_POL 20 +#define BM_RTC_CR_POL 0x100000 +#define BF_RTC_CR_POL(v) (((v) & 0x1) << 20) +#define BFM_RTC_CR_POL(v) BM_RTC_CR_POL +#define BF_RTC_CR_POL_V(e) BF_RTC_CR_POL(BV_RTC_CR_POL__##e) +#define BFM_RTC_CR_POL_V(v) BM_RTC_CR_POL +#define BP_RTC_CR_COSEL 19 +#define BM_RTC_CR_COSEL 0x80000 +#define BF_RTC_CR_COSEL(v) (((v) & 0x1) << 19) +#define BFM_RTC_CR_COSEL(v) BM_RTC_CR_COSEL +#define BF_RTC_CR_COSEL_V(e) BF_RTC_CR_COSEL(BV_RTC_CR_COSEL__##e) +#define BFM_RTC_CR_COSEL_V(v) BM_RTC_CR_COSEL +#define BP_RTC_CR_BKP 18 +#define BM_RTC_CR_BKP 0x40000 +#define BF_RTC_CR_BKP(v) (((v) & 0x1) << 18) +#define BFM_RTC_CR_BKP(v) BM_RTC_CR_BKP +#define BF_RTC_CR_BKP_V(e) BF_RTC_CR_BKP(BV_RTC_CR_BKP__##e) +#define BFM_RTC_CR_BKP_V(v) BM_RTC_CR_BKP +#define BP_RTC_CR_SUB1H 17 +#define BM_RTC_CR_SUB1H 0x20000 +#define BF_RTC_CR_SUB1H(v) (((v) & 0x1) << 17) +#define BFM_RTC_CR_SUB1H(v) BM_RTC_CR_SUB1H +#define BF_RTC_CR_SUB1H_V(e) BF_RTC_CR_SUB1H(BV_RTC_CR_SUB1H__##e) +#define BFM_RTC_CR_SUB1H_V(v) BM_RTC_CR_SUB1H +#define BP_RTC_CR_ADD1H 16 +#define BM_RTC_CR_ADD1H 0x10000 +#define BF_RTC_CR_ADD1H(v) (((v) & 0x1) << 16) +#define BFM_RTC_CR_ADD1H(v) BM_RTC_CR_ADD1H +#define BF_RTC_CR_ADD1H_V(e) BF_RTC_CR_ADD1H(BV_RTC_CR_ADD1H__##e) +#define BFM_RTC_CR_ADD1H_V(v) BM_RTC_CR_ADD1H +#define BP_RTC_CR_TSIE 15 +#define BM_RTC_CR_TSIE 0x8000 +#define BF_RTC_CR_TSIE(v) (((v) & 0x1) << 15) +#define BFM_RTC_CR_TSIE(v) BM_RTC_CR_TSIE +#define BF_RTC_CR_TSIE_V(e) BF_RTC_CR_TSIE(BV_RTC_CR_TSIE__##e) +#define BFM_RTC_CR_TSIE_V(v) BM_RTC_CR_TSIE +#define BP_RTC_CR_WUTIE 14 +#define BM_RTC_CR_WUTIE 0x4000 +#define BF_RTC_CR_WUTIE(v) (((v) & 0x1) << 14) +#define BFM_RTC_CR_WUTIE(v) BM_RTC_CR_WUTIE +#define BF_RTC_CR_WUTIE_V(e) BF_RTC_CR_WUTIE(BV_RTC_CR_WUTIE__##e) +#define BFM_RTC_CR_WUTIE_V(v) BM_RTC_CR_WUTIE +#define BP_RTC_CR_ALRBIE 13 +#define BM_RTC_CR_ALRBIE 0x2000 +#define BF_RTC_CR_ALRBIE(v) (((v) & 0x1) << 13) +#define BFM_RTC_CR_ALRBIE(v) BM_RTC_CR_ALRBIE +#define BF_RTC_CR_ALRBIE_V(e) BF_RTC_CR_ALRBIE(BV_RTC_CR_ALRBIE__##e) +#define BFM_RTC_CR_ALRBIE_V(v) BM_RTC_CR_ALRBIE +#define BP_RTC_CR_ALRAIE 12 +#define BM_RTC_CR_ALRAIE 0x1000 +#define BF_RTC_CR_ALRAIE(v) (((v) & 0x1) << 12) +#define BFM_RTC_CR_ALRAIE(v) BM_RTC_CR_ALRAIE +#define BF_RTC_CR_ALRAIE_V(e) BF_RTC_CR_ALRAIE(BV_RTC_CR_ALRAIE__##e) +#define BFM_RTC_CR_ALRAIE_V(v) BM_RTC_CR_ALRAIE +#define BP_RTC_CR_TSE 11 +#define BM_RTC_CR_TSE 0x800 +#define BF_RTC_CR_TSE(v) (((v) & 0x1) << 11) +#define BFM_RTC_CR_TSE(v) BM_RTC_CR_TSE +#define BF_RTC_CR_TSE_V(e) BF_RTC_CR_TSE(BV_RTC_CR_TSE__##e) +#define BFM_RTC_CR_TSE_V(v) BM_RTC_CR_TSE +#define BP_RTC_CR_WUTE 10 +#define BM_RTC_CR_WUTE 0x400 +#define BF_RTC_CR_WUTE(v) (((v) & 0x1) << 10) +#define BFM_RTC_CR_WUTE(v) BM_RTC_CR_WUTE +#define BF_RTC_CR_WUTE_V(e) BF_RTC_CR_WUTE(BV_RTC_CR_WUTE__##e) +#define BFM_RTC_CR_WUTE_V(v) BM_RTC_CR_WUTE +#define BP_RTC_CR_ALRBE 9 +#define BM_RTC_CR_ALRBE 0x200 +#define BF_RTC_CR_ALRBE(v) (((v) & 0x1) << 9) +#define BFM_RTC_CR_ALRBE(v) BM_RTC_CR_ALRBE +#define BF_RTC_CR_ALRBE_V(e) BF_RTC_CR_ALRBE(BV_RTC_CR_ALRBE__##e) +#define BFM_RTC_CR_ALRBE_V(v) BM_RTC_CR_ALRBE +#define BP_RTC_CR_ALRAE 8 +#define BM_RTC_CR_ALRAE 0x100 +#define BF_RTC_CR_ALRAE(v) (((v) & 0x1) << 8) +#define BFM_RTC_CR_ALRAE(v) BM_RTC_CR_ALRAE +#define BF_RTC_CR_ALRAE_V(e) BF_RTC_CR_ALRAE(BV_RTC_CR_ALRAE__##e) +#define BFM_RTC_CR_ALRAE_V(v) BM_RTC_CR_ALRAE +#define BP_RTC_CR_FMT 6 +#define BM_RTC_CR_FMT 0x40 +#define BF_RTC_CR_FMT(v) (((v) & 0x1) << 6) +#define BFM_RTC_CR_FMT(v) BM_RTC_CR_FMT +#define BF_RTC_CR_FMT_V(e) BF_RTC_CR_FMT(BV_RTC_CR_FMT__##e) +#define BFM_RTC_CR_FMT_V(v) BM_RTC_CR_FMT +#define BP_RTC_CR_BYPSHAD 5 +#define BM_RTC_CR_BYPSHAD 0x20 +#define BF_RTC_CR_BYPSHAD(v) (((v) & 0x1) << 5) +#define BFM_RTC_CR_BYPSHAD(v) BM_RTC_CR_BYPSHAD +#define BF_RTC_CR_BYPSHAD_V(e) BF_RTC_CR_BYPSHAD(BV_RTC_CR_BYPSHAD__##e) +#define BFM_RTC_CR_BYPSHAD_V(v) BM_RTC_CR_BYPSHAD +#define BP_RTC_CR_REFCKON 4 +#define BM_RTC_CR_REFCKON 0x10 +#define BF_RTC_CR_REFCKON(v) (((v) & 0x1) << 4) +#define BFM_RTC_CR_REFCKON(v) BM_RTC_CR_REFCKON +#define BF_RTC_CR_REFCKON_V(e) BF_RTC_CR_REFCKON(BV_RTC_CR_REFCKON__##e) +#define BFM_RTC_CR_REFCKON_V(v) BM_RTC_CR_REFCKON +#define BP_RTC_CR_TSEDGE 3 +#define BM_RTC_CR_TSEDGE 0x8 +#define BF_RTC_CR_TSEDGE(v) (((v) & 0x1) << 3) +#define BFM_RTC_CR_TSEDGE(v) BM_RTC_CR_TSEDGE +#define BF_RTC_CR_TSEDGE_V(e) BF_RTC_CR_TSEDGE(BV_RTC_CR_TSEDGE__##e) +#define BFM_RTC_CR_TSEDGE_V(v) BM_RTC_CR_TSEDGE +#define BP_RTC_CR_WUCKSEL 0 +#define BM_RTC_CR_WUCKSEL 0x7 +#define BV_RTC_CR_WUCKSEL__RTC_16 0x0 +#define BV_RTC_CR_WUCKSEL__RTC_8 0x1 +#define BV_RTC_CR_WUCKSEL__RTC_4 0x2 +#define BV_RTC_CR_WUCKSEL__RTC_2 0x3 +#define BV_RTC_CR_WUCKSEL__CK_SPRE 0x4 +#define BV_RTC_CR_WUCKSEL__CK_SPRE_ADDWUT 0x6 +#define BF_RTC_CR_WUCKSEL(v) (((v) & 0x7) << 0) +#define BFM_RTC_CR_WUCKSEL(v) BM_RTC_CR_WUCKSEL +#define BF_RTC_CR_WUCKSEL_V(e) BF_RTC_CR_WUCKSEL(BV_RTC_CR_WUCKSEL__##e) +#define BFM_RTC_CR_WUCKSEL_V(v) BM_RTC_CR_WUCKSEL + +#define REG_RTC_ISR st_reg(RTC_ISR) +#define STA_RTC_ISR (0x58004000 + 0xc) +#define STO_RTC_ISR (0xc) +#define STT_RTC_ISR STIO_32_RW +#define STN_RTC_ISR RTC_ISR +#define BP_RTC_ISR_ITSF 17 +#define BM_RTC_ISR_ITSF 0x20000 +#define BF_RTC_ISR_ITSF(v) (((v) & 0x1) << 17) +#define BFM_RTC_ISR_ITSF(v) BM_RTC_ISR_ITSF +#define BF_RTC_ISR_ITSF_V(e) BF_RTC_ISR_ITSF(BV_RTC_ISR_ITSF__##e) +#define BFM_RTC_ISR_ITSF_V(v) BM_RTC_ISR_ITSF +#define BP_RTC_ISR_RECALPF 16 +#define BM_RTC_ISR_RECALPF 0x10000 +#define BF_RTC_ISR_RECALPF(v) (((v) & 0x1) << 16) +#define BFM_RTC_ISR_RECALPF(v) BM_RTC_ISR_RECALPF +#define BF_RTC_ISR_RECALPF_V(e) BF_RTC_ISR_RECALPF(BV_RTC_ISR_RECALPF__##e) +#define BFM_RTC_ISR_RECALPF_V(v) BM_RTC_ISR_RECALPF +#define BP_RTC_ISR_TAMP3F 15 +#define BM_RTC_ISR_TAMP3F 0x8000 +#define BF_RTC_ISR_TAMP3F(v) (((v) & 0x1) << 15) +#define BFM_RTC_ISR_TAMP3F(v) BM_RTC_ISR_TAMP3F +#define BF_RTC_ISR_TAMP3F_V(e) BF_RTC_ISR_TAMP3F(BV_RTC_ISR_TAMP3F__##e) +#define BFM_RTC_ISR_TAMP3F_V(v) BM_RTC_ISR_TAMP3F +#define BP_RTC_ISR_TAMP2F 14 +#define BM_RTC_ISR_TAMP2F 0x4000 +#define BF_RTC_ISR_TAMP2F(v) (((v) & 0x1) << 14) +#define BFM_RTC_ISR_TAMP2F(v) BM_RTC_ISR_TAMP2F +#define BF_RTC_ISR_TAMP2F_V(e) BF_RTC_ISR_TAMP2F(BV_RTC_ISR_TAMP2F__##e) +#define BFM_RTC_ISR_TAMP2F_V(v) BM_RTC_ISR_TAMP2F +#define BP_RTC_ISR_TAMP1F 13 +#define BM_RTC_ISR_TAMP1F 0x2000 +#define BF_RTC_ISR_TAMP1F(v) (((v) & 0x1) << 13) +#define BFM_RTC_ISR_TAMP1F(v) BM_RTC_ISR_TAMP1F +#define BF_RTC_ISR_TAMP1F_V(e) BF_RTC_ISR_TAMP1F(BV_RTC_ISR_TAMP1F__##e) +#define BFM_RTC_ISR_TAMP1F_V(v) BM_RTC_ISR_TAMP1F +#define BP_RTC_ISR_TSOVF 12 +#define BM_RTC_ISR_TSOVF 0x1000 +#define BF_RTC_ISR_TSOVF(v) (((v) & 0x1) << 12) +#define BFM_RTC_ISR_TSOVF(v) BM_RTC_ISR_TSOVF +#define BF_RTC_ISR_TSOVF_V(e) BF_RTC_ISR_TSOVF(BV_RTC_ISR_TSOVF__##e) +#define BFM_RTC_ISR_TSOVF_V(v) BM_RTC_ISR_TSOVF +#define BP_RTC_ISR_TSF 11 +#define BM_RTC_ISR_TSF 0x800 +#define BF_RTC_ISR_TSF(v) (((v) & 0x1) << 11) +#define BFM_RTC_ISR_TSF(v) BM_RTC_ISR_TSF +#define BF_RTC_ISR_TSF_V(e) BF_RTC_ISR_TSF(BV_RTC_ISR_TSF__##e) +#define BFM_RTC_ISR_TSF_V(v) BM_RTC_ISR_TSF +#define BP_RTC_ISR_WUTF 10 +#define BM_RTC_ISR_WUTF 0x400 +#define BF_RTC_ISR_WUTF(v) (((v) & 0x1) << 10) +#define BFM_RTC_ISR_WUTF(v) BM_RTC_ISR_WUTF +#define BF_RTC_ISR_WUTF_V(e) BF_RTC_ISR_WUTF(BV_RTC_ISR_WUTF__##e) +#define BFM_RTC_ISR_WUTF_V(v) BM_RTC_ISR_WUTF +#define BP_RTC_ISR_ALRBF 9 +#define BM_RTC_ISR_ALRBF 0x200 +#define BF_RTC_ISR_ALRBF(v) (((v) & 0x1) << 9) +#define BFM_RTC_ISR_ALRBF(v) BM_RTC_ISR_ALRBF +#define BF_RTC_ISR_ALRBF_V(e) BF_RTC_ISR_ALRBF(BV_RTC_ISR_ALRBF__##e) +#define BFM_RTC_ISR_ALRBF_V(v) BM_RTC_ISR_ALRBF +#define BP_RTC_ISR_ALRAF 8 +#define BM_RTC_ISR_ALRAF 0x100 +#define BF_RTC_ISR_ALRAF(v) (((v) & 0x1) << 8) +#define BFM_RTC_ISR_ALRAF(v) BM_RTC_ISR_ALRAF +#define BF_RTC_ISR_ALRAF_V(e) BF_RTC_ISR_ALRAF(BV_RTC_ISR_ALRAF__##e) +#define BFM_RTC_ISR_ALRAF_V(v) BM_RTC_ISR_ALRAF +#define BP_RTC_ISR_INIT 7 +#define BM_RTC_ISR_INIT 0x80 +#define BF_RTC_ISR_INIT(v) (((v) & 0x1) << 7) +#define BFM_RTC_ISR_INIT(v) BM_RTC_ISR_INIT +#define BF_RTC_ISR_INIT_V(e) BF_RTC_ISR_INIT(BV_RTC_ISR_INIT__##e) +#define BFM_RTC_ISR_INIT_V(v) BM_RTC_ISR_INIT +#define BP_RTC_ISR_INITF 6 +#define BM_RTC_ISR_INITF 0x40 +#define BF_RTC_ISR_INITF(v) (((v) & 0x1) << 6) +#define BFM_RTC_ISR_INITF(v) BM_RTC_ISR_INITF +#define BF_RTC_ISR_INITF_V(e) BF_RTC_ISR_INITF(BV_RTC_ISR_INITF__##e) +#define BFM_RTC_ISR_INITF_V(v) BM_RTC_ISR_INITF +#define BP_RTC_ISR_RSF 5 +#define BM_RTC_ISR_RSF 0x20 +#define BF_RTC_ISR_RSF(v) (((v) & 0x1) << 5) +#define BFM_RTC_ISR_RSF(v) BM_RTC_ISR_RSF +#define BF_RTC_ISR_RSF_V(e) BF_RTC_ISR_RSF(BV_RTC_ISR_RSF__##e) +#define BFM_RTC_ISR_RSF_V(v) BM_RTC_ISR_RSF +#define BP_RTC_ISR_INITS 4 +#define BM_RTC_ISR_INITS 0x10 +#define BF_RTC_ISR_INITS(v) (((v) & 0x1) << 4) +#define BFM_RTC_ISR_INITS(v) BM_RTC_ISR_INITS +#define BF_RTC_ISR_INITS_V(e) BF_RTC_ISR_INITS(BV_RTC_ISR_INITS__##e) +#define BFM_RTC_ISR_INITS_V(v) BM_RTC_ISR_INITS +#define BP_RTC_ISR_SHPF 3 +#define BM_RTC_ISR_SHPF 0x8 +#define BF_RTC_ISR_SHPF(v) (((v) & 0x1) << 3) +#define BFM_RTC_ISR_SHPF(v) BM_RTC_ISR_SHPF +#define BF_RTC_ISR_SHPF_V(e) BF_RTC_ISR_SHPF(BV_RTC_ISR_SHPF__##e) +#define BFM_RTC_ISR_SHPF_V(v) BM_RTC_ISR_SHPF +#define BP_RTC_ISR_WUTWF 2 +#define BM_RTC_ISR_WUTWF 0x4 +#define BF_RTC_ISR_WUTWF(v) (((v) & 0x1) << 2) +#define BFM_RTC_ISR_WUTWF(v) BM_RTC_ISR_WUTWF +#define BF_RTC_ISR_WUTWF_V(e) BF_RTC_ISR_WUTWF(BV_RTC_ISR_WUTWF__##e) +#define BFM_RTC_ISR_WUTWF_V(v) BM_RTC_ISR_WUTWF +#define BP_RTC_ISR_ALRBWF 1 +#define BM_RTC_ISR_ALRBWF 0x2 +#define BF_RTC_ISR_ALRBWF(v) (((v) & 0x1) << 1) +#define BFM_RTC_ISR_ALRBWF(v) BM_RTC_ISR_ALRBWF +#define BF_RTC_ISR_ALRBWF_V(e) BF_RTC_ISR_ALRBWF(BV_RTC_ISR_ALRBWF__##e) +#define BFM_RTC_ISR_ALRBWF_V(v) BM_RTC_ISR_ALRBWF +#define BP_RTC_ISR_ALRAWF 0 +#define BM_RTC_ISR_ALRAWF 0x1 +#define BF_RTC_ISR_ALRAWF(v) (((v) & 0x1) << 0) +#define BFM_RTC_ISR_ALRAWF(v) BM_RTC_ISR_ALRAWF +#define BF_RTC_ISR_ALRAWF_V(e) BF_RTC_ISR_ALRAWF(BV_RTC_ISR_ALRAWF__##e) +#define BFM_RTC_ISR_ALRAWF_V(v) BM_RTC_ISR_ALRAWF + +#define REG_RTC_PRER st_reg(RTC_PRER) +#define STA_RTC_PRER (0x58004000 + 0x10) +#define STO_RTC_PRER (0x10) +#define STT_RTC_PRER STIO_32_RW +#define STN_RTC_PRER RTC_PRER +#define BP_RTC_PRER_PREDIV_A 16 +#define BM_RTC_PRER_PREDIV_A 0x7f0000 +#define BF_RTC_PRER_PREDIV_A(v) (((v) & 0x7f) << 16) +#define BFM_RTC_PRER_PREDIV_A(v) BM_RTC_PRER_PREDIV_A +#define BF_RTC_PRER_PREDIV_A_V(e) BF_RTC_PRER_PREDIV_A(BV_RTC_PRER_PREDIV_A__##e) +#define BFM_RTC_PRER_PREDIV_A_V(v) BM_RTC_PRER_PREDIV_A +#define BP_RTC_PRER_PREDIV_S 0 +#define BM_RTC_PRER_PREDIV_S 0x7fff +#define BF_RTC_PRER_PREDIV_S(v) (((v) & 0x7fff) << 0) +#define BFM_RTC_PRER_PREDIV_S(v) BM_RTC_PRER_PREDIV_S +#define BF_RTC_PRER_PREDIV_S_V(e) BF_RTC_PRER_PREDIV_S(BV_RTC_PRER_PREDIV_S__##e) +#define BFM_RTC_PRER_PREDIV_S_V(v) BM_RTC_PRER_PREDIV_S + +#define REG_RTC_WPR st_reg(RTC_WPR) +#define STA_RTC_WPR (0x58004000 + 0x24) +#define STO_RTC_WPR (0x24) +#define STT_RTC_WPR STIO_32_RW +#define STN_RTC_WPR RTC_WPR +#define BP_RTC_WPR_KEY 0 +#define BM_RTC_WPR_KEY 0xff +#define BV_RTC_WPR_KEY__KEY1 0xca +#define BV_RTC_WPR_KEY__KEY2 0x53 +#define BF_RTC_WPR_KEY(v) (((v) & 0xff) << 0) +#define BFM_RTC_WPR_KEY(v) BM_RTC_WPR_KEY +#define BF_RTC_WPR_KEY_V(e) BF_RTC_WPR_KEY(BV_RTC_WPR_KEY__##e) +#define BFM_RTC_WPR_KEY_V(v) BM_RTC_WPR_KEY + +#define REG_RTC_SSR st_reg(RTC_SSR) +#define STA_RTC_SSR (0x58004000 + 0x28) +#define STO_RTC_SSR (0x28) +#define STT_RTC_SSR STIO_32_RW +#define STN_RTC_SSR RTC_SSR +#define BP_RTC_SSR_SS 0 +#define BM_RTC_SSR_SS 0xffff +#define BF_RTC_SSR_SS(v) (((v) & 0xffff) << 0) +#define BFM_RTC_SSR_SS(v) BM_RTC_SSR_SS +#define BF_RTC_SSR_SS_V(e) BF_RTC_SSR_SS(BV_RTC_SSR_SS__##e) +#define BFM_RTC_SSR_SS_V(v) BM_RTC_SSR_SS + +#define REG_RTC_TSSSR st_reg(RTC_TSSSR) +#define STA_RTC_TSSSR (0x58004000 + 0x38) +#define STO_RTC_TSSSR (0x38) +#define STT_RTC_TSSSR STIO_32_RW +#define STN_RTC_TSSSR RTC_TSSSR +#define BP_RTC_TSSSR_SS 0 +#define BM_RTC_TSSSR_SS 0xffff +#define BF_RTC_TSSSR_SS(v) (((v) & 0xffff) << 0) +#define BFM_RTC_TSSSR_SS(v) BM_RTC_TSSSR_SS +#define BF_RTC_TSSSR_SS_V(e) BF_RTC_TSSSR_SS(BV_RTC_TSSSR_SS__##e) +#define BFM_RTC_TSSSR_SS_V(v) BM_RTC_TSSSR_SS + +#define REG_RTC_OR st_reg(RTC_OR) +#define STA_RTC_OR (0x58004000 + 0x4c) +#define STO_RTC_OR (0x4c) +#define STT_RTC_OR STIO_32_RW +#define STN_RTC_OR RTC_OR +#define BP_RTC_OR_RTC_OUT_RMP 1 +#define BM_RTC_OR_RTC_OUT_RMP 0x2 +#define BF_RTC_OR_RTC_OUT_RMP(v) (((v) & 0x1) << 1) +#define BFM_RTC_OR_RTC_OUT_RMP(v) BM_RTC_OR_RTC_OUT_RMP +#define BF_RTC_OR_RTC_OUT_RMP_V(e) BF_RTC_OR_RTC_OUT_RMP(BV_RTC_OR_RTC_OUT_RMP__##e) +#define BFM_RTC_OR_RTC_OUT_RMP_V(v) BM_RTC_OR_RTC_OUT_RMP +#define BP_RTC_OR_RTC_ALARM_TYPE 0 +#define BM_RTC_OR_RTC_ALARM_TYPE 0x1 +#define BV_RTC_OR_RTC_ALARM_TYPE__OPEN_DRAIN 0x0 +#define BV_RTC_OR_RTC_ALARM_TYPE__PUSH_PULL 0x1 +#define BF_RTC_OR_RTC_ALARM_TYPE(v) (((v) & 0x1) << 0) +#define BFM_RTC_OR_RTC_ALARM_TYPE(v) BM_RTC_OR_RTC_ALARM_TYPE +#define BF_RTC_OR_RTC_ALARM_TYPE_V(e) BF_RTC_OR_RTC_ALARM_TYPE(BV_RTC_OR_RTC_ALARM_TYPE__##e) +#define BFM_RTC_OR_RTC_ALARM_TYPE_V(v) BM_RTC_OR_RTC_ALARM_TYPE + +#define REG_RTC_BKPR(_n1) st_reg(RTC_BKPR(_n1)) +#define STA_RTC_BKPR(_n1) (0x58004000 + 0x50 + (_n1) * 0x4) +#define STO_RTC_BKPR(_n1) (0x50 + (_n1) * 0x4) +#define STT_RTC_BKPR(_n1) STIO_32_RW +#define STN_RTC_BKPR(_n1) RTC_BKPR + +#endif /* __HEADERGEN_RTC_H__*/ diff --git a/firmware/target/arm/stm32/stm32h7/spi.h b/firmware/target/arm/stm32/stm32h7/spi.h new file mode 100644 index 0000000000..97934ece0c --- /dev/null +++ b/firmware/target/arm/stm32/stm32h7/spi.h @@ -0,0 +1,662 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * stm32h743 version: 1.0 + * stm32h743 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_SPI_H__ +#define __HEADERGEN_SPI_H__ + +#include "macro.h" + +#define STA_SPI1 (0x40013000) + +#define STA_SPI2 (0x40003800) + +#define STA_SPI3 (0x40003c00) + +#define STA_SPI4 (0x40013400) + +#define STA_SPI5 (0x40015000) + +#define STA_SPI6 (0x58001400) + +#define REG_SPI_CR1 st_reg(SPI_CR1) +#define STO_SPI_CR1 (0x0) +#define STT_SPI_CR1 STIO_32_RW +#define STN_SPI_CR1 SPI_CR1 +#define BP_SPI_CR1_IO_LOCK 16 +#define BM_SPI_CR1_IO_LOCK 0x10000 +#define BF_SPI_CR1_IO_LOCK(v) (((v) & 0x1) << 16) +#define BFM_SPI_CR1_IO_LOCK(v) BM_SPI_CR1_IO_LOCK +#define BF_SPI_CR1_IO_LOCK_V(e) BF_SPI_CR1_IO_LOCK(BV_SPI_CR1_IO_LOCK__##e) +#define BFM_SPI_CR1_IO_LOCK_V(v) BM_SPI_CR1_IO_LOCK +#define BP_SPI_CR1_TCRCINI 15 +#define BM_SPI_CR1_TCRCINI 0x8000 +#define BF_SPI_CR1_TCRCINI(v) (((v) & 0x1) << 15) +#define BFM_SPI_CR1_TCRCINI(v) BM_SPI_CR1_TCRCINI +#define BF_SPI_CR1_TCRCINI_V(e) BF_SPI_CR1_TCRCINI(BV_SPI_CR1_TCRCINI__##e) +#define BFM_SPI_CR1_TCRCINI_V(v) BM_SPI_CR1_TCRCINI +#define BP_SPI_CR1_RCRCINI 14 +#define BM_SPI_CR1_RCRCINI 0x4000 +#define BF_SPI_CR1_RCRCINI(v) (((v) & 0x1) << 14) +#define BFM_SPI_CR1_RCRCINI(v) BM_SPI_CR1_RCRCINI +#define BF_SPI_CR1_RCRCINI_V(e) BF_SPI_CR1_RCRCINI(BV_SPI_CR1_RCRCINI__##e) +#define BFM_SPI_CR1_RCRCINI_V(v) BM_SPI_CR1_RCRCINI +#define BP_SPI_CR1_CRC33_17 13 +#define BM_SPI_CR1_CRC33_17 0x2000 +#define BF_SPI_CR1_CRC33_17(v) (((v) & 0x1) << 13) +#define BFM_SPI_CR1_CRC33_17(v) BM_SPI_CR1_CRC33_17 +#define BF_SPI_CR1_CRC33_17_V(e) BF_SPI_CR1_CRC33_17(BV_SPI_CR1_CRC33_17__##e) +#define BFM_SPI_CR1_CRC33_17_V(v) BM_SPI_CR1_CRC33_17 +#define BP_SPI_CR1_SSI 12 +#define BM_SPI_CR1_SSI 0x1000 +#define BF_SPI_CR1_SSI(v) (((v) & 0x1) << 12) +#define BFM_SPI_CR1_SSI(v) BM_SPI_CR1_SSI +#define BF_SPI_CR1_SSI_V(e) BF_SPI_CR1_SSI(BV_SPI_CR1_SSI__##e) +#define BFM_SPI_CR1_SSI_V(v) BM_SPI_CR1_SSI +#define BP_SPI_CR1_HDDIR 11 +#define BM_SPI_CR1_HDDIR 0x800 +#define BF_SPI_CR1_HDDIR(v) (((v) & 0x1) << 11) +#define BFM_SPI_CR1_HDDIR(v) BM_SPI_CR1_HDDIR +#define BF_SPI_CR1_HDDIR_V(e) BF_SPI_CR1_HDDIR(BV_SPI_CR1_HDDIR__##e) +#define BFM_SPI_CR1_HDDIR_V(v) BM_SPI_CR1_HDDIR +#define BP_SPI_CR1_CSUSP 10 +#define BM_SPI_CR1_CSUSP 0x400 +#define BF_SPI_CR1_CSUSP(v) (((v) & 0x1) << 10) +#define BFM_SPI_CR1_CSUSP(v) BM_SPI_CR1_CSUSP +#define BF_SPI_CR1_CSUSP_V(e) BF_SPI_CR1_CSUSP(BV_SPI_CR1_CSUSP__##e) +#define BFM_SPI_CR1_CSUSP_V(v) BM_SPI_CR1_CSUSP +#define BP_SPI_CR1_CSTART 9 +#define BM_SPI_CR1_CSTART 0x200 +#define BF_SPI_CR1_CSTART(v) (((v) & 0x1) << 9) +#define BFM_SPI_CR1_CSTART(v) BM_SPI_CR1_CSTART +#define BF_SPI_CR1_CSTART_V(e) BF_SPI_CR1_CSTART(BV_SPI_CR1_CSTART__##e) +#define BFM_SPI_CR1_CSTART_V(v) BM_SPI_CR1_CSTART +#define BP_SPI_CR1_MASRX 8 +#define BM_SPI_CR1_MASRX 0x100 +#define BF_SPI_CR1_MASRX(v) (((v) & 0x1) << 8) +#define BFM_SPI_CR1_MASRX(v) BM_SPI_CR1_MASRX +#define BF_SPI_CR1_MASRX_V(e) BF_SPI_CR1_MASRX(BV_SPI_CR1_MASRX__##e) +#define BFM_SPI_CR1_MASRX_V(v) BM_SPI_CR1_MASRX +#define BP_SPI_CR1_SPE 0 +#define BM_SPI_CR1_SPE 0x1 +#define BF_SPI_CR1_SPE(v) (((v) & 0x1) << 0) +#define BFM_SPI_CR1_SPE(v) BM_SPI_CR1_SPE +#define BF_SPI_CR1_SPE_V(e) BF_SPI_CR1_SPE(BV_SPI_CR1_SPE__##e) +#define BFM_SPI_CR1_SPE_V(v) BM_SPI_CR1_SPE + +#define REG_SPI_CR2 st_reg(SPI_CR2) +#define STO_SPI_CR2 (0x4) +#define STT_SPI_CR2 STIO_32_RW +#define STN_SPI_CR2 SPI_CR2 +#define BP_SPI_CR2_TSER 16 +#define BM_SPI_CR2_TSER 0xffff0000 +#define BF_SPI_CR2_TSER(v) (((v) & 0xffff) << 16) +#define BFM_SPI_CR2_TSER(v) BM_SPI_CR2_TSER +#define BF_SPI_CR2_TSER_V(e) BF_SPI_CR2_TSER(BV_SPI_CR2_TSER__##e) +#define BFM_SPI_CR2_TSER_V(v) BM_SPI_CR2_TSER +#define BP_SPI_CR2_TSIZE 0 +#define BM_SPI_CR2_TSIZE 0xffff +#define BF_SPI_CR2_TSIZE(v) (((v) & 0xffff) << 0) +#define BFM_SPI_CR2_TSIZE(v) BM_SPI_CR2_TSIZE +#define BF_SPI_CR2_TSIZE_V(e) BF_SPI_CR2_TSIZE(BV_SPI_CR2_TSIZE__##e) +#define BFM_SPI_CR2_TSIZE_V(v) BM_SPI_CR2_TSIZE + +#define REG_SPI_CFG1 st_reg(SPI_CFG1) +#define STO_SPI_CFG1 (0x8) +#define STT_SPI_CFG1 STIO_32_RW +#define STN_SPI_CFG1 SPI_CFG1 +#define BP_SPI_CFG1_MBR 28 +#define BM_SPI_CFG1_MBR 0x70000000 +#define BF_SPI_CFG1_MBR(v) (((v) & 0x7) << 28) +#define BFM_SPI_CFG1_MBR(v) BM_SPI_CFG1_MBR +#define BF_SPI_CFG1_MBR_V(e) BF_SPI_CFG1_MBR(BV_SPI_CFG1_MBR__##e) +#define BFM_SPI_CFG1_MBR_V(v) BM_SPI_CFG1_MBR +#define BP_SPI_CFG1_CRCSIZE 16 +#define BM_SPI_CFG1_CRCSIZE 0x1f0000 +#define BF_SPI_CFG1_CRCSIZE(v) (((v) & 0x1f) << 16) +#define BFM_SPI_CFG1_CRCSIZE(v) BM_SPI_CFG1_CRCSIZE +#define BF_SPI_CFG1_CRCSIZE_V(e) BF_SPI_CFG1_CRCSIZE(BV_SPI_CFG1_CRCSIZE__##e) +#define BFM_SPI_CFG1_CRCSIZE_V(v) BM_SPI_CFG1_CRCSIZE +#define BP_SPI_CFG1_UDRDET 11 +#define BM_SPI_CFG1_UDRDET 0x1800 +#define BF_SPI_CFG1_UDRDET(v) (((v) & 0x3) << 11) +#define BFM_SPI_CFG1_UDRDET(v) BM_SPI_CFG1_UDRDET +#define BF_SPI_CFG1_UDRDET_V(e) BF_SPI_CFG1_UDRDET(BV_SPI_CFG1_UDRDET__##e) +#define BFM_SPI_CFG1_UDRDET_V(v) BM_SPI_CFG1_UDRDET +#define BP_SPI_CFG1_UDRCFG 9 +#define BM_SPI_CFG1_UDRCFG 0x600 +#define BF_SPI_CFG1_UDRCFG(v) (((v) & 0x3) << 9) +#define BFM_SPI_CFG1_UDRCFG(v) BM_SPI_CFG1_UDRCFG +#define BF_SPI_CFG1_UDRCFG_V(e) BF_SPI_CFG1_UDRCFG(BV_SPI_CFG1_UDRCFG__##e) +#define BFM_SPI_CFG1_UDRCFG_V(v) BM_SPI_CFG1_UDRCFG +#define BP_SPI_CFG1_FTHLV 5 +#define BM_SPI_CFG1_FTHLV 0x1e0 +#define BF_SPI_CFG1_FTHLV(v) (((v) & 0xf) << 5) +#define BFM_SPI_CFG1_FTHLV(v) BM_SPI_CFG1_FTHLV +#define BF_SPI_CFG1_FTHLV_V(e) BF_SPI_CFG1_FTHLV(BV_SPI_CFG1_FTHLV__##e) +#define BFM_SPI_CFG1_FTHLV_V(v) BM_SPI_CFG1_FTHLV +#define BP_SPI_CFG1_DSIZE 0 +#define BM_SPI_CFG1_DSIZE 0x1f +#define BF_SPI_CFG1_DSIZE(v) (((v) & 0x1f) << 0) +#define BFM_SPI_CFG1_DSIZE(v) BM_SPI_CFG1_DSIZE +#define BF_SPI_CFG1_DSIZE_V(e) BF_SPI_CFG1_DSIZE(BV_SPI_CFG1_DSIZE__##e) +#define BFM_SPI_CFG1_DSIZE_V(v) BM_SPI_CFG1_DSIZE +#define BP_SPI_CFG1_CRCEN 22 +#define BM_SPI_CFG1_CRCEN 0x400000 +#define BF_SPI_CFG1_CRCEN(v) (((v) & 0x1) << 22) +#define BFM_SPI_CFG1_CRCEN(v) BM_SPI_CFG1_CRCEN +#define BF_SPI_CFG1_CRCEN_V(e) BF_SPI_CFG1_CRCEN(BV_SPI_CFG1_CRCEN__##e) +#define BFM_SPI_CFG1_CRCEN_V(v) BM_SPI_CFG1_CRCEN +#define BP_SPI_CFG1_TXDMAEN 15 +#define BM_SPI_CFG1_TXDMAEN 0x8000 +#define BF_SPI_CFG1_TXDMAEN(v) (((v) & 0x1) << 15) +#define BFM_SPI_CFG1_TXDMAEN(v) BM_SPI_CFG1_TXDMAEN +#define BF_SPI_CFG1_TXDMAEN_V(e) BF_SPI_CFG1_TXDMAEN(BV_SPI_CFG1_TXDMAEN__##e) +#define BFM_SPI_CFG1_TXDMAEN_V(v) BM_SPI_CFG1_TXDMAEN +#define BP_SPI_CFG1_RXDMAEN 14 +#define BM_SPI_CFG1_RXDMAEN 0x4000 +#define BF_SPI_CFG1_RXDMAEN(v) (((v) & 0x1) << 14) +#define BFM_SPI_CFG1_RXDMAEN(v) BM_SPI_CFG1_RXDMAEN +#define BF_SPI_CFG1_RXDMAEN_V(e) BF_SPI_CFG1_RXDMAEN(BV_SPI_CFG1_RXDMAEN__##e) +#define BFM_SPI_CFG1_RXDMAEN_V(v) BM_SPI_CFG1_RXDMAEN + +#define REG_SPI_CFG2 st_reg(SPI_CFG2) +#define STO_SPI_CFG2 (0xc) +#define STT_SPI_CFG2 STIO_32_RW +#define STN_SPI_CFG2 SPI_CFG2 +#define BP_SPI_CFG2_SP 19 +#define BM_SPI_CFG2_SP 0x380000 +#define BV_SPI_CFG2_SP__MOTOROLA 0x0 +#define BV_SPI_CFG2_SP__TI 0x1 +#define BF_SPI_CFG2_SP(v) (((v) & 0x7) << 19) +#define BFM_SPI_CFG2_SP(v) BM_SPI_CFG2_SP +#define BF_SPI_CFG2_SP_V(e) BF_SPI_CFG2_SP(BV_SPI_CFG2_SP__##e) +#define BFM_SPI_CFG2_SP_V(v) BM_SPI_CFG2_SP +#define BP_SPI_CFG2_COMM 17 +#define BM_SPI_CFG2_COMM 0x60000 +#define BV_SPI_CFG2_COMM__DUPLEX 0x0 +#define BV_SPI_CFG2_COMM__TXONLY 0x1 +#define BV_SPI_CFG2_COMM__RXONLY 0x2 +#define BV_SPI_CFG2_COMM__HALF_DUPLEX 0x3 +#define BF_SPI_CFG2_COMM(v) (((v) & 0x3) << 17) +#define BFM_SPI_CFG2_COMM(v) BM_SPI_CFG2_COMM +#define BF_SPI_CFG2_COMM_V(e) BF_SPI_CFG2_COMM(BV_SPI_CFG2_COMM__##e) +#define BFM_SPI_CFG2_COMM_V(v) BM_SPI_CFG2_COMM +#define BP_SPI_CFG2_MIDI 4 +#define BM_SPI_CFG2_MIDI 0xf0 +#define BF_SPI_CFG2_MIDI(v) (((v) & 0xf) << 4) +#define BFM_SPI_CFG2_MIDI(v) BM_SPI_CFG2_MIDI +#define BF_SPI_CFG2_MIDI_V(e) BF_SPI_CFG2_MIDI(BV_SPI_CFG2_MIDI__##e) +#define BFM_SPI_CFG2_MIDI_V(v) BM_SPI_CFG2_MIDI +#define BP_SPI_CFG2_MSSI 0 +#define BM_SPI_CFG2_MSSI 0xf +#define BF_SPI_CFG2_MSSI(v) (((v) & 0xf) << 0) +#define BFM_SPI_CFG2_MSSI(v) BM_SPI_CFG2_MSSI +#define BF_SPI_CFG2_MSSI_V(e) BF_SPI_CFG2_MSSI(BV_SPI_CFG2_MSSI__##e) +#define BFM_SPI_CFG2_MSSI_V(v) BM_SPI_CFG2_MSSI +#define BP_SPI_CFG2_AFCNTR 31 +#define BM_SPI_CFG2_AFCNTR 0x80000000 +#define BF_SPI_CFG2_AFCNTR(v) (((v) & 0x1) << 31) +#define BFM_SPI_CFG2_AFCNTR(v) BM_SPI_CFG2_AFCNTR +#define BF_SPI_CFG2_AFCNTR_V(e) BF_SPI_CFG2_AFCNTR(BV_SPI_CFG2_AFCNTR__##e) +#define BFM_SPI_CFG2_AFCNTR_V(v) BM_SPI_CFG2_AFCNTR +#define BP_SPI_CFG2_SSOM 30 +#define BM_SPI_CFG2_SSOM 0x40000000 +#define BF_SPI_CFG2_SSOM(v) (((v) & 0x1) << 30) +#define BFM_SPI_CFG2_SSOM(v) BM_SPI_CFG2_SSOM +#define BF_SPI_CFG2_SSOM_V(e) BF_SPI_CFG2_SSOM(BV_SPI_CFG2_SSOM__##e) +#define BFM_SPI_CFG2_SSOM_V(v) BM_SPI_CFG2_SSOM +#define BP_SPI_CFG2_SSOE 29 +#define BM_SPI_CFG2_SSOE 0x20000000 +#define BF_SPI_CFG2_SSOE(v) (((v) & 0x1) << 29) +#define BFM_SPI_CFG2_SSOE(v) BM_SPI_CFG2_SSOE +#define BF_SPI_CFG2_SSOE_V(e) BF_SPI_CFG2_SSOE(BV_SPI_CFG2_SSOE__##e) +#define BFM_SPI_CFG2_SSOE_V(v) BM_SPI_CFG2_SSOE +#define BP_SPI_CFG2_SSIOP 28 +#define BM_SPI_CFG2_SSIOP 0x10000000 +#define BF_SPI_CFG2_SSIOP(v) (((v) & 0x1) << 28) +#define BFM_SPI_CFG2_SSIOP(v) BM_SPI_CFG2_SSIOP +#define BF_SPI_CFG2_SSIOP_V(e) BF_SPI_CFG2_SSIOP(BV_SPI_CFG2_SSIOP__##e) +#define BFM_SPI_CFG2_SSIOP_V(v) BM_SPI_CFG2_SSIOP +#define BP_SPI_CFG2_SSM 26 +#define BM_SPI_CFG2_SSM 0x4000000 +#define BV_SPI_CFG2_SSM__SS_PAD 0x0 +#define BV_SPI_CFG2_SSM__SSI_BIT 0x1 +#define BF_SPI_CFG2_SSM(v) (((v) & 0x1) << 26) +#define BFM_SPI_CFG2_SSM(v) BM_SPI_CFG2_SSM +#define BF_SPI_CFG2_SSM_V(e) BF_SPI_CFG2_SSM(BV_SPI_CFG2_SSM__##e) +#define BFM_SPI_CFG2_SSM_V(v) BM_SPI_CFG2_SSM +#define BP_SPI_CFG2_CPOL 25 +#define BM_SPI_CFG2_CPOL 0x2000000 +#define BF_SPI_CFG2_CPOL(v) (((v) & 0x1) << 25) +#define BFM_SPI_CFG2_CPOL(v) BM_SPI_CFG2_CPOL +#define BF_SPI_CFG2_CPOL_V(e) BF_SPI_CFG2_CPOL(BV_SPI_CFG2_CPOL__##e) +#define BFM_SPI_CFG2_CPOL_V(v) BM_SPI_CFG2_CPOL +#define BP_SPI_CFG2_CPHA 24 +#define BM_SPI_CFG2_CPHA 0x1000000 +#define BF_SPI_CFG2_CPHA(v) (((v) & 0x1) << 24) +#define BFM_SPI_CFG2_CPHA(v) BM_SPI_CFG2_CPHA +#define BF_SPI_CFG2_CPHA_V(e) BF_SPI_CFG2_CPHA(BV_SPI_CFG2_CPHA__##e) +#define BFM_SPI_CFG2_CPHA_V(v) BM_SPI_CFG2_CPHA +#define BP_SPI_CFG2_LSBFIRST 23 +#define BM_SPI_CFG2_LSBFIRST 0x800000 +#define BF_SPI_CFG2_LSBFIRST(v) (((v) & 0x1) << 23) +#define BFM_SPI_CFG2_LSBFIRST(v) BM_SPI_CFG2_LSBFIRST +#define BF_SPI_CFG2_LSBFIRST_V(e) BF_SPI_CFG2_LSBFIRST(BV_SPI_CFG2_LSBFIRST__##e) +#define BFM_SPI_CFG2_LSBFIRST_V(v) BM_SPI_CFG2_LSBFIRST +#define BP_SPI_CFG2_MASTER 22 +#define BM_SPI_CFG2_MASTER 0x400000 +#define BF_SPI_CFG2_MASTER(v) (((v) & 0x1) << 22) +#define BFM_SPI_CFG2_MASTER(v) BM_SPI_CFG2_MASTER +#define BF_SPI_CFG2_MASTER_V(e) BF_SPI_CFG2_MASTER(BV_SPI_CFG2_MASTER__##e) +#define BFM_SPI_CFG2_MASTER_V(v) BM_SPI_CFG2_MASTER +#define BP_SPI_CFG2_IOSWP 15 +#define BM_SPI_CFG2_IOSWP 0x8000 +#define BF_SPI_CFG2_IOSWP(v) (((v) & 0x1) << 15) +#define BFM_SPI_CFG2_IOSWP(v) BM_SPI_CFG2_IOSWP +#define BF_SPI_CFG2_IOSWP_V(e) BF_SPI_CFG2_IOSWP(BV_SPI_CFG2_IOSWP__##e) +#define BFM_SPI_CFG2_IOSWP_V(v) BM_SPI_CFG2_IOSWP + +#define REG_SPI_IER st_reg(SPI_IER) +#define STO_SPI_IER (0x10) +#define STT_SPI_IER STIO_32_RW +#define STN_SPI_IER SPI_IER +#define BP_SPI_IER_TSERFIE 10 +#define BM_SPI_IER_TSERFIE 0x400 +#define BF_SPI_IER_TSERFIE(v) (((v) & 0x1) << 10) +#define BFM_SPI_IER_TSERFIE(v) BM_SPI_IER_TSERFIE +#define BF_SPI_IER_TSERFIE_V(e) BF_SPI_IER_TSERFIE(BV_SPI_IER_TSERFIE__##e) +#define BFM_SPI_IER_TSERFIE_V(v) BM_SPI_IER_TSERFIE +#define BP_SPI_IER_MODFIE 9 +#define BM_SPI_IER_MODFIE 0x200 +#define BF_SPI_IER_MODFIE(v) (((v) & 0x1) << 9) +#define BFM_SPI_IER_MODFIE(v) BM_SPI_IER_MODFIE +#define BF_SPI_IER_MODFIE_V(e) BF_SPI_IER_MODFIE(BV_SPI_IER_MODFIE__##e) +#define BFM_SPI_IER_MODFIE_V(v) BM_SPI_IER_MODFIE +#define BP_SPI_IER_TIFREIE 8 +#define BM_SPI_IER_TIFREIE 0x100 +#define BF_SPI_IER_TIFREIE(v) (((v) & 0x1) << 8) +#define BFM_SPI_IER_TIFREIE(v) BM_SPI_IER_TIFREIE +#define BF_SPI_IER_TIFREIE_V(e) BF_SPI_IER_TIFREIE(BV_SPI_IER_TIFREIE__##e) +#define BFM_SPI_IER_TIFREIE_V(v) BM_SPI_IER_TIFREIE +#define BP_SPI_IER_CRCEIE 7 +#define BM_SPI_IER_CRCEIE 0x80 +#define BF_SPI_IER_CRCEIE(v) (((v) & 0x1) << 7) +#define BFM_SPI_IER_CRCEIE(v) BM_SPI_IER_CRCEIE +#define BF_SPI_IER_CRCEIE_V(e) BF_SPI_IER_CRCEIE(BV_SPI_IER_CRCEIE__##e) +#define BFM_SPI_IER_CRCEIE_V(v) BM_SPI_IER_CRCEIE +#define BP_SPI_IER_OVRIE 6 +#define BM_SPI_IER_OVRIE 0x40 +#define BF_SPI_IER_OVRIE(v) (((v) & 0x1) << 6) +#define BFM_SPI_IER_OVRIE(v) BM_SPI_IER_OVRIE +#define BF_SPI_IER_OVRIE_V(e) BF_SPI_IER_OVRIE(BV_SPI_IER_OVRIE__##e) +#define BFM_SPI_IER_OVRIE_V(v) BM_SPI_IER_OVRIE +#define BP_SPI_IER_UDRIE 5 +#define BM_SPI_IER_UDRIE 0x20 +#define BF_SPI_IER_UDRIE(v) (((v) & 0x1) << 5) +#define BFM_SPI_IER_UDRIE(v) BM_SPI_IER_UDRIE +#define BF_SPI_IER_UDRIE_V(e) BF_SPI_IER_UDRIE(BV_SPI_IER_UDRIE__##e) +#define BFM_SPI_IER_UDRIE_V(v) BM_SPI_IER_UDRIE +#define BP_SPI_IER_TXTFIE 4 +#define BM_SPI_IER_TXTFIE 0x10 +#define BF_SPI_IER_TXTFIE(v) (((v) & 0x1) << 4) +#define BFM_SPI_IER_TXTFIE(v) BM_SPI_IER_TXTFIE +#define BF_SPI_IER_TXTFIE_V(e) BF_SPI_IER_TXTFIE(BV_SPI_IER_TXTFIE__##e) +#define BFM_SPI_IER_TXTFIE_V(v) BM_SPI_IER_TXTFIE +#define BP_SPI_IER_EOTIE 3 +#define BM_SPI_IER_EOTIE 0x8 +#define BF_SPI_IER_EOTIE(v) (((v) & 0x1) << 3) +#define BFM_SPI_IER_EOTIE(v) BM_SPI_IER_EOTIE +#define BF_SPI_IER_EOTIE_V(e) BF_SPI_IER_EOTIE(BV_SPI_IER_EOTIE__##e) +#define BFM_SPI_IER_EOTIE_V(v) BM_SPI_IER_EOTIE +#define BP_SPI_IER_DXPIE 2 +#define BM_SPI_IER_DXPIE 0x4 +#define BF_SPI_IER_DXPIE(v) (((v) & 0x1) << 2) +#define BFM_SPI_IER_DXPIE(v) BM_SPI_IER_DXPIE +#define BF_SPI_IER_DXPIE_V(e) BF_SPI_IER_DXPIE(BV_SPI_IER_DXPIE__##e) +#define BFM_SPI_IER_DXPIE_V(v) BM_SPI_IER_DXPIE +#define BP_SPI_IER_TXPIE 1 +#define BM_SPI_IER_TXPIE 0x2 +#define BF_SPI_IER_TXPIE(v) (((v) & 0x1) << 1) +#define BFM_SPI_IER_TXPIE(v) BM_SPI_IER_TXPIE +#define BF_SPI_IER_TXPIE_V(e) BF_SPI_IER_TXPIE(BV_SPI_IER_TXPIE__##e) +#define BFM_SPI_IER_TXPIE_V(v) BM_SPI_IER_TXPIE +#define BP_SPI_IER_RXPIE 0 +#define BM_SPI_IER_RXPIE 0x1 +#define BF_SPI_IER_RXPIE(v) (((v) & 0x1) << 0) +#define BFM_SPI_IER_RXPIE(v) BM_SPI_IER_RXPIE +#define BF_SPI_IER_RXPIE_V(e) BF_SPI_IER_RXPIE(BV_SPI_IER_RXPIE__##e) +#define BFM_SPI_IER_RXPIE_V(v) BM_SPI_IER_RXPIE + +#define REG_SPI_SR st_reg(SPI_SR) +#define STO_SPI_SR (0x14) +#define STT_SPI_SR STIO_32_RW +#define STN_SPI_SR SPI_SR +#define BP_SPI_SR_CTSIZE 16 +#define BM_SPI_SR_CTSIZE 0xffff0000 +#define BF_SPI_SR_CTSIZE(v) (((v) & 0xffff) << 16) +#define BFM_SPI_SR_CTSIZE(v) BM_SPI_SR_CTSIZE +#define BF_SPI_SR_CTSIZE_V(e) BF_SPI_SR_CTSIZE(BV_SPI_SR_CTSIZE__##e) +#define BFM_SPI_SR_CTSIZE_V(v) BM_SPI_SR_CTSIZE +#define BP_SPI_SR_RXPLVL 13 +#define BM_SPI_SR_RXPLVL 0x6000 +#define BF_SPI_SR_RXPLVL(v) (((v) & 0x3) << 13) +#define BFM_SPI_SR_RXPLVL(v) BM_SPI_SR_RXPLVL +#define BF_SPI_SR_RXPLVL_V(e) BF_SPI_SR_RXPLVL(BV_SPI_SR_RXPLVL__##e) +#define BFM_SPI_SR_RXPLVL_V(v) BM_SPI_SR_RXPLVL +#define BP_SPI_SR_RXWNE 15 +#define BM_SPI_SR_RXWNE 0x8000 +#define BF_SPI_SR_RXWNE(v) (((v) & 0x1) << 15) +#define BFM_SPI_SR_RXWNE(v) BM_SPI_SR_RXWNE +#define BF_SPI_SR_RXWNE_V(e) BF_SPI_SR_RXWNE(BV_SPI_SR_RXWNE__##e) +#define BFM_SPI_SR_RXWNE_V(v) BM_SPI_SR_RXWNE +#define BP_SPI_SR_TXC 12 +#define BM_SPI_SR_TXC 0x1000 +#define BF_SPI_SR_TXC(v) (((v) & 0x1) << 12) +#define BFM_SPI_SR_TXC(v) BM_SPI_SR_TXC +#define BF_SPI_SR_TXC_V(e) BF_SPI_SR_TXC(BV_SPI_SR_TXC__##e) +#define BFM_SPI_SR_TXC_V(v) BM_SPI_SR_TXC +#define BP_SPI_SR_SUSP 11 +#define BM_SPI_SR_SUSP 0x800 +#define BF_SPI_SR_SUSP(v) (((v) & 0x1) << 11) +#define BFM_SPI_SR_SUSP(v) BM_SPI_SR_SUSP +#define BF_SPI_SR_SUSP_V(e) BF_SPI_SR_SUSP(BV_SPI_SR_SUSP__##e) +#define BFM_SPI_SR_SUSP_V(v) BM_SPI_SR_SUSP +#define BP_SPI_SR_TSERF 10 +#define BM_SPI_SR_TSERF 0x400 +#define BF_SPI_SR_TSERF(v) (((v) & 0x1) << 10) +#define BFM_SPI_SR_TSERF(v) BM_SPI_SR_TSERF +#define BF_SPI_SR_TSERF_V(e) BF_SPI_SR_TSERF(BV_SPI_SR_TSERF__##e) +#define BFM_SPI_SR_TSERF_V(v) BM_SPI_SR_TSERF +#define BP_SPI_SR_MODF 9 +#define BM_SPI_SR_MODF 0x200 +#define BF_SPI_SR_MODF(v) (((v) & 0x1) << 9) +#define BFM_SPI_SR_MODF(v) BM_SPI_SR_MODF +#define BF_SPI_SR_MODF_V(e) BF_SPI_SR_MODF(BV_SPI_SR_MODF__##e) +#define BFM_SPI_SR_MODF_V(v) BM_SPI_SR_MODF +#define BP_SPI_SR_TIFRE 8 +#define BM_SPI_SR_TIFRE 0x100 +#define BF_SPI_SR_TIFRE(v) (((v) & 0x1) << 8) +#define BFM_SPI_SR_TIFRE(v) BM_SPI_SR_TIFRE +#define BF_SPI_SR_TIFRE_V(e) BF_SPI_SR_TIFRE(BV_SPI_SR_TIFRE__##e) +#define BFM_SPI_SR_TIFRE_V(v) BM_SPI_SR_TIFRE +#define BP_SPI_SR_CRCE 7 +#define BM_SPI_SR_CRCE 0x80 +#define BF_SPI_SR_CRCE(v) (((v) & 0x1) << 7) +#define BFM_SPI_SR_CRCE(v) BM_SPI_SR_CRCE +#define BF_SPI_SR_CRCE_V(e) BF_SPI_SR_CRCE(BV_SPI_SR_CRCE__##e) +#define BFM_SPI_SR_CRCE_V(v) BM_SPI_SR_CRCE +#define BP_SPI_SR_OVR 6 +#define BM_SPI_SR_OVR 0x40 +#define BF_SPI_SR_OVR(v) (((v) & 0x1) << 6) +#define BFM_SPI_SR_OVR(v) BM_SPI_SR_OVR +#define BF_SPI_SR_OVR_V(e) BF_SPI_SR_OVR(BV_SPI_SR_OVR__##e) +#define BFM_SPI_SR_OVR_V(v) BM_SPI_SR_OVR +#define BP_SPI_SR_UDR 5 +#define BM_SPI_SR_UDR 0x20 +#define BF_SPI_SR_UDR(v) (((v) & 0x1) << 5) +#define BFM_SPI_SR_UDR(v) BM_SPI_SR_UDR +#define BF_SPI_SR_UDR_V(e) BF_SPI_SR_UDR(BV_SPI_SR_UDR__##e) +#define BFM_SPI_SR_UDR_V(v) BM_SPI_SR_UDR +#define BP_SPI_SR_TXTF 4 +#define BM_SPI_SR_TXTF 0x10 +#define BF_SPI_SR_TXTF(v) (((v) & 0x1) << 4) +#define BFM_SPI_SR_TXTF(v) BM_SPI_SR_TXTF +#define BF_SPI_SR_TXTF_V(e) BF_SPI_SR_TXTF(BV_SPI_SR_TXTF__##e) +#define BFM_SPI_SR_TXTF_V(v) BM_SPI_SR_TXTF +#define BP_SPI_SR_EOT 3 +#define BM_SPI_SR_EOT 0x8 +#define BF_SPI_SR_EOT(v) (((v) & 0x1) << 3) +#define BFM_SPI_SR_EOT(v) BM_SPI_SR_EOT +#define BF_SPI_SR_EOT_V(e) BF_SPI_SR_EOT(BV_SPI_SR_EOT__##e) +#define BFM_SPI_SR_EOT_V(v) BM_SPI_SR_EOT +#define BP_SPI_SR_DXP 2 +#define BM_SPI_SR_DXP 0x4 +#define BF_SPI_SR_DXP(v) (((v) & 0x1) << 2) +#define BFM_SPI_SR_DXP(v) BM_SPI_SR_DXP +#define BF_SPI_SR_DXP_V(e) BF_SPI_SR_DXP(BV_SPI_SR_DXP__##e) +#define BFM_SPI_SR_DXP_V(v) BM_SPI_SR_DXP +#define BP_SPI_SR_TXP 1 +#define BM_SPI_SR_TXP 0x2 +#define BF_SPI_SR_TXP(v) (((v) & 0x1) << 1) +#define BFM_SPI_SR_TXP(v) BM_SPI_SR_TXP +#define BF_SPI_SR_TXP_V(e) BF_SPI_SR_TXP(BV_SPI_SR_TXP__##e) +#define BFM_SPI_SR_TXP_V(v) BM_SPI_SR_TXP +#define BP_SPI_SR_RXP 0 +#define BM_SPI_SR_RXP 0x1 +#define BF_SPI_SR_RXP(v) (((v) & 0x1) << 0) +#define BFM_SPI_SR_RXP(v) BM_SPI_SR_RXP +#define BF_SPI_SR_RXP_V(e) BF_SPI_SR_RXP(BV_SPI_SR_RXP__##e) +#define BFM_SPI_SR_RXP_V(v) BM_SPI_SR_RXP + +#define REG_SPI_IFCR st_reg(SPI_IFCR) +#define STO_SPI_IFCR (0x18) +#define STT_SPI_IFCR STIO_32_RW +#define STN_SPI_IFCR SPI_IFCR +#define BP_SPI_IFCR_SUSPC 11 +#define BM_SPI_IFCR_SUSPC 0x800 +#define BF_SPI_IFCR_SUSPC(v) (((v) & 0x1) << 11) +#define BFM_SPI_IFCR_SUSPC(v) BM_SPI_IFCR_SUSPC +#define BF_SPI_IFCR_SUSPC_V(e) BF_SPI_IFCR_SUSPC(BV_SPI_IFCR_SUSPC__##e) +#define BFM_SPI_IFCR_SUSPC_V(v) BM_SPI_IFCR_SUSPC +#define BP_SPI_IFCR_TSERFC 10 +#define BM_SPI_IFCR_TSERFC 0x400 +#define BF_SPI_IFCR_TSERFC(v) (((v) & 0x1) << 10) +#define BFM_SPI_IFCR_TSERFC(v) BM_SPI_IFCR_TSERFC +#define BF_SPI_IFCR_TSERFC_V(e) BF_SPI_IFCR_TSERFC(BV_SPI_IFCR_TSERFC__##e) +#define BFM_SPI_IFCR_TSERFC_V(v) BM_SPI_IFCR_TSERFC +#define BP_SPI_IFCR_MODFC 9 +#define BM_SPI_IFCR_MODFC 0x200 +#define BF_SPI_IFCR_MODFC(v) (((v) & 0x1) << 9) +#define BFM_SPI_IFCR_MODFC(v) BM_SPI_IFCR_MODFC +#define BF_SPI_IFCR_MODFC_V(e) BF_SPI_IFCR_MODFC(BV_SPI_IFCR_MODFC__##e) +#define BFM_SPI_IFCR_MODFC_V(v) BM_SPI_IFCR_MODFC +#define BP_SPI_IFCR_TIFREC 8 +#define BM_SPI_IFCR_TIFREC 0x100 +#define BF_SPI_IFCR_TIFREC(v) (((v) & 0x1) << 8) +#define BFM_SPI_IFCR_TIFREC(v) BM_SPI_IFCR_TIFREC +#define BF_SPI_IFCR_TIFREC_V(e) BF_SPI_IFCR_TIFREC(BV_SPI_IFCR_TIFREC__##e) +#define BFM_SPI_IFCR_TIFREC_V(v) BM_SPI_IFCR_TIFREC +#define BP_SPI_IFCR_CRCEC 7 +#define BM_SPI_IFCR_CRCEC 0x80 +#define BF_SPI_IFCR_CRCEC(v) (((v) & 0x1) << 7) +#define BFM_SPI_IFCR_CRCEC(v) BM_SPI_IFCR_CRCEC +#define BF_SPI_IFCR_CRCEC_V(e) BF_SPI_IFCR_CRCEC(BV_SPI_IFCR_CRCEC__##e) +#define BFM_SPI_IFCR_CRCEC_V(v) BM_SPI_IFCR_CRCEC +#define BP_SPI_IFCR_OVRC 6 +#define BM_SPI_IFCR_OVRC 0x40 +#define BF_SPI_IFCR_OVRC(v) (((v) & 0x1) << 6) +#define BFM_SPI_IFCR_OVRC(v) BM_SPI_IFCR_OVRC +#define BF_SPI_IFCR_OVRC_V(e) BF_SPI_IFCR_OVRC(BV_SPI_IFCR_OVRC__##e) +#define BFM_SPI_IFCR_OVRC_V(v) BM_SPI_IFCR_OVRC +#define BP_SPI_IFCR_UDRC 5 +#define BM_SPI_IFCR_UDRC 0x20 +#define BF_SPI_IFCR_UDRC(v) (((v) & 0x1) << 5) +#define BFM_SPI_IFCR_UDRC(v) BM_SPI_IFCR_UDRC +#define BF_SPI_IFCR_UDRC_V(e) BF_SPI_IFCR_UDRC(BV_SPI_IFCR_UDRC__##e) +#define BFM_SPI_IFCR_UDRC_V(v) BM_SPI_IFCR_UDRC +#define BP_SPI_IFCR_TXTFC 4 +#define BM_SPI_IFCR_TXTFC 0x10 +#define BF_SPI_IFCR_TXTFC(v) (((v) & 0x1) << 4) +#define BFM_SPI_IFCR_TXTFC(v) BM_SPI_IFCR_TXTFC +#define BF_SPI_IFCR_TXTFC_V(e) BF_SPI_IFCR_TXTFC(BV_SPI_IFCR_TXTFC__##e) +#define BFM_SPI_IFCR_TXTFC_V(v) BM_SPI_IFCR_TXTFC +#define BP_SPI_IFCR_EOTC 3 +#define BM_SPI_IFCR_EOTC 0x8 +#define BF_SPI_IFCR_EOTC(v) (((v) & 0x1) << 3) +#define BFM_SPI_IFCR_EOTC(v) BM_SPI_IFCR_EOTC +#define BF_SPI_IFCR_EOTC_V(e) BF_SPI_IFCR_EOTC(BV_SPI_IFCR_EOTC__##e) +#define BFM_SPI_IFCR_EOTC_V(v) BM_SPI_IFCR_EOTC + +#define REG_SPI_TXDR8 st_reg(SPI_TXDR8) +#define STO_SPI_TXDR8 (0x20) +#define STT_SPI_TXDR8 STIO_8_RW +#define STN_SPI_TXDR8 SPI_TXDR8 + +#define REG_SPI_TXDR16 st_reg(SPI_TXDR16) +#define STO_SPI_TXDR16 (0x20) +#define STT_SPI_TXDR16 STIO_16_RW +#define STN_SPI_TXDR16 SPI_TXDR16 + +#define REG_SPI_TXDR32 st_reg(SPI_TXDR32) +#define STO_SPI_TXDR32 (0x20) +#define STT_SPI_TXDR32 STIO_32_RW +#define STN_SPI_TXDR32 SPI_TXDR32 + +#define REG_SPI_RXDR8 st_reg(SPI_RXDR8) +#define STO_SPI_RXDR8 (0x30) +#define STT_SPI_RXDR8 STIO_8_RW +#define STN_SPI_RXDR8 SPI_RXDR8 + +#define REG_SPI_RXDR16 st_reg(SPI_RXDR16) +#define STO_SPI_RXDR16 (0x30) +#define STT_SPI_RXDR16 STIO_16_RW +#define STN_SPI_RXDR16 SPI_RXDR16 + +#define REG_SPI_RXDR32 st_reg(SPI_RXDR32) +#define STO_SPI_RXDR32 (0x30) +#define STT_SPI_RXDR32 STIO_32_RW +#define STN_SPI_RXDR32 SPI_RXDR32 + +#define REG_SPI_CRCPOLY st_reg(SPI_CRCPOLY) +#define STO_SPI_CRCPOLY (0x40) +#define STT_SPI_CRCPOLY STIO_32_RW +#define STN_SPI_CRCPOLY SPI_CRCPOLY + +#define REG_SPI_TXCRC st_reg(SPI_TXCRC) +#define STO_SPI_TXCRC (0x44) +#define STT_SPI_TXCRC STIO_32_RW +#define STN_SPI_TXCRC SPI_TXCRC + +#define REG_SPI_RXCRC st_reg(SPI_RXCRC) +#define STO_SPI_RXCRC (0x48) +#define STT_SPI_RXCRC STIO_32_RW +#define STN_SPI_RXCRC SPI_RXCRC + +#define REG_SPI_UDRDR st_reg(SPI_UDRDR) +#define STO_SPI_UDRDR (0x4c) +#define STT_SPI_UDRDR STIO_32_RW +#define STN_SPI_UDRDR SPI_UDRDR + +#define REG_SPI_I2SCFGR st_reg(SPI_I2SCFGR) +#define STO_SPI_I2SCFGR (0x50) +#define STT_SPI_I2SCFGR STIO_32_RW +#define STN_SPI_I2SCFGR SPI_I2SCFGR +#define BP_SPI_I2SCFGR_I2SDIV 16 +#define BM_SPI_I2SCFGR_I2SDIV 0xff0000 +#define BF_SPI_I2SCFGR_I2SDIV(v) (((v) & 0xff) << 16) +#define BFM_SPI_I2SCFGR_I2SDIV(v) BM_SPI_I2SCFGR_I2SDIV +#define BF_SPI_I2SCFGR_I2SDIV_V(e) BF_SPI_I2SCFGR_I2SDIV(BV_SPI_I2SCFGR_I2SDIV__##e) +#define BFM_SPI_I2SCFGR_I2SDIV_V(v) BM_SPI_I2SCFGR_I2SDIV +#define BP_SPI_I2SCFGR_DATLEN 8 +#define BM_SPI_I2SCFGR_DATLEN 0x300 +#define BV_SPI_I2SCFGR_DATLEN__16BIT 0x0 +#define BV_SPI_I2SCFGR_DATLEN__24BIT 0x1 +#define BV_SPI_I2SCFGR_DATLEN__32BIT 0x2 +#define BF_SPI_I2SCFGR_DATLEN(v) (((v) & 0x3) << 8) +#define BFM_SPI_I2SCFGR_DATLEN(v) BM_SPI_I2SCFGR_DATLEN +#define BF_SPI_I2SCFGR_DATLEN_V(e) BF_SPI_I2SCFGR_DATLEN(BV_SPI_I2SCFGR_DATLEN__##e) +#define BFM_SPI_I2SCFGR_DATLEN_V(v) BM_SPI_I2SCFGR_DATLEN +#define BP_SPI_I2SCFGR_I2SSTD 4 +#define BM_SPI_I2SCFGR_I2SSTD 0x30 +#define BV_SPI_I2SCFGR_I2SSTD__I2S 0x0 +#define BV_SPI_I2SCFGR_I2SSTD__MSB_JUSTIFIED 0x1 +#define BV_SPI_I2SCFGR_I2SSTD__LSB_JUSTIFIED 0x2 +#define BV_SPI_I2SCFGR_I2SSTD__PCM 0x3 +#define BF_SPI_I2SCFGR_I2SSTD(v) (((v) & 0x3) << 4) +#define BFM_SPI_I2SCFGR_I2SSTD(v) BM_SPI_I2SCFGR_I2SSTD +#define BF_SPI_I2SCFGR_I2SSTD_V(e) BF_SPI_I2SCFGR_I2SSTD(BV_SPI_I2SCFGR_I2SSTD__##e) +#define BFM_SPI_I2SCFGR_I2SSTD_V(v) BM_SPI_I2SCFGR_I2SSTD +#define BP_SPI_I2SCFGR_I2SCFG 1 +#define BM_SPI_I2SCFGR_I2SCFG 0xe +#define BV_SPI_I2SCFGR_I2SCFG__SLAVE_TX 0x0 +#define BV_SPI_I2SCFGR_I2SCFG__SLAVE_RX 0x1 +#define BV_SPI_I2SCFGR_I2SCFG__MASTER_TX 0x2 +#define BV_SPI_I2SCFGR_I2SCFG__MASTER_RX 0x3 +#define BV_SPI_I2SCFGR_I2SCFG__SLAVE_DUPLEX 0x4 +#define BV_SPI_I2SCFGR_I2SCFG__MASTER_DUPLEX 0x5 +#define BF_SPI_I2SCFGR_I2SCFG(v) (((v) & 0x7) << 1) +#define BFM_SPI_I2SCFGR_I2SCFG(v) BM_SPI_I2SCFGR_I2SCFG +#define BF_SPI_I2SCFGR_I2SCFG_V(e) BF_SPI_I2SCFGR_I2SCFG(BV_SPI_I2SCFGR_I2SCFG__##e) +#define BFM_SPI_I2SCFGR_I2SCFG_V(v) BM_SPI_I2SCFGR_I2SCFG +#define BP_SPI_I2SCFGR_MCKOE 25 +#define BM_SPI_I2SCFGR_MCKOE 0x2000000 +#define BF_SPI_I2SCFGR_MCKOE(v) (((v) & 0x1) << 25) +#define BFM_SPI_I2SCFGR_MCKOE(v) BM_SPI_I2SCFGR_MCKOE +#define BF_SPI_I2SCFGR_MCKOE_V(e) BF_SPI_I2SCFGR_MCKOE(BV_SPI_I2SCFGR_MCKOE__##e) +#define BFM_SPI_I2SCFGR_MCKOE_V(v) BM_SPI_I2SCFGR_MCKOE +#define BP_SPI_I2SCFGR_ODD 24 +#define BM_SPI_I2SCFGR_ODD 0x1000000 +#define BF_SPI_I2SCFGR_ODD(v) (((v) & 0x1) << 24) +#define BFM_SPI_I2SCFGR_ODD(v) BM_SPI_I2SCFGR_ODD +#define BF_SPI_I2SCFGR_ODD_V(e) BF_SPI_I2SCFGR_ODD(BV_SPI_I2SCFGR_ODD__##e) +#define BFM_SPI_I2SCFGR_ODD_V(v) BM_SPI_I2SCFGR_ODD +#define BP_SPI_I2SCFGR_DATFMT 14 +#define BM_SPI_I2SCFGR_DATFMT 0x4000 +#define BV_SPI_I2SCFGR_DATFMT__RIGHT_ALIGNED 0x0 +#define BV_SPI_I2SCFGR_DATFMT__LEFT_ALIGNED 0x1 +#define BF_SPI_I2SCFGR_DATFMT(v) (((v) & 0x1) << 14) +#define BFM_SPI_I2SCFGR_DATFMT(v) BM_SPI_I2SCFGR_DATFMT +#define BF_SPI_I2SCFGR_DATFMT_V(e) BF_SPI_I2SCFGR_DATFMT(BV_SPI_I2SCFGR_DATFMT__##e) +#define BFM_SPI_I2SCFGR_DATFMT_V(v) BM_SPI_I2SCFGR_DATFMT +#define BP_SPI_I2SCFGR_WSINV 13 +#define BM_SPI_I2SCFGR_WSINV 0x2000 +#define BF_SPI_I2SCFGR_WSINV(v) (((v) & 0x1) << 13) +#define BFM_SPI_I2SCFGR_WSINV(v) BM_SPI_I2SCFGR_WSINV +#define BF_SPI_I2SCFGR_WSINV_V(e) BF_SPI_I2SCFGR_WSINV(BV_SPI_I2SCFGR_WSINV__##e) +#define BFM_SPI_I2SCFGR_WSINV_V(v) BM_SPI_I2SCFGR_WSINV +#define BP_SPI_I2SCFGR_FIXCH 12 +#define BM_SPI_I2SCFGR_FIXCH 0x1000 +#define BF_SPI_I2SCFGR_FIXCH(v) (((v) & 0x1) << 12) +#define BFM_SPI_I2SCFGR_FIXCH(v) BM_SPI_I2SCFGR_FIXCH +#define BF_SPI_I2SCFGR_FIXCH_V(e) BF_SPI_I2SCFGR_FIXCH(BV_SPI_I2SCFGR_FIXCH__##e) +#define BFM_SPI_I2SCFGR_FIXCH_V(v) BM_SPI_I2SCFGR_FIXCH +#define BP_SPI_I2SCFGR_CKPOL 11 +#define BM_SPI_I2SCFGR_CKPOL 0x800 +#define BF_SPI_I2SCFGR_CKPOL(v) (((v) & 0x1) << 11) +#define BFM_SPI_I2SCFGR_CKPOL(v) BM_SPI_I2SCFGR_CKPOL +#define BF_SPI_I2SCFGR_CKPOL_V(e) BF_SPI_I2SCFGR_CKPOL(BV_SPI_I2SCFGR_CKPOL__##e) +#define BFM_SPI_I2SCFGR_CKPOL_V(v) BM_SPI_I2SCFGR_CKPOL +#define BP_SPI_I2SCFGR_CHLEN 10 +#define BM_SPI_I2SCFGR_CHLEN 0x400 +#define BV_SPI_I2SCFGR_CHLEN__16BIT 0x0 +#define BV_SPI_I2SCFGR_CHLEN__32BIT 0x1 +#define BF_SPI_I2SCFGR_CHLEN(v) (((v) & 0x1) << 10) +#define BFM_SPI_I2SCFGR_CHLEN(v) BM_SPI_I2SCFGR_CHLEN +#define BF_SPI_I2SCFGR_CHLEN_V(e) BF_SPI_I2SCFGR_CHLEN(BV_SPI_I2SCFGR_CHLEN__##e) +#define BFM_SPI_I2SCFGR_CHLEN_V(v) BM_SPI_I2SCFGR_CHLEN +#define BP_SPI_I2SCFGR_PCMSYNC 7 +#define BM_SPI_I2SCFGR_PCMSYNC 0x80 +#define BV_SPI_I2SCFGR_PCMSYNC__SHORT 0x0 +#define BV_SPI_I2SCFGR_PCMSYNC__LONG 0x1 +#define BF_SPI_I2SCFGR_PCMSYNC(v) (((v) & 0x1) << 7) +#define BFM_SPI_I2SCFGR_PCMSYNC(v) BM_SPI_I2SCFGR_PCMSYNC +#define BF_SPI_I2SCFGR_PCMSYNC_V(e) BF_SPI_I2SCFGR_PCMSYNC(BV_SPI_I2SCFGR_PCMSYNC__##e) +#define BFM_SPI_I2SCFGR_PCMSYNC_V(v) BM_SPI_I2SCFGR_PCMSYNC +#define BP_SPI_I2SCFGR_I2SMOD 0 +#define BM_SPI_I2SCFGR_I2SMOD 0x1 +#define BF_SPI_I2SCFGR_I2SMOD(v) (((v) & 0x1) << 0) +#define BFM_SPI_I2SCFGR_I2SMOD(v) BM_SPI_I2SCFGR_I2SMOD +#define BF_SPI_I2SCFGR_I2SMOD_V(e) BF_SPI_I2SCFGR_I2SMOD(BV_SPI_I2SCFGR_I2SMOD__##e) +#define BFM_SPI_I2SCFGR_I2SMOD_V(v) BM_SPI_I2SCFGR_I2SMOD + +#endif /* __HEADERGEN_SPI_H__*/ diff --git a/firmware/target/arm/stm32/stm32h7/syscfg.h b/firmware/target/arm/stm32/stm32h7/syscfg.h new file mode 100644 index 0000000000..8418735d99 --- /dev/null +++ b/firmware/target/arm/stm32/stm32h7/syscfg.h @@ -0,0 +1,43 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * This file was automatically generated by headergen, DO NOT EDIT it. + * headergen version: 3.0.0 + * stm32h743 version: 1.0 + * stm32h743 authors: Aidan MacDonald + * + * Copyright (C) 2015 by the authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ +#ifndef __HEADERGEN_SYSCFG_H__ +#define __HEADERGEN_SYSCFG_H__ + +#include "macro.h" + +#define STA_SYSCFG (0x58000400) + +#define REG_SYSCFG_PWRCFG st_reg(SYSCFG_PWRCFG) +#define STA_SYSCFG_PWRCFG (0x58000400 + 0x2c) +#define STO_SYSCFG_PWRCFG (0x2c) +#define STT_SYSCFG_PWRCFG STIO_32_RW +#define STN_SYSCFG_PWRCFG SYSCFG_PWRCFG +#define BP_SYSCFG_PWRCFG_ODEN 0 +#define BM_SYSCFG_PWRCFG_ODEN 0x1 +#define BF_SYSCFG_PWRCFG_ODEN(v) (((v) & 0x1) << 0) +#define BFM_SYSCFG_PWRCFG_ODEN(v) BM_SYSCFG_PWRCFG_ODEN +#define BF_SYSCFG_PWRCFG_ODEN_V(e) BF_SYSCFG_PWRCFG_ODEN(BV_SYSCFG_PWRCFG_ODEN__##e) +#define BFM_SYSCFG_PWRCFG_ODEN_V(v) BM_SYSCFG_PWRCFG_ODEN + +#endif /* __HEADERGEN_SYSCFG_H__*/ diff --git a/utils/reggen-ng/stm32h743.reggen b/utils/reggen-ng/stm32h743.reggen new file mode 100644 index 0000000000..02aed537ba --- /dev/null +++ b/utils/reggen-ng/stm32h743.reggen @@ -0,0 +1,685 @@ +name "stm32h743" +title "STM32H743" +isa "armv7-m" +version "1.0" +author "Aidan MacDonald" + +node FLASH { + title "Embedded flash memory" + addr 0x52002000 + + reg ACR 0x00 { + fld 5 3 WRHIGHFREQ + fld 3 0 LATENCY + } +} + +node PWR { + title "Power control" + addr 0x58024800 + + reg CR1 0x00 { + fld 18 17 ALS + bit 16 AVDEN + fld 15 14 SVOS + bit 9 FLPS + bit 8 DBP + fld 7 5 PLS + bit 4 PVDE + bit 0 LPDS + } + + reg CSR1 0x04 { + bit 16 AVDO + fld 15 14 ACTVOS + bit 13 ACTVOSRDY + bit 4 PVDO + } + + reg CR3 0x0c { + bit 26 USB33RDY + bit 25 USBREGEN + bit 24 USB33DEN + bit 9 VBRS + bit 8 VBE + bit 2 SCUEN + bit 1 LDOEN + bit 0 BYPASS + } + + reg D3CR 0x18 { + fld 15 14 VOS { enum VOS3 1; enum VOS2 2; enum VOS1 3; } + bit 13 VOSRDY + } +} + +node RCC { + title "Reset and clock control" + addr 0x58024400 + + reg CR 0x00 { + bit 29 PLL3RDY + bit 28 PLL3ON + bit 27 PLL2RDY + bit 26 PLL2ON + bit 25 PLL1RDY + bit 24 PLL1ON + bit 19 HSECSSON + bit 18 HSEBYP + bit 17 HSERDY + bit 16 HSEON + bit 15 D2CKRDY + bit 14 D1CKRDY + bit 13 HSI48RDY + bit 12 HSI48ON + bit 9 CSIKERON + bit 8 CSIRDY + bit 7 CSION + bit 5 HSIDIVF + fld 4 3 HSIDIV + bit 2 HSIRDY + bit 1 HSIKERON + bit 0 HSION + } + + reg CFGR 0x10 { + fld 31 29 MCO2 { enum SYSCLK 0; enum PLL2P 1; enum HSE 2; enum PLL1P 3; enum CSI 4; enum LSI 5 } + fld 28 25 MCO2PRE + fld 24 22 MCO1 { enum HSI 0; enum LSE 1; enum HSE 2; enum PLL1Q 3; enum HSI48 4 } + fld 21 18 MCO1PRE + bit 15 TIMPRE + bit 14 HRTIMSEL + fld 13 8 RTCPRE + bit 7 STOPKERWUCK + bit 6 STOPWUCK + fld 5 3 SWS + fld 2 0 SW { enum HSI 0; enum CSI 1; enum HSE 2; enum PLL1P 3; } + } + + reg D1CFGR 0x18 { + fld 11 8 D1CPRE + fld 6 4 D1PPRE + fld 4 0 HPRE + } + + reg D2CFGR 0x1c { + fld 10 8 D2PPRE2 + fld 6 4 D2PPRE1 + } + + reg D3CFGR 0x20 { + fld 6 4 D3PPRE + } + + reg PLLCKSELR 0x28 { + fld 25 20 DIVM3 + fld 17 12 DIVM2 + fld 9 4 DIVM1 + fld 1 0 PLLSRC { enum HSI 0; enum CSI 1; enum HSE 2; enum NONE 3; } + } + + reg PLLCFGR 0x2c { + bit 24 DIVR3EN + bit 23 DIVQ3EN + bit 22 DIVP3EN + bit 21 DIVR2EN + bit 20 DIVQ2EN + bit 19 DIVP2EN + bit 18 DIVR1EN + bit 17 DIVQ1EN + bit 16 DIVP1EN + fld 11 10 PLL3RGE { enum 1_2MHZ 0; enum 2_4MHz 1; enum 4_8MHz 2; enum 8_16MHz 3; } + bit 9 PLL3VCOSEL { enum WIDE 0; enum MEDIUM 1; } + bit 8 PLL3FRACEN + fld 7 6 PLL2RGE { enum 1_2MHZ 0; enum 2_4MHz 1; enum 4_8MHz 2; enum 8_16MHz 3; } + bit 5 PLL2VCOSEL { enum WIDE 0; enum MEDIUM 1; } + bit 4 PLL2FRACEN + fld 3 2 PLL1RGE { enum 1_2MHZ 0; enum 2_4MHz 1; enum 4_8MHz 2; enum 8_16MHz 3; } + bit 1 PLL1VCOSEL { enum WIDE 0; enum MEDIUM 1; } + bit 0 PLL1FRACEN + } + + reg PLLxDIVR { + instance PLL1DIVR 0x30 + instance PLL2DIVR 0x38 + instance PLL3DIVR 0x40 + + fld 30 24 DIVR + fld 22 16 DIVQ + fld 15 9 DIVP + fld 8 0 DIVN + } + + reg PLLxFRACR { + instance PLL1FRACR 0x34 + instance PLL2FRACR 0x3c + instance PLL3FRACR 0x44 + + fld 15 3 FRACN + } + + reg D1CCIPR 0x4c { + fld 29 28 CKPERSEL { enum HSI 0; enum CSI 1; enum HSE 2; } + bit 16 SDMMCSEL { enum PLL1Q 0; enum PLL2R 1; } + fld 5 4 QSPISEL { enum AHB 0; enum PLL1Q 1; enum PLL2R 2; enum PER 3; } + fld 1 0 FMCSEL { enum AHB 0; enum PLL1Q 1; enum PLL2R 2; enum PER 3; } + } + + reg D2CCIP1R 0x50 { + bit 31 SWPSEL { enum APB1 0; enum HSI 1; } + fld 29 28 FDCANSEL { enum HSE 0; enum PLL1Q 1; enum PLL2Q 1; } + bit 24 DFSDM1SEL { enum APB2 0; enum SYSCLK 1; } + fld 21 20 SPDIFSEL { enum PLL1Q 0; enum PLL2R 1; enum PLL3R 2; enum HSI 3; } + fld 18 16 SPI45SEL { enum APB2 0; enum PLL2Q 1; enum PLL3Q 2; enum HSI 3; + enum CSI 4; enum HSE 5; } + fld 14 12 SPI123SEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2; enum I2SCKIN 3; + enum PER 4; } + fld 8 6 SAI23SEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2; enum I2SCKIN 4; + enum PER 4; } + fld 2 0 SAI1SEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2; enum I2SCKIN 4; + enum PER 4; } + } + + reg D2CCIP2R 0x54 { + fld 30 28 LPTIM1SEL { enum APB1 0; enum PLL2P 1; enum PLL3R 2; + enum LSE 3; enum LSI 4; enum PER 5; } + fld 23 22 CECSEL { enum LSE 0; enum LSI 1; enum CSI 2; } + fld 21 20 USBSEL { enum DISABLE 0; enum PLL1Q 1; enum PLL3Q 2; enum HSI48 3; } + fld 13 12 I2C123SEL { enum APB1 0; enum PLL3R 1; enum HSI 2; enum CSI 3; } + fld 9 8 RNGSEL { enum HSI 0; enum PLL1Q 1; enum LSE 2; enum LSI 3; } + fld 5 3 USART16SEL { enum APB2 0; enum PLL2Q 1; enum PLL3Q 2; + enum HSI 3; enum CSI 4; enum LSE 5; } + fld 2 0 USART234578SEL { enum APB1 0; enum PLL2Q 1; enum PLL3Q 2; + enum HSI 3; enum CSI 4; enum LSE 5; } + } + + reg D3CCIPR 0x58 { + fld 30 28 SPI6SEL { enum APB4 0; enum PLL2Q 1; enum PLL3Q 2; + enum HSI 3; enum CSI 4; enum HSE 5; } + fld 26 24 SAI4BSEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2; + enum I2S_CKIN 3; enum PER 4; } + fld 23 21 SAI4ASEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2; + enum I2S_CKIN 3; enum PER 4; } + fld 17 16 ADCSEL { enum PLL2P 0; enum PLL3R 1; enum PER 2; } + fld 15 13 LPTIM345SEL { enum APB4 0; enum PLL2P 1; enum PLL3R 2; + enum LSE 3; enum LSI 4; enum PER 5; } + fld 12 10 LPTIM2SEL { enum APB4 0; enum PLL2P 1; enum PLL3R 2; + enum LSE 3; enum LSI 4; enum PER 5; } + fld 9 8 I2C4SEL { enum APB4 0; enum PLL3R 1; enum HSI 2; enum CSI 3; } + fld 2 0 LPUART1SEL { enum APB4 0; enum PLL2Q 1; enum PLL3Q 2; + enum HSI 3; enum CSI 4; enum LSE 5; } + } + + reg BDCR 0x70 { + bit 16 BDRST + bit 15 RTCEN + fld 9 8 RTCSEL { enum NONE 0; enum LSE 1; enum LSI 2; enum HSE 3; } + bit 6 LSECSSD + bit 5 LSECSSON + fld 4 3 LSEDRV { enum LOW 0; enum MED_LOW 1; enum MED_HIGH 2; enum HIGH 3; } + bit 2 LSEBYP + bit 1 LSERDY + bit 0 LSEON + } + + reg CSR 0x74 { + bit 1 LSIRDY + bit 0 LSION + } + + reg AHB3EN { + instance AHB3ENR 0xd4 + instance AHB3LPENR 0xfc + + # note: + # - bits 8 and 28-31 exist in AHB3LPENR only + # - all other bits are common + + bit 31 AXISRAMEN + bit 30 ITCMEN + bit 29 DTCM2EN + bit 28 D1DTCM1EN + bit 16 SDMMC1EN + bit 14 QSPIEN + bit 12 FMCEN + bit 8 FLASHEN + bit 5 JPEGDECEN + bit 4 DMA2DEN + bit 0 MDMAEN + } + + reg AHB4EN { + instance AHB4ENR 0xe0 + instance AHB4LPENR 0x108 + + # note: + # - bit 29 exists in AHB4LPENR only + # - bit 25 exists in AHB4ENR only + # - all other bits are common + + bit 29 SRAM4EN + bit 28 BKPRAMEN + bit 25 HSEMEN + bit 24 ADC3EN + bit 21 BDMAEN + bit 19 CRCEN + bit 10 GPIOKEN + bit 9 GPIOJEN + bit 8 GPIOIEN + bit 7 GPIOHEN + bit 6 GPIOGEN + bit 5 GPIOFEN + bit 4 GPIOEEN + bit 3 GPIODEN + bit 2 GPIOCEN + bit 1 GPIOBEN + bit 0 GPIOAEN + } + + reg APB3EN { + instance APB3ENR 0xe4 + instance APB3LPENR 0x10c + + bit 6 WWDG1EN + bit 3 LTDCEN + } + + reg APB1LEN { + instance APB1LENR 0xe8 + instance APB1LLPENR 0x110 + + bit 31 UART8EN + bit 30 UART7EN + bit 29 DAC12EN + bit 27 CECEN + bit 23 I2C3EN + bit 22 I2C2EN + bit 21 I2C1EN + bit 20 UART5EN + bit 19 UART4EN + bit 18 USART3EN + bit 17 USART2EN + bit 16 SPDIFRXEN + bit 15 SPI3EN + bit 14 SPI2EN + bit 9 LPTIM1EN + bit 8 TIM14EN + bit 7 TIM13EN + bit 6 TIM12EN + bit 5 TIM7EN + bit 4 TIM6EN + bit 3 TIM5EN + bit 2 TIM4EN + bit 1 TIM3EN + bit 0 TIM2EN + } + + reg APB1HEN { + instance APB1HENR 0xec + instance APB1HLPENR 0x114 + + bit 8 FDCANEN + bit 5 MDIOSEN + bit 4 OPAMPEN + bit 2 SWPEN + bit 1 CRSEN + } + + reg APB2EN { + instance APB2ENR 0xf0 + instance APB2LPENR 0x118 + + bit 29 HRTIMEN + bit 28 DFSDM1EN + bit 24 SAI3EN + bit 23 SAI2EN + bit 22 SAI1EN + bit 20 SPI5EN + bit 18 TIM17EN + bit 17 TIM16EN + bit 16 TIM15EN + bit 13 SPI4EN + bit 12 SPI1EN + bit 5 USART6EN + bit 4 USART1EN + bit 1 TIM8EN + bit 0 TIM1EN + } + + reg APB4EN { + instance APB4ENR 0xf4 + instance APB4LPENR 0x11c + + bit 21 SAI4EN + bit 16 RTCAPBEN + bit 15 VREFEN + bit 14 COMP12EN + bit 12 LPTIM5EN + bit 11 LPTIM4EN + bit 10 LPTIM3EN + bit 9 LPTIM2EN + bit 7 I2C4EN + bit 5 SPI6EN + bit 3 LPUART1EN + bit 1 SYSCFGEN + } +} + +node GPIO { + title "General-purpose I/Os" + instance 0x58020000 0x400 11 + + reg MODER 0x00 + reg OTYPER 0x04 + reg OSPEEDR 0x08 + reg PUPDR 0x0c + reg IDR 0x10 + reg ODR 0x14 + reg BSRR 0x18 + reg LCKR 0x1c + reg AFRL 0x20 + reg AFRH 0x24 +} + +node SYSCFG { + title "System configuration controller" + addr 0x58000400 + + reg PWRCFG 0x2c { + bit 0 ODEN + } +} + +node FMC { + title "Flexible memory controller" + addr 0x52004000 + + reg BCR { + instance 0x000 0x8 4 + + bit 31 FMCEN + fld 25 24 BMAP + bit 21 WFDIS + } + + reg SDCR { + instance 0x140 0x4 2 + + fld 14 13 RPIPE + bit 12 RBURST + fld 11 10 SDCLK + bit 9 WP + fld 8 7 CAS + bit 6 NB + fld 5 4 MWID + fld 3 2 NR + fld 1 0 NC + } + + reg SDTR { + instance 0x148 0x4 2 + + fld 27 24 TRCD + fld 23 20 TRP + fld 19 16 TWR + fld 15 12 TRC + fld 11 8 TRAS + fld 7 4 TXSR + fld 3 0 TMRD + } + + reg SDCMR 0x150 { + fld 22 9 MRD + fld 8 5 NRFS + bit 4 CTB1 + bit 3 CTB2 + fld 2 0 MODE + } + + reg SDRTR 0x154 { + bit 14 REIE + fld 13 1 COUNT + bit 0 CRE + } + + reg SDSR 0x158 { + fld 4 3 MODES2 + fld 2 1 MODES1 + bit 0 RE + } +} + +node RTC { + title "Real time clock" + addr 0x58004000 + + reg TR { + instance TR 0x00 + instance TSTR 0x30 + + bit 22 PM + fld 21 20 HT + fld 19 16 HU + fld 14 12 MNT + fld 11 8 MNU + fld 6 4 ST + fld 3 0 SU + } + + reg DR { + instance DR 0x04 + instance DRTR 0x34 + + fld 23 20 YT + fld 19 16 YU + fld 15 13 WDU + bit 12 MT + fld 11 8 MU + fld 5 4 DT + fld 3 0 DU + } + + reg CR 0x08 { + bit 24 ITSE + bit 23 COE + fld 22 21 OSEL { enum DISABLED 0; enum ALARM_A 1; enum ALARM_B 2; enum WAKEUP 3; } + bit 20 POL + bit 19 COSEL + bit 18 BKP + bit 17 SUB1H + bit 16 ADD1H + bit 15 TSIE + bit 14 WUTIE + bit 13 ALRBIE + bit 12 ALRAIE + bit 11 TSE + bit 10 WUTE + bit 9 ALRBE + bit 8 ALRAE + bit 6 FMT + bit 5 BYPSHAD + bit 4 REFCKON + bit 3 TSEDGE + bit 2 0 WUCKSEL { enum RTC_16 0; enum RTC_8 1; enum RTC_4 2; enum RTC_2 3; + enum CK_SPRE 4; enum CK_SPRE_ADDWUT 6; } + } + + reg ISR 0x0c { + bit 17 ITSF + bit 16 RECALPF + bit 15 TAMP3F + bit 14 TAMP2F + bit 13 TAMP1F + bit 12 TSOVF + bit 11 TSF + bit 10 WUTF + bit 9 ALRBF + bit 8 ALRAF + bit 7 INIT + bit 6 INITF + bit 5 RSF + bit 4 INITS + bit 3 SHPF + bit 2 WUTWF + bit 1 ALRBWF + bit 0 ALRAWF + } + + reg PRER 0x10 { + fld 22 16 PREDIV_A + fld 14 0 PREDIV_S + } + + reg WPR 0x24 { + fld 7 0 KEY { enum KEY1 0xCA; enum KEY2 0x53; } + } + + reg SSR { + instance SSR 0x28 + instance TSSSR 0x38 + + fld 15 0 SS + } + + reg OR 0x4c { + bit 1 RTC_OUT_RMP + bit 0 RTC_ALARM_TYPE { enum OPEN_DRAIN 0; enum PUSH_PULL 1; } + } + + reg BKPR { + instance 0x50 0x4 32 + } +} + +node SPI { + title "Serial peripheral interface" + instance nochild SPI1 0x40013000 + instance nochild SPI2 0x40003800 + instance nochild SPI3 0x40003c00 + instance nochild SPI4 0x40013400 + instance nochild SPI5 0x40015000 + instance nochild SPI6 0x58001400 + instance floating + + reg CR1 0x00 { + bit 16 IO_LOCK + bit 15 TCRCINI + bit 14 RCRCINI + bit 13 CRC33_17 + bit 12 SSI + bit 11 HDDIR + bit 10 CSUSP + bit 9 CSTART + bit 8 MASRX + bit 0 SPE + } + + reg CR2 0x04 { + fld 31 16 TSER + fld 15 0 TSIZE + } + + reg CFG1 0x08 { + fld 30 28 MBR + bit 22 CRCEN + fld 20 16 CRCSIZE + bit 15 TXDMAEN + bit 14 RXDMAEN + fld 12 11 UDRDET + fld 10 9 UDRCFG + fld 8 5 FTHLV + fld 4 0 DSIZE + } + + reg CFG2 0x0c { + bit 31 AFCNTR + bit 30 SSOM + bit 29 SSOE + bit 28 SSIOP + bit 26 SSM { enum SS_PAD 0; enum SSI_BIT 1; } + bit 25 CPOL + bit 24 CPHA + bit 23 LSBFIRST + bit 22 MASTER + fld 21 19 SP { enum MOTOROLA 0; enum TI 1; } + fld 18 17 COMM { enum DUPLEX 0; enum TXONLY 1; enum RXONLY 2; enum HALF_DUPLEX 3; } + bit 15 IOSWP + fld 7 4 MIDI + fld 3 0 MSSI + } + + reg IER 0x10 { + bit 10 TSERFIE + bit 9 MODFIE + bit 8 TIFREIE + bit 7 CRCEIE + bit 6 OVRIE + bit 5 UDRIE + bit 4 TXTFIE + bit 3 EOTIE + bit 2 DXPIE + bit 1 TXPIE + bit 0 RXPIE + } + + reg SR 0x14 { + fld 31 16 CTSIZE + bit 15 RXWNE + fld 14 13 RXPLVL + bit 12 TXC + bit 11 SUSP + bit 10 TSERF + bit 9 MODF + bit 8 TIFRE + bit 7 CRCE + bit 6 OVR + bit 5 UDR + bit 4 TXTF + bit 3 EOT + bit 2 DXP + bit 1 TXP + bit 0 RXP + } + + reg IFCR 0x18 { + bit 11 SUSPC + bit 10 TSERFC + bit 9 MODFC + bit 8 TIFREC + bit 7 CRCEC + bit 6 OVRC + bit 5 UDRC + bit 4 TXTFC + bit 3 EOTC + } + + reg 8 TXDR8 0x20 + reg 16 TXDR16 0x20 + reg 32 TXDR32 0x20 + reg 8 RXDR8 0x30 + reg 16 RXDR16 0x30 + reg 32 RXDR32 0x30 + + reg CRCPOLY 0x40 + reg TXCRC 0x44 + reg RXCRC 0x48 + reg UDRDR 0x4c + + reg I2SCFGR 0x50 { + bit 25 MCKOE + bit 24 ODD + fld 23 16 I2SDIV + bit 14 DATFMT { enum RIGHT_ALIGNED 0; enum LEFT_ALIGNED 1; } + bit 13 WSINV + bit 12 FIXCH + bit 11 CKPOL + bit 10 CHLEN { enum 16BIT 0; enum 32BIT 1; } + fld 9 8 DATLEN { enum 16BIT 0; enum 24BIT 1; enum 32BIT 2; } + bit 7 PCMSYNC { enum SHORT 0; enum LONG 1; } + fld 5 4 I2SSTD { enum I2S 0; enum MSB_JUSTIFIED 1; enum LSB_JUSTIFIED 2; enum PCM 3; } + fld 3 1 I2SCFG { enum SLAVE_TX 0; enum SLAVE_RX 1; + enum MASTER_TX 2; enum MASTER_RX 3; + enum SLAVE_DUPLEX 4; enum MASTER_DUPLEX 5; } + bit 0 I2SMOD + } +}