forked from len0rd/rockbox
Gigabeat S: Use the fastest PIO mode the installed drive allows instead of always PIO0. Centralize clock information in clkctl-imx31.c.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17371 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
367aec35d7
commit
be0c7d0ff3
6 changed files with 173 additions and 111 deletions
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@ -1089,6 +1089,10 @@ static int identify(void)
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identify_info[i] = ATA_DATA;
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#endif
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}
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#ifdef ATA_NOTIFY_IDENTIFY_READY
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ata_identify_ready();
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#endif
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return 0;
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}
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@ -26,32 +26,7 @@
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#include "debug-target.h"
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#include "mc13783.h"
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#include "adc.h"
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#define CONFIG_CLK32_FREQ 32768
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#define CONFIG_HCLK_FREQ 27000000
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/* Return PLL frequency in HZ */
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static unsigned int decode_pll(unsigned int reg,
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unsigned int infreq)
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{
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uint64_t mfi = (reg >> 10) & 0xf;
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uint64_t mfn = reg & 0x3ff;
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uint64_t mfd = ((reg >> 16) & 0x3ff) + 1;
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uint64_t pd = ((reg >> 26) & 0xf) + 1;
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mfi = mfi <= 5 ? 5 : mfi;
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return 2*infreq*(mfi * mfd + mfn) / (mfd * pd);
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}
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/* Get the PLL reference clock frequency */
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static unsigned int get_pll_ref_clk_freq(void)
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{
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if ((CLKCTL_CCMR & (3 << 1)) == (1 << 1))
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return CONFIG_CLK32_FREQ * 1024;
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else
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return CONFIG_HCLK_FREQ;
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}
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#include "clkctl-imx31.h"
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bool __dbg_hw_info(void)
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{
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@ -74,11 +49,11 @@ bool __dbg_hw_info(void)
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spctl = CLKCTL_SPCTL;
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upctl = CLKCTL_UPCTL;
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pllref = get_pll_ref_clk_freq();
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pllref = imx31_clkctl_get_pll_ref_clk();
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mcu_pllfreq = decode_pll(mpctl, pllref);
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ser_pllfreq = decode_pll(spctl, pllref);
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usb_pllfreq = decode_pll(upctl, pllref);
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mcu_pllfreq = imx31_clkctl_get_pll(PLL_MCU);
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ser_pllfreq = imx31_clkctl_get_pll(PLL_SERIAL);
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usb_pllfreq = imx31_clkctl_get_pll(PLL_USB);
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snprintf(buf, sizeof (buf), "pll_ref_clk: %u", pllref);
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lcd_puts(0, line++, buf); line++;
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@ -23,8 +23,82 @@
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#include "system.h"
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#include "power.h"
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#include "panic.h"
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#include "pcf50606.h"
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#include "ata-target.h"
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#include "ata.h"
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#include "clkctl-imx31.h"
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static const struct ata_pio_timings
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{
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uint16_t time_2w; /* t2 during write */
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uint16_t time_2r; /* t2 during read */
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uint8_t time_1; /* t1 */
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uint8_t time_pio_rdx; /* trd */
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uint8_t time_4; /* t4 */
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uint8_t time_9; /* t9 */
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} pio_timings[5] =
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{
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[0] = /* PIO mode 0 */
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{
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.time_1 = 70,
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.time_2w = 290,
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.time_2r = 290,
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.time_4 = 30,
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.time_9 = 20
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},
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[1] = /* PIO mode 1 */
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{
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.time_1 = 50,
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.time_2w = 290,
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.time_2r = 290,
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.time_4 = 20,
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.time_9 = 15
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},
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[2] = /* PIO mode 2 */
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{
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.time_1 = 30,
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.time_2w = 290,
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.time_2r = 290,
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.time_4 = 15,
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.time_9 = 10
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},
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[3] = /* PIO mode 3 */
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{
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.time_1 = 30,
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.time_2w = 80,
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.time_2r = 80,
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.time_4 = 10,
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.time_9 = 10
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},
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[4] = /* PIO mode 4 */
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{
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.time_1 = 25,
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.time_2w = 70,
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.time_2r = 70,
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.time_4 = 10,
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.time_9 = 10
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},
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};
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/* Setup the timing for PIO mode */
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static void ata_set_pio_mode(int mode)
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{
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const struct ata_pio_timings * const timings = &pio_timings[mode];
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/* T = period in nanoseconds */
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int T = 1000 * 1000 * 1000 / imx31_clkctl_get_ata_clk();
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while (!(ATA_INTERRUPT_PENDING & ATA_CONTROLLER_IDLE));
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ATA_TIME_OFF = 3;
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ATA_TIME_ON = 3;
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ATA_TIME_1 = (timings->time_1 + T) / T;
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ATA_TIME_2W = (timings->time_2w + T) / T;
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ATA_TIME_2R = (timings->time_2r + T) / T;
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ATA_TIME_AX = (35 + T) / T; /* tA */
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ATA_TIME_PIO_RDX = 1;
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ATA_TIME_4 = (timings->time_4 + T) / T;
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ATA_TIME_9 = (timings->time_9 + T) / T;
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}
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void ata_reset(void)
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{
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@ -47,92 +121,35 @@ bool ata_is_coldstart(void)
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return true;
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}
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unsigned long get_pll(bool serial) {
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unsigned long mfi, mfn, mfd, pdf, ref_clk;
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unsigned long reg = 0, ccmr;
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unsigned long long temp;
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unsigned int prcs;
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ccmr = CLKCTL_CCMR;
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prcs = (ccmr & 0x6) >> 1;
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if(prcs == 0x1) {
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ref_clk = 32768 * 1024;
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} else {
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ref_clk = 27000000;
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}
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if(serial) {
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reg = CLKCTL_SPCTL;
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} else {
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if((ccmr & 0x8) == 0)
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return ref_clk;
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if((ccmr & 0x80) != 0)
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return ref_clk;
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reg = CLKCTL_MPCTL;
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}
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pdf = (reg & (0x7 << 26)) >> 26;
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mfd = (reg & (0x3FF << 16)) >> 16;
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mfi = (reg & (0xF << 10)) >> 10;
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mfi = (mfi <= 5) ? 5 : mfi;
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mfn = (reg & 0x3FF);
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if(mfn < 0x200) {
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temp = (unsigned long long)2 *ref_clk * mfn;
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temp /= (mfd + 1);
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temp = (unsigned long long)2 *ref_clk * mfi + temp;
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temp /= (pdf + 1);
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} else {
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temp = (unsigned long long)2 *ref_clk * (0x400 - mfn);
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temp /= (mfd + 1);
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temp = (unsigned long long)2 *ref_clk * mfi - temp;
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temp /= (pdf + 1);
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}
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return (unsigned long)temp;
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}
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unsigned long get_ata_clock(void) {
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unsigned long pll, ret_val, hclk, max_pdf, ipg_pdf, mcu_pdf;
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max_pdf = (CLKCTL_PDR0 & (0x7 << 3)) >> 3;
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ipg_pdf = (CLKCTL_PDR0 & (0x3 << 6)) >> 6;
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mcu_pdf = (CLKCTL_PDR0 & 0x7);
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if((CLKCTL_PMCR0 & 0xC0000000 ) == 0) {
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pll = get_pll(true);
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} else {
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pll = get_pll(false);
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}
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hclk = pll/(max_pdf + 1);
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ret_val = hclk / (ipg_pdf + 1);
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return ret_val;
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}
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void ata_device_init(void)
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{
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ATA_INTF_CONTROL |= ATA_ATA_RST; /* Make sure we're not in reset mode */
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while (!(ATA_INTERRUPT_PENDING & ATA_CONTROLLER_IDLE));
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/* Setup the timing for PIO mode */
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int T = 1000 * 1000 * 1000 / get_ata_clock();
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ATA_TIME_OFF = 3;
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ATA_TIME_ON = 3;
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ATA_TIME_1 = (T + 70)/T;
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ATA_TIME_2W = (T + 290)/T;
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ATA_TIME_2R = (T + 290)/T;
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ATA_TIME_AX = (T + 50)/T;
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ATA_TIME_PIO_RDX = 1;
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ATA_TIME_4 = (T + 30)/T;
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ATA_TIME_9 = (T + 20)/T;
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/* Setup mode 0 by default */
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ata_set_pio_mode(0);
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}
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#if 0
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#if !defined(BOOTLOADER)
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void copy_write_sectors(const unsigned char* buf, int wordcount)
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void ata_identify_ready(void)
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{
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(void)buf; (void)wordcount;
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const unsigned short* identify_info = ata_get_identify();
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int mode = 0;
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if (identify_info[53] & (1 << 1))
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{
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/* Set up advanced timings */
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if (identify_info[64] & (1 << 1))
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mode = 4; /* Mode 0, 1, 2, 3, 4 */
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else if (identify_info[64] & (1 << 0))
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mode = 3; /* Mode 0, 1, 2, 3 */
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else
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mode = 2; /* Mode 0, 1, 2 */
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}
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/* If mode changed, actually set the timings */
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if (mode != 0)
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{
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ata_set_pio_mode(mode);
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}
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}
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#endif
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#endif
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@ -68,4 +68,7 @@ void ata_reset(void);
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void ata_device_init(void);
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bool ata_is_coldstart(void);
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#define ATA_NOTIFY_IDENTIFY_READY
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void ata_identify_ready(void);
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#endif
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@ -43,3 +43,43 @@ void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg,
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restore_interrupt(oldlevel);
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}
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/* Get the PLL reference clock frequency in HZ */
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unsigned int imx31_clkctl_get_pll_ref_clk(void)
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{
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if ((CLKCTL_CCMR & (3 << 1)) == (1 << 1))
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return CONFIG_CLK32_FREQ * 1024;
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else
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return CONFIG_HCLK_FREQ;
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}
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/* Return PLL frequency in HZ */
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unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll)
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{
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uint32_t infreq = imx31_clkctl_get_pll_ref_clk();
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uint32_t reg = (&CLKCTL_MPCTL)[pll];
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uint32_t mfn = reg & 0x3ff;
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uint32_t pd = ((reg >> 26) & 0xf) + 1;
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uint64_t mfd = ((reg >> 16) & 0x3ff) + 1;
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uint32_t mfi = (reg >> 10) & 0xf;
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mfi = mfi <= 5 ? 5 : mfi;
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return 2*infreq*(mfi * mfd + mfn) / (mfd * pd);
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}
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unsigned int imx31_clkctl_get_ipg_clk(void)
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{
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unsigned int pll = imx31_clkctl_get_pll((CLKCTL_PMCR0 & 0xC0000000) == 0 ?
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PLL_SERIAL : PLL_MCU);
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uint32_t reg = CLKCTL_PDR0;
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unsigned int max_pdf = ((reg >> 3) & 0x7) + 1;
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unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1;
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return pll / (max_pdf * ipg_pdf);
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}
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unsigned int imx31_clkctl_get_ata_clk(void)
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{
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return imx31_clkctl_get_ipg_clk();
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}
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@ -83,4 +83,27 @@ enum IMX31_CG_MODES
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void imx31_clkctl_module_clock_gating(enum IMX31_CG_LIST cg,
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enum IMX31_CG_MODES mode);
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enum IMX31_PLLS
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{
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PLL_MCU = 0,
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PLL_USB,
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PLL_SERIAL,
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NUM_PLLS,
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};
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#define CONFIG_CLK32_FREQ 32768
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#define CONFIG_HCLK_FREQ 27000000
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/* Get the PLL reference clock frequency in HZ */
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unsigned int imx31_clkctl_get_pll_ref_clk(void);
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/* Return PLL frequency in HZ */
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unsigned int imx31_clkctl_get_pll(enum IMX31_PLLS pll);
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/* Return ipg_clk in HZ */
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unsigned int imx31_clkctl_get_ipg_clk(void);
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/* Return the ATA frequency in HZ */
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unsigned int imx31_clkctl_get_ata_clk(void);
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#endif /* _CLKCTL_IMX31_H_ */
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