forked from len0rd/rockbox
Bring the IMX31 serial driver in line with the CONTRIBUTING guidelines.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16352 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Will Robertson
parent
ed4a635058
commit
bc4621499a
3 changed files with 123 additions and 104 deletions
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@ -174,36 +174,38 @@ void serial_setup (void)
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void serial_setup(void)
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void serial_setup(void)
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{
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{
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#ifdef UART_INT /*enable UART Interrupts */
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#ifdef UART_INT /*enable UART Interrupts */
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UCR1_1 |= (EUartUCR1_TRDYEN | EUartUCR1_RRDYEN | EUartUCR1_TXMPTYEN);
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UCR1_1 |= (EUARTUCR1_TRDYEN | EUaRTUCR1_RRDYEN | EUARTUCR1_TXMPTYEN);
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UCR4_1 |= (EUartUCR4_TCEN);
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UCR4_1 |= (EUARTUCR4_TCEN);
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#else /*disable UART Interrupts*/
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#else /*disable UART Interrupts*/
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UCR1_1 &= ~(EUartUCR1_TRDYEN | EUartUCR1_RRDYEN | EUartUCR1_TXMPTYEN);
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UCR1_1 &= ~(EUARTUCR1_TRDYEN | EUARTUCR1_RRDYEN | EUARTUCR1_TXMPTYEN);
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UCR4_1 &= ~(EUartUCR4_TCEN);
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UCR4_1 &= ~(EUARTUCR4_TCEN);
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#endif
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#endif
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UCR1_1 |= EUartUCR1_UARTEN;
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UCR1_1 |= EUARTUCR1_UARTEN;
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UCR2_1 |= (EUartUCR2_TXEN | EUartUCR2_RXEN | EUartUCR2_IRTS);
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UCR2_1 |= (EUARTUCR2_TXEN | EUARTUCR2_RXEN | EUARTUCR2_IRTS);
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/* Tx,Rx Interrupt Trigger levels, Disable for now*/
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/* Tx,Rx Interrupt Trigger levels, Disable for now*/
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/*UFCR1 |= (UFCR1_TXTL_32 | UFCR1_RXTL_32);*/
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/*UFCR1 |= (UFCR1_TXTL_32 | UFCR1_RXTL_32);*/
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}
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}
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int Tx_Rdy(void)
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int tx_rdy(void)
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{
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{
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if((UTS1 & EUartUTS_TXEMPTY))
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if((UTS1 & EUARTUTS_TXEMPTY))
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return 1;
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return 1;
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else return 0;
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else
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return 0;
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}
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}
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/*Not ready...After first Rx, UTS1 & UTS1_RXEMPTY
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/*Not ready...After first Rx, UTS1 & UTS1_RXEMPTY
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keeps returning true*/
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keeps returning true*/
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int Rx_Rdy(void)
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int rx_rdy(void)
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{
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{
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if(!(UTS1 & EUartUTS_RXEMPTY))
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if(!(UTS1 & EUARTUTS_RXEMPTY))
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return 1;
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return 1;
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else return 0;
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else
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return 0;
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}
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}
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void Tx_Writec(char c)
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void tx_writec(char c)
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{
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{
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UTXD1=(int) c;
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UTXD1=(int) c;
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}
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}
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@ -227,12 +229,12 @@ void serial_tx(const unsigned char * buf)
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{
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{
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/*Tx*/
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/*Tx*/
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for(;;) {
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for(;;) {
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if(Tx_Rdy()) {
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if(tx_rdy()) {
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if(*buf == '\0')
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if(*buf == '\0')
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return;
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return;
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if(*buf == '\n')
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if(*buf == '\n')
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Tx_Writec('\r');
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tx_writec('\r');
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Tx_Writec(*buf);
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tx_writec(*buf);
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buf++;
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buf++;
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}
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}
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}
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}
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@ -682,92 +682,90 @@
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/*
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/*
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* UART Control Register 0 Bit Fields.
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* UART Control Register 0 Bit Fields.
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*/
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*/
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#define EUartUCR1_ADEN (1 << 15) // Auto detect interrupt
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#define EUARTUCR1_ADEN (1 << 15) // Auto detect interrupt
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#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
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#define EUARTUCR1_ADBR (1 << 14) // Auto detect baud rate
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#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
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#define EUARTUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
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#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
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#define EUARTUCR1_IDEN (1 << 12) // Idle condition interrupt
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#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
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#define EUARTUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
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#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
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#define EUARTUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
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#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
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#define EUARTUCR1_IREN (1 << 7) // Infrared interface enable
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#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable
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#define EUARTUCR1_TXMPTYEN (1 << 6) // Transimitter empt interrupt enable
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#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
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#define EUARTUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
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#define EUartUCR1_SNDBRK (1 << 4) // Send break
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#define EUARTUCR1_SNDBRK (1 << 4) // Send break
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#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
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#define EUARTUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
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#define EUartUCR1_DOZE (1 << 1) // Doze
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#define EUARTUCR1_DOZE (1 << 1) // Doze
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#define EUartUCR1_UARTEN (1 << 0) // UART enabled
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#define EUARTUCR1_UARTEN (1 << 0) // UART enabled
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#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
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#define EUARTUCR2_ESCI (1 << 15) // Escape seq interrupt enable
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#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
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#define EUARTUCR2_IRTS (1 << 14) // Ignore RTS pin
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#define EUartUCR2_CTSC (1 << 13) // CTS pin control
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#define EUARTUCR2_CTSC (1 << 13) // CTS pin control
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#define EUartUCR2_CTS (1 << 12) // Clear to send
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#define EUARTUCR2_CTS (1 << 12) // Clear to send
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#define EUartUCR2_ESCEN (1 << 11) // Escape enable
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#define EUARTUCR2_ESCEN (1 << 11) // Escape enable
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#define EUartUCR2_PREN (1 << 8) // Parity enable
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#define EUARTUCR2_PREN (1 << 8) // Parity enable
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#define EUartUCR2_PROE (1 << 7) // Parity odd/even
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#define EUARTUCR2_PROE (1 << 7) // Parity odd/even
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#define EUartUCR2_STPB (1 << 6) // Stop
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#define EUARTUCR2_STPB (1 << 6) // Stop
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#define EUartUCR2_WS (1 << 5) // Word size
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#define EUARTUCR2_WS (1 << 5) // Word size
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#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
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#define EUARTUCR2_RTSEN (1 << 4) // Request to send interrupt enable
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#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
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#define EUARTUCR2_ATEN (1 << 3) // Aging timer enable
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#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
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#define EUARTUCR2_TXEN (1 << 2) // Transmitter enabled
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#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
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#define EUARTUCR2_RXEN (1 << 1) // Receiver enabled
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#define EUartUCR2_SRST_ (1 << 0) // SW reset
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#define EUARTUCR2_SRST_ (1 << 0) // SW reset
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#define EUartUCR3_PARERREN (1 << 12) // Parity enable
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#define EUARTUCR3_PARERREN (1 << 12) // Parity enable
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#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
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#define EUARTUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
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#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
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#define EUARTUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
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#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
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#define EUARTUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
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#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
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#define EUARTUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
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#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
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#define EUARTUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
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#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
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#define EUARTUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
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#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
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#define EUARTUCR3_INVT (1 << 1) // Inverted Infrared transmission
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#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
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#define EUARTUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
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#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
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#define EUARTUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
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#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
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#define EUARTUCR4_INVR (1 << 9) // Inverted infrared reception
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#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
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#define EUARTUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
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#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
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#define EUARTUCR4_WKEN (1 << 7) // Wake interrupt enable
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#define EUartUCR4_IRSC (1 << 5) // IR special case
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#define EUARTUCR4_IRSC (1 << 5) // IR special case
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#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
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#define EUARTUCR4_LPBYP (1 << 4) // Low power bypass
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#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
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#define EUARTUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
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#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
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#define EUARTUCR4_BKEN (1 << 2) // Break condition interrupt enable
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#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
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#define EUARTUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
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#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
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#define EUARTUCR4_DREN (1 << 0) // Recv data ready interrupt enable
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#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
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#define EUARTUFCR_RXTL_SHF 0 // Receiver trigger level shift
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#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1)
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#define EUARTUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div> 1)
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#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2)
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#define EUARTUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div> 2)
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#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
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#define EUARTUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
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#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
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#define EUARTUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
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#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
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#define EUARTUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
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#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
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#define EUARTUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
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#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
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#define EUARTUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
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#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
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#define EUARTUFCR_TXTL_SHF 10 // Transmitter trigger level shift
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#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
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#define EUARTUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
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#define EUartUSR1_RTSS (1 << 14) // RTS pin status
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#define EUARTUSR1_RTSS (1 << 14) // RTS pin status
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#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
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#define EUARTUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
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#define EUartUSR1_RTSD (1 << 12) // RTS delta
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#define EUARTUSR1_RTSD (1 << 12) // RTS delta
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#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
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#define EUARTUSR1_ESCF (1 << 11) // Escape seq interrupt flag
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#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
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#define EUARTUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
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#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
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#define EUARTUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
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#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
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#define EUARTUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
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#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
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#define EUARTUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
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#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
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#define EUARTUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
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#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
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#define EUARTUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
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#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
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#define EUARTUSR2_ADET (1 << 15) // Auto baud rate detect complete
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#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
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#define EUARTUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
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#define EUartUSR2_IDLE (1 << 12) // Idle condition
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#define EUARTUSR2_IDLE (1 << 12) // Idle condition
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#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
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#define EUARTUSR2_ACST (1 << 11) // Autobaud counter stopped
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#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
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#define EUARTUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
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#define EUartUSR2_WAKE (1 << 7) // Wake
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#define EUARTUSR2_WAKE (1 << 7) // Wake
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#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
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#define EUARTUSR2_RTSF (1 << 4) // RTS edge interrupt flag
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#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
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#define EUARTUSR2_TXDC (1 << 3) // Transmitter complete
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#define EUartUSR2_BRCD (1 << 2) // Break condition
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#define EUARTUSR2_BRCD (1 << 2) // Break condition
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#define EUartUSR2_ORE (1 << 1) // Overrun error
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#define EUARTUSR2_ORE (1 << 1) // Overrun error
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#define EUartUSR2_RDR (1 << 0) // Recv data ready
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#define EUARTUSR2_RDR (1 << 0) // Recv data ready
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#define EUartUTS_FRCPERR (1 << 13) // Force parity error
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#define EUARTUTS_FRCPERR (1 << 13) // Force parity error
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#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
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#define EUARTUTS_LOOP (1 << 12) // Loop tx and rx
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#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
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#define EUARTUTS_TXEMPTY (1 << 6) // TxFIFO empty
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#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
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#define EUARTUTS_RXEMPTY (1 << 5) // RxFIFO empty
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#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
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#define EUARTUTS_TXFULL (1 << 4) // TxFIFO full
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#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
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#define EUARTUTS_RXFULL (1 << 3) // RxFIFO full
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#define EUartUTS_SOFTRST (1 << 0) // Software reset
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#define EUARTUTS_SOFTRST (1 << 0) // Software reset
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#define DelayTimerPresVal 3
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#define L2CC_ENABLED
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#define L2CC_ENABLED
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@ -1,11 +1,30 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by James Espinoza
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SERIAL_IMX31_H
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#ifndef SERIAL_IMX31_H
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#define SERIAL_IMX31_H
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#define SERIAL_IMX31_H
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#include <stdarg.h>
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdio.h>
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int Tx_Rdy(void);
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int tx_rdy(void);
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void Tx_Writec(const char c);
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void tx_writec(const char c);
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void dprintf(const char * str, ... );
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void dprintf(const char * str, ... );
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#endif
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#endif
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