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Gigabeat S: Get boot to go a little father.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16245 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2008-02-08 06:34:11 +00:00
parent 2e3a8c776f
commit bc057f91b5
5 changed files with 116 additions and 63 deletions
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2
firmware/export/config-gigabeat-s.h
View file

@ -1,6 +1,8 @@
/* /*
* This config file is for toshiba Gigabeat S * This config file is for toshiba Gigabeat S
*/ */
#define NO_LOW_BATTERY_SHUTDOWN
#define TARGET_TREE /* this target is using the target tree system */ #define TARGET_TREE /* this target is using the target tree system */
#define TOSHIBA_GIGABEAT_S 1 #define TOSHIBA_GIGABEAT_S 1

77
firmware/export/imx31l.h
View file

@ -25,8 +25,6 @@
/* Place in the section with the framebuffer */ /* Place in the section with the framebuffer */
#define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE) #define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE)
#define IRAM_BASE_ADDR 0x1fffc000
#define L2CC_BASE_ADDR 0x30000000
/*Frame Buffer and TTB defines from gigabeat f/x build*/ /*Frame Buffer and TTB defines from gigabeat f/x build*/
#define FRAME ((short *)0x80100000) /* Framebuffer */ #define FRAME ((short *)0x80100000) /* Framebuffer */
@ -37,6 +35,8 @@
/* /*
* AIPS 1 * AIPS 1
*/ */
#define IRAM_BASE_ADDR 0x1fffc000
#define L2CC_BASE_ADDR 0x30000000
#define AIPS1_BASE_ADDR 0x43F00000 #define AIPS1_BASE_ADDR 0x43F00000
#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
#define MAX_BASE_ADDR 0x43F04000 #define MAX_BASE_ADDR 0x43F04000
@ -133,15 +133,70 @@
/* ATA */ /* ATA */
#define TIME_OFF (*(REG8_PTR_T)0x43F8C000) #define ATA_TIME_OFF (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00))
#define TIME_ON (*(REG8_PTR_T)0x43F8C001) #define ATA_TIME_ON (*(REG8_PTR_T)(ATA_BASE_ADDR+0x01))
#define TIME_1 (*(REG8_PTR_T)0x43F8C002) #define ATA_TIME_1 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x02))
#define TIME_2W (*(REG8_PTR_T)0x43F8C003) #define ATA_TIME_2W (*(REG8_PTR_T)(ATA_BASE_ADDR+0x03))
#define TIME_2R (*(REG8_PTR_T)0x43F8C004) /* PIO */
#define TIME_AX (*(REG8_PTR_T)0x43F8C005) #define ATA_TIME_2R (*(REG8_PTR_T)(ATA_BASE_ADDR+0x04))
#define TIME_PIO_RDX (*(REG8_PTR_T)0x43F8C00F) #define ATA_TIME_AX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x05))
#define TIME_4 (*(REG8_PTR_T)0x43F8C007) #define ATA_TIME_4 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x07))
#define TIME_9 (*(REG8_PTR_T)0x43F8C008) #define ATA_TIME_9 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x08))
/* MDMA */
#define ATA_TIME_M (*(REG8_PTR_T)(ATA_BASE_ADDR+0x09))
#define ATA_TIME_JN (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0A))
#define ATA_TIME_D (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0B))
#define ATA_TIME_K (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0C))
/* UDMA */
#define ATA_TIME_ACK (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0D))
#define ATA_TIME_ENV (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0E))
#define ATA_TIME_PIO_RDX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0F))
#define ATA_TIME_ZAH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x10))
#define ATA_TIME_MLIX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x11))
#define ATA_TIME_DVH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x12))
#define ATA_TIME_DZFS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x13))
#define ATA_TIME_DVS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x14))
#define ATA_TIME_CVS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x15))
#define ATA_TIME_SS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x16))
#define ATA_TIME_CYC (*(REG8_PTR_T)(ATA_BASE_ADDR+0x17))
/* */
#define ATA_FIFO_DATA_32 (*(REG32_PTR_T)(ATA_BASE_ADDR+0x18))
#define ATA_FIFO_DATA_16 (*(REG16_PTR_T)(ATA_BASE_ADDR+0x1c))
#define ATA_FIFO_FILL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x20))
/* Actually ATA_CONTROL but conflicts arise */
#define ATA_INTF_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x24))
#define ATA_INTERRUPT_PENDING (*(REG8_PTR_T)(ATA_BASE_ADDR+0x28))
#define ATA_INTERRUPT_ENABLE (*(REG8_PTR_T)(ATA_BASE_ADDR+0x2c))
#define ATA_INTERRUPT_CLEAR (*(REG8_PTR_T)(ATA_BASE_ADDR+0x30))
#define ATA_FIFO_ALARM (*(REG8_PTR_T)(ATA_BASE_ADDR+0x34))
#define ATA_DRIVE_DATA (*(REG16_PTR_T)(ATA_BASE_ADDR+0xA0))
#define ATA_DRIVE_FEATURES (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA4))
#define ATA_DRIVE_SECTOR_COUNT (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA8))
#define ATA_DRIVE_SECTOR_NUM (*(REG8_PTR_T)(ATA_BASE_ADDR+0xAC))
#define ATA_DRIVE_CYL_LOW (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB0))
#define ATA_DRIVE_CYL_HIGH (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB4))
#define ATA_DRIVE_CYL_HEAD (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB8))
#define ATA_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* rd */
#define ATA_DRIVE_COMMAND (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* wr */
#define ATA_ALT_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* rd */
#define ATA_DRIVE_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* wr */
/* ATA_INTF_CONTROL flags */
#define ATA_FIFO_RST (1 << 7)
#define ATA_ATA_RST (1 << 6)
#define ATA_FIFO_TX_EN (1 << 5)
#define ATA_FIFO_RCV_EN (1 << 4)
#define ATA_DMA_PENDING (1 << 3)
#define ATA_DMA_ULTRA_SELECTED (1 << 2)
#define ATA_DMA_WRITE (1 << 1)
#define ATA_IORDY_EN (1 << 0)
/* ATA_INTERRUPT_PENDING, ATA_INTERRUPT_ENABLE, ATA_INTERRUPT_CLEAR flags */
#define ATA_INTRQ1 (1 << 7)
#define ATA_FIFO_UNDERFLOW (1 << 6)
#define ATA_FIFO_OVERFLOW (1 << 5)
#define ATA_CONTROLLER_IDLE (1 << 4)
#define ATA_INTRQ2 (1 << 3)
/* Timers */ /* Timers */
#define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00)) #define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00))

37
firmware/target/arm/imx31/gigabeat-s/ata-imx31.c
View file

@ -26,14 +26,14 @@
#include "pcf50606.h" #include "pcf50606.h"
#include "ata-target.h" #include "ata-target.h"
#define ATA_RST (1 << 6)
void ata_reset(void) void ata_reset(void)
{ {
ATA_CONTROL &= ~ATA_RST; ATA_INTF_CONTROL &= ~ATA_ATA_RST;
sleep(1); sleep(1);
ATA_CONTROL |= ATA_RST; ATA_INTF_CONTROL |= ATA_ATA_RST;
sleep(1); sleep(1);
while (!(ATA_INTERRUPT_PENDING & ATA_CONTROLLER_IDLE));
} }
/* This function is called before enabling the USB bus */ /* This function is called before enabling the USB bus */
@ -44,7 +44,7 @@ void ata_enable(bool on)
bool ata_is_coldstart(void) bool ata_is_coldstart(void)
{ {
return 0; return true;
} }
unsigned long get_pll(bool serial) { unsigned long get_pll(bool serial) {
@ -110,26 +110,27 @@ unsigned long get_ata_clock(void) {
void ata_device_init(void) void ata_device_init(void)
{ {
ATA_CONTROL |= ATA_RST; /* Make sure we're not in reset mode */ ATA_INTF_CONTROL |= ATA_ATA_RST; /* Make sure we're not in reset mode */
while (!(ATA_INTERRUPT_PENDING & ATA_CONTROLLER_IDLE));
/* Setup the timing for PIO mode */ /* Setup the timing for PIO mode */
int T = 1000 * 1000 * 1000 / get_ata_clock(); int T = 1000 * 1000 * 1000 / get_ata_clock();
TIME_OFF = 3; ATA_TIME_OFF = 3;
TIME_ON = 3; ATA_TIME_ON = 3;
TIME_1 = (T + 70)/T; ATA_TIME_1 = (T + 70)/T;
TIME_2W = (T + 290)/T; ATA_TIME_2W = (T + 290)/T;
TIME_2R = (T + 290)/T; ATA_TIME_2R = (T + 290)/T;
TIME_AX = (T + 50)/T; ATA_TIME_AX = (T + 50)/T;
TIME_PIO_RDX = 1; ATA_TIME_PIO_RDX = 1;
TIME_4 = (T + 30)/T; ATA_TIME_4 = (T + 30)/T;
TIME_9 = (T + 20)/T; ATA_TIME_9 = (T + 20)/T;
} }
#if !defined(BOOTLOADER) #if !defined(BOOTLOADER)
void copy_read_sectors(unsigned char* buf, int wordcount) void copy_write_sectors(const unsigned char* buf, int wordcount)
{ {
(void)buf; (void)buf; (void)wordcount;
(void)wordcount;
} }
#endif #endif

23
firmware/target/arm/imx31/gigabeat-s/ata-target.h
View file

@ -23,20 +23,19 @@
#define PREFER_C_READING #define PREFER_C_READING
#define PREFER_C_WRITING #define PREFER_C_WRITING
#if !defined(BOOTLOADER) #if !defined(BOOTLOADER)
#define ATA_OPTIMIZED_READING #define ATA_OPTIMIZED_WRITING
void copy_read_sectors(unsigned char* buf, int wordcount); void copy_write_sectors(const unsigned char* buf, int wordcount);
#endif #endif
#define ATA_IOBASE 0x43F8C000 #define ATA_DATA ATA_DRIVE_DATA
#define ATA_DATA (*((volatile unsigned short*)(ATA_IOBASE + 0xA0))) #define ATA_ERROR ATA_DRIVE_FEATURES
#define ATA_ERROR (*((volatile unsigned char*)(ATA_IOBASE + 0xA4))) #define ATA_NSECTOR ATA_DRIVE_SECTOR_COUNT
#define ATA_NSECTOR (*((volatile unsigned char*)(ATA_IOBASE + 0xA8))) #define ATA_SECTOR ATA_DRIVE_SECTOR_NUM
#define ATA_SECTOR (*((volatile unsigned char*)(ATA_IOBASE + 0xAC))) #define ATA_LCYL ATA_DRIVE_CYL_LOW
#define ATA_LCYL (*((volatile unsigned char*)(ATA_IOBASE + 0xB0))) #define ATA_HCYL ATA_DRIVE_CYL_HIGH
#define ATA_HCYL (*((volatile unsigned char*)(ATA_IOBASE + 0xB4))) #define ATA_SELECT ATA_DRIVE_CYL_HEAD
#define ATA_SELECT (*((volatile unsigned char*)(ATA_IOBASE + 0xB8))) #define ATA_COMMAND ATA_DRIVE_COMMAND
#define ATA_COMMAND (*((volatile unsigned char*)(ATA_IOBASE + 0xBC))) #define ATA_CONTROL ATA_DRIVE_CONTROL
#define ATA_CONTROL (*((volatile unsigned char*)(ATA_IOBASE + 0xD8)))
#define STATUS_BSY 0x80 #define STATUS_BSY 0x80
#define STATUS_RDY 0x40 #define STATUS_RDY 0x40

14
firmware/target/arm/imx31/gigabeat-s/button-imx31.c
View file

@ -36,7 +36,7 @@ void button_init_device(void)
{ {
unsigned int reg_val; unsigned int reg_val;
/* Enable keypad clock */ /* Enable keypad clock */
//mxc_clks_enable(KPP_CLK); CLKCTL_CGR1 |= (3 << 2*10);
/* Enable number of rows in keypad (KPCR[7:0]) /* Enable number of rows in keypad (KPCR[7:0])
* Configure keypad columns as open-drain (KPCR[15:8]) * Configure keypad columns as open-drain (KPCR[15:8])
@ -45,11 +45,8 @@ void button_init_device(void)
* LSB nibble in KPP is for 8 rows * LSB nibble in KPP is for 8 rows
* MSB nibble in KPP is for 8 cols * MSB nibble in KPP is for 8 cols
*/ */
reg_val = KPP_KPCR; #if 0
reg_val |= (1 << 8) - 1; /* LSB */ KPP_KPCR = (0xff << 8) | 0xff;
reg_val |= ((1 << 8) - 1) << 8; /* MSB */
KPP_KPCR = reg_val;
/* Write 0's to KPDR[15:8] */ /* Write 0's to KPDR[15:8] */
reg_val = KPP_KPDR; reg_val = KPP_KPDR;
reg_val &= 0x00ff; reg_val &= 0x00ff;
@ -57,10 +54,9 @@ void button_init_device(void)
/* Configure columns as output, rows as input (KDDR[15:0]) */ /* Configure columns as output, rows as input (KDDR[15:0]) */
KPP_KDDR = 0xff00; KPP_KDDR = 0xff00;
#endif
reg_val = 0xD; KPP_KPSR = (1 << 3) | (1 << 2);
reg_val |= (1 << 8);
KPP_KPSR = reg_val;
} }
inline bool button_hold(void) inline bool button_hold(void)