forked from len0rd/rockbox
Gigabeat S: Get boot to go a little father.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16245 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
2e3a8c776f
commit
bc057f91b5
5 changed files with 116 additions and 63 deletions
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@ -1,6 +1,8 @@
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/*
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* This config file is for toshiba Gigabeat S
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*/
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#define NO_LOW_BATTERY_SHUTDOWN
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#define TARGET_TREE /* this target is using the target tree system */
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#define TOSHIBA_GIGABEAT_S 1
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@ -25,8 +25,6 @@
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/* Place in the section with the framebuffer */
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#define TTB_BASE_ADDR (0x80100000 + 0x00100000 - TTB_SIZE)
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#define IRAM_BASE_ADDR 0x1fffc000
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#define L2CC_BASE_ADDR 0x30000000
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/*Frame Buffer and TTB defines from gigabeat f/x build*/
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#define FRAME ((short *)0x80100000) /* Framebuffer */
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@ -37,6 +35,8 @@
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/*
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* AIPS 1
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*/
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#define IRAM_BASE_ADDR 0x1fffc000
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#define L2CC_BASE_ADDR 0x30000000
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#define AIPS1_BASE_ADDR 0x43F00000
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#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
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#define MAX_BASE_ADDR 0x43F04000
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@ -133,15 +133,70 @@
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/* ATA */
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#define TIME_OFF (*(REG8_PTR_T)0x43F8C000)
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#define TIME_ON (*(REG8_PTR_T)0x43F8C001)
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#define TIME_1 (*(REG8_PTR_T)0x43F8C002)
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#define TIME_2W (*(REG8_PTR_T)0x43F8C003)
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#define TIME_2R (*(REG8_PTR_T)0x43F8C004)
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#define TIME_AX (*(REG8_PTR_T)0x43F8C005)
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#define TIME_PIO_RDX (*(REG8_PTR_T)0x43F8C00F)
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#define TIME_4 (*(REG8_PTR_T)0x43F8C007)
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#define TIME_9 (*(REG8_PTR_T)0x43F8C008)
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#define ATA_TIME_OFF (*(REG8_PTR_T)(ATA_BASE_ADDR+0x00))
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#define ATA_TIME_ON (*(REG8_PTR_T)(ATA_BASE_ADDR+0x01))
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#define ATA_TIME_1 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x02))
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#define ATA_TIME_2W (*(REG8_PTR_T)(ATA_BASE_ADDR+0x03))
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/* PIO */
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#define ATA_TIME_2R (*(REG8_PTR_T)(ATA_BASE_ADDR+0x04))
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#define ATA_TIME_AX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x05))
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#define ATA_TIME_4 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x07))
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#define ATA_TIME_9 (*(REG8_PTR_T)(ATA_BASE_ADDR+0x08))
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/* MDMA */
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#define ATA_TIME_M (*(REG8_PTR_T)(ATA_BASE_ADDR+0x09))
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#define ATA_TIME_JN (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0A))
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#define ATA_TIME_D (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0B))
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#define ATA_TIME_K (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0C))
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/* UDMA */
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#define ATA_TIME_ACK (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0D))
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#define ATA_TIME_ENV (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0E))
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#define ATA_TIME_PIO_RDX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x0F))
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#define ATA_TIME_ZAH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x10))
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#define ATA_TIME_MLIX (*(REG8_PTR_T)(ATA_BASE_ADDR+0x11))
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#define ATA_TIME_DVH (*(REG8_PTR_T)(ATA_BASE_ADDR+0x12))
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#define ATA_TIME_DZFS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x13))
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#define ATA_TIME_DVS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x14))
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#define ATA_TIME_CVS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x15))
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#define ATA_TIME_SS (*(REG8_PTR_T)(ATA_BASE_ADDR+0x16))
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#define ATA_TIME_CYC (*(REG8_PTR_T)(ATA_BASE_ADDR+0x17))
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/* */
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#define ATA_FIFO_DATA_32 (*(REG32_PTR_T)(ATA_BASE_ADDR+0x18))
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#define ATA_FIFO_DATA_16 (*(REG16_PTR_T)(ATA_BASE_ADDR+0x1c))
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#define ATA_FIFO_FILL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x20))
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/* Actually ATA_CONTROL but conflicts arise */
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#define ATA_INTF_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0x24))
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#define ATA_INTERRUPT_PENDING (*(REG8_PTR_T)(ATA_BASE_ADDR+0x28))
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#define ATA_INTERRUPT_ENABLE (*(REG8_PTR_T)(ATA_BASE_ADDR+0x2c))
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#define ATA_INTERRUPT_CLEAR (*(REG8_PTR_T)(ATA_BASE_ADDR+0x30))
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#define ATA_FIFO_ALARM (*(REG8_PTR_T)(ATA_BASE_ADDR+0x34))
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#define ATA_DRIVE_DATA (*(REG16_PTR_T)(ATA_BASE_ADDR+0xA0))
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#define ATA_DRIVE_FEATURES (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA4))
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#define ATA_DRIVE_SECTOR_COUNT (*(REG8_PTR_T)(ATA_BASE_ADDR+0xA8))
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#define ATA_DRIVE_SECTOR_NUM (*(REG8_PTR_T)(ATA_BASE_ADDR+0xAC))
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#define ATA_DRIVE_CYL_LOW (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB0))
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#define ATA_DRIVE_CYL_HIGH (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB4))
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#define ATA_DRIVE_CYL_HEAD (*(REG8_PTR_T)(ATA_BASE_ADDR+0xB8))
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#define ATA_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* rd */
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#define ATA_DRIVE_COMMAND (*(REG8_PTR_T)(ATA_BASE_ADDR+0xBC)) /* wr */
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#define ATA_ALT_DRIVE_STATUS (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* rd */
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#define ATA_DRIVE_CONTROL (*(REG8_PTR_T)(ATA_BASE_ADDR+0xD8)) /* wr */
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/* ATA_INTF_CONTROL flags */
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#define ATA_FIFO_RST (1 << 7)
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#define ATA_ATA_RST (1 << 6)
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#define ATA_FIFO_TX_EN (1 << 5)
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#define ATA_FIFO_RCV_EN (1 << 4)
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#define ATA_DMA_PENDING (1 << 3)
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#define ATA_DMA_ULTRA_SELECTED (1 << 2)
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#define ATA_DMA_WRITE (1 << 1)
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#define ATA_IORDY_EN (1 << 0)
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/* ATA_INTERRUPT_PENDING, ATA_INTERRUPT_ENABLE, ATA_INTERRUPT_CLEAR flags */
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#define ATA_INTRQ1 (1 << 7)
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#define ATA_FIFO_UNDERFLOW (1 << 6)
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#define ATA_FIFO_OVERFLOW (1 << 5)
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#define ATA_CONTROLLER_IDLE (1 << 4)
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#define ATA_INTRQ2 (1 << 3)
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/* Timers */
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#define EPITCR1 (*(REG32_PTR_T)(EPIT1_BASE_ADDR+0x00))
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@ -26,14 +26,14 @@
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#include "pcf50606.h"
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#include "ata-target.h"
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#define ATA_RST (1 << 6)
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void ata_reset(void)
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{
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ATA_CONTROL &= ~ATA_RST;
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ATA_INTF_CONTROL &= ~ATA_ATA_RST;
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sleep(1);
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ATA_CONTROL |= ATA_RST;
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ATA_INTF_CONTROL |= ATA_ATA_RST;
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sleep(1);
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while (!(ATA_INTERRUPT_PENDING & ATA_CONTROLLER_IDLE));
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}
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/* This function is called before enabling the USB bus */
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@ -44,7 +44,7 @@ void ata_enable(bool on)
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bool ata_is_coldstart(void)
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{
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return 0;
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return true;
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}
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unsigned long get_pll(bool serial) {
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@ -110,26 +110,27 @@ unsigned long get_ata_clock(void) {
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void ata_device_init(void)
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{
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ATA_CONTROL |= ATA_RST; /* Make sure we're not in reset mode */
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ATA_INTF_CONTROL |= ATA_ATA_RST; /* Make sure we're not in reset mode */
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while (!(ATA_INTERRUPT_PENDING & ATA_CONTROLLER_IDLE));
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/* Setup the timing for PIO mode */
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int T = 1000 * 1000 * 1000 / get_ata_clock();
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TIME_OFF = 3;
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TIME_ON = 3;
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ATA_TIME_OFF = 3;
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ATA_TIME_ON = 3;
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TIME_1 = (T + 70)/T;
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TIME_2W = (T + 290)/T;
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TIME_2R = (T + 290)/T;
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TIME_AX = (T + 50)/T;
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TIME_PIO_RDX = 1;
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TIME_4 = (T + 30)/T;
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TIME_9 = (T + 20)/T;
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ATA_TIME_1 = (T + 70)/T;
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ATA_TIME_2W = (T + 290)/T;
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ATA_TIME_2R = (T + 290)/T;
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ATA_TIME_AX = (T + 50)/T;
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ATA_TIME_PIO_RDX = 1;
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ATA_TIME_4 = (T + 30)/T;
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ATA_TIME_9 = (T + 20)/T;
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}
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#if !defined(BOOTLOADER)
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void copy_read_sectors(unsigned char* buf, int wordcount)
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void copy_write_sectors(const unsigned char* buf, int wordcount)
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{
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(void)buf;
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(void)wordcount;
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(void)buf; (void)wordcount;
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}
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#endif
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@ -23,20 +23,19 @@
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#define PREFER_C_READING
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#define PREFER_C_WRITING
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#if !defined(BOOTLOADER)
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#define ATA_OPTIMIZED_READING
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void copy_read_sectors(unsigned char* buf, int wordcount);
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#define ATA_OPTIMIZED_WRITING
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void copy_write_sectors(const unsigned char* buf, int wordcount);
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#endif
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#define ATA_IOBASE 0x43F8C000
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#define ATA_DATA (*((volatile unsigned short*)(ATA_IOBASE + 0xA0)))
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#define ATA_ERROR (*((volatile unsigned char*)(ATA_IOBASE + 0xA4)))
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#define ATA_NSECTOR (*((volatile unsigned char*)(ATA_IOBASE + 0xA8)))
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#define ATA_SECTOR (*((volatile unsigned char*)(ATA_IOBASE + 0xAC)))
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#define ATA_LCYL (*((volatile unsigned char*)(ATA_IOBASE + 0xB0)))
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#define ATA_HCYL (*((volatile unsigned char*)(ATA_IOBASE + 0xB4)))
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#define ATA_SELECT (*((volatile unsigned char*)(ATA_IOBASE + 0xB8)))
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#define ATA_COMMAND (*((volatile unsigned char*)(ATA_IOBASE + 0xBC)))
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#define ATA_CONTROL (*((volatile unsigned char*)(ATA_IOBASE + 0xD8)))
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#define ATA_DATA ATA_DRIVE_DATA
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#define ATA_ERROR ATA_DRIVE_FEATURES
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#define ATA_NSECTOR ATA_DRIVE_SECTOR_COUNT
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#define ATA_SECTOR ATA_DRIVE_SECTOR_NUM
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#define ATA_LCYL ATA_DRIVE_CYL_LOW
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#define ATA_HCYL ATA_DRIVE_CYL_HIGH
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#define ATA_SELECT ATA_DRIVE_CYL_HEAD
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#define ATA_COMMAND ATA_DRIVE_COMMAND
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#define ATA_CONTROL ATA_DRIVE_CONTROL
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#define STATUS_BSY 0x80
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#define STATUS_RDY 0x40
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@ -36,31 +36,27 @@ void button_init_device(void)
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{
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unsigned int reg_val;
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/* Enable keypad clock */
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//mxc_clks_enable(KPP_CLK);
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CLKCTL_CGR1 |= (3 << 2*10);
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/* Enable number of rows in keypad (KPCR[7:0])
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* Configure keypad columns as open-drain (KPCR[15:8])
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*
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* Configure the rows/cols in KPP
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* LSB nibble in KPP is for 8 rows
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* MSB nibble in KPP is for 8 cols
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*/
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reg_val = KPP_KPCR;
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reg_val |= (1 << 8) - 1; /* LSB */
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reg_val |= ((1 << 8) - 1) << 8; /* MSB */
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KPP_KPCR = reg_val;
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/* Enable number of rows in keypad (KPCR[7:0])
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* Configure keypad columns as open-drain (KPCR[15:8])
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*
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* Configure the rows/cols in KPP
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* LSB nibble in KPP is for 8 rows
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* MSB nibble in KPP is for 8 cols
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*/
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#if 0
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KPP_KPCR = (0xff << 8) | 0xff;
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/* Write 0's to KPDR[15:8] */
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reg_val = KPP_KPDR;
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reg_val &= 0x00ff;
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KPP_KPDR = reg_val;
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/* Write 0's to KPDR[15:8] */
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reg_val = KPP_KPDR;
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reg_val &= 0x00ff;
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KPP_KPDR = reg_val;
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/* Configure columns as output, rows as input (KDDR[15:0]) */
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KPP_KDDR = 0xff00;
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#endif
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/* Configure columns as output, rows as input (KDDR[15:0]) */
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KPP_KDDR = 0xff00;
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reg_val = 0xD;
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reg_val |= (1 << 8);
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KPP_KPSR = reg_val;
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KPP_KPSR = (1 << 3) | (1 << 2);
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}
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inline bool button_hold(void)
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