forked from len0rd/rockbox
Use LTV350QV register definitions
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17452 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere
parent
572e7a9659
commit
ba3cfca6dd
2 changed files with 165 additions and 54 deletions
113
firmware/export/ltv350qv.h
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113
firmware/export/ltv350qv.h
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@ -0,0 +1,113 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/*
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* Register definitions for Samsung LTV350QV Quarter VGA LCD Panel
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*
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* Copyright (C) 2006, 2007 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __LTV350QV_H
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#define __LTV350QV_H
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#define LTV_OPC_INDEX 0x74
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#define LTV_OPC_DATA 0x76
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#define LTV_ID 0x00 /* ID Read */
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#define LTV_IFCTL 0x01 /* Display Interface Control */
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#define LTV_DATACTL 0x02 /* Display Data Control */
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#define LTV_ENTRY_MODE 0x03 /* Entry Mode */
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#define LTV_GATECTL1 0x04 /* Gate Control 1 */
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#define LTV_GATECTL2 0x05 /* Gate Control 2 */
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#define LTV_VBP 0x06 /* Vertical Back Porch */
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#define LTV_HBP 0x07 /* Horizontal Back Porch */
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#define LTV_SOTCTL 0x08 /* Source Output Timing Control */
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#define LTV_PWRCTL1 0x09 /* Power Control 1 */
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#define LTV_PWRCTL2 0x0a /* Power Control 2 */
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#define LTV_GAMMA(x) (0x10 + (x))/* Gamma control */
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/* Bit definitions for LTV_IFCTL */
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#define LTV_IM (1 << 15)
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#define LTV_NMD (1 << 14)
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#define LTV_SSMD (1 << 13)
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#define LTV_REV (1 << 7)
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#define LTV_NL(x) (((x) & 0x001f) << 0)
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/* Bit definitions for LTV_DATACTL */
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#define LTV_DS_SAME (0 << 12)
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#define LTV_DS_D_TO_S (1 << 12)
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#define LTV_DS_S_TO_D (2 << 12)
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#define LTV_CHS_384 (0 << 9)
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#define LTV_CHS_480 (1 << 9)
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#define LTV_CHS_492 (2 << 9)
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#define LTV_DF_RGB (0 << 6)
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#define LTV_DF_RGBX (1 << 6)
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#define LTV_DF_XRGB (2 << 6)
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#define LTV_RGB_RGB (0 << 2)
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#define LTV_RGB_BGR (1 << 2)
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#define LTV_RGB_GRB (2 << 2)
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#define LTV_RGB_RBG (3 << 2)
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/* Bit definitions for LTV_ENTRY_MODE */
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#define LTV_VSPL_ACTIVE_LOW (0 << 15)
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#define LTV_VSPL_ACTIVE_HIGH (1 << 15)
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#define LTV_HSPL_ACTIVE_LOW (0 << 14)
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#define LTV_HSPL_ACTIVE_HIGH (1 << 14)
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#define LTV_DPL_SAMPLE_RISING (0 << 13)
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#define LTV_DPL_SAMPLE_FALLING (1 << 13)
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#define LTV_EPL_ACTIVE_LOW (0 << 12)
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#define LTV_EPL_ACTIVE_HIGH (1 << 12)
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#define LTV_SS_LEFT_TO_RIGHT (0 << 8)
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#define LTV_SS_RIGHT_TO_LEFT (1 << 8)
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#define LTV_STB (1 << 1)
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/* Bit definitions for LTV_GATECTL1 */
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#define LTV_CLW(x) (((x) & 0x0007) << 12)
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#define LTV_GAON (1 << 5)
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#define LTV_SDR (1 << 3)
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/* Bit definitions for LTV_GATECTL2 */
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#define LTV_NW_INV_FRAME (0 << 14)
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#define LTV_NW_INV_1LINE (1 << 14)
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#define LTV_NW_INV_2LINE (2 << 14)
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#define LTV_DSC (1 << 12)
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#define LTV_GIF (1 << 8)
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#define LTV_FHN (1 << 7)
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#define LTV_FTI(x) (((x) & 0x0003) << 4)
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#define LTV_FWI(x) (((x) & 0x0003) << 0)
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/* Bit definitions for LTV_SOTCTL */
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#define LTV_SDT(x) (((x) & 0x0007) << 10)
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#define LTV_EQ(x) (((x) & 0x0007) << 2)
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/* Bit definitions for LTV_PWRCTL1 */
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#define LTV_VCOM_DISABLE (1 << 14)
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#define LTV_VCOMOUT_ENABLE (1 << 11)
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#define LTV_POWER_ON (1 << 9)
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#define LTV_DRIVE_CURRENT(x) (((x) & 0x0007) << 4) /* 0=off, 5=max */
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#define LTV_SUPPLY_CURRENT(x) (((x) & 0x0007) << 0) /* 0=off, 5=max */
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/* Bit definitions for LTV_PWRCTL2 */
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#define LTV_VCOML_ENABLE (1 << 13)
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#define LTV_VCOML_VOLTAGE(x) (((x) & 0x001f) << 8) /* 0=1V, 31=-1V */
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#define LTV_VCOMH_VOLTAGE(x) (((x) & 0x001f) << 0) /* 0=3V, 31=4.5V */
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#endif /* __LTV350QV_H */
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@ -27,6 +27,7 @@
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#include "spi.h"
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#include "spi.h"
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#include "spi-target.h"
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#include "spi-target.h"
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#include "lcd-target.h"
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#include "lcd-target.h"
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#include "ltv350qv.h"
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/* Power and display status */
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/* Power and display status */
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static bool display_on = false; /* Is the display turned on? */
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static bool display_on = false; /* Is the display turned on? */
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@ -85,13 +86,10 @@ static void enable_venc(bool enable)
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/* LTV250QV panel functions */
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/* LTV250QV panel functions */
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static void lcd_write_reg(unsigned char reg, unsigned short val)
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static void lcd_write_reg(unsigned char reg, unsigned short val)
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{
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{
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unsigned char block[3];
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unsigned char block[3] = {LTV_OPC_INDEX, 0, reg | 0xFF};
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block[0] = 0x74;
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block[1] = 0;
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block[2] = reg | 0xFF;
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spi_block_transfer(SPI_target_LTV250QV, block, sizeof(block), NULL, 0);
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spi_block_transfer(SPI_target_LTV250QV, block, sizeof(block), NULL, 0);
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block[0] = 0x76;
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block[0] = LTV_OPC_DATA;
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block[1] = (val >> 8) & 0xFF;
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block[1] = val >> 8;
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block[2] = val & 0xFF;
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block[2] = val & 0xFF;
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spi_block_transfer(SPI_target_LTV250QV, block, sizeof(block), NULL, 0);
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spi_block_transfer(SPI_target_LTV250QV, block, sizeof(block), NULL, 0);
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}
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}
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@ -128,57 +126,57 @@ static void lcd_display_on(bool reset)
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IO_GIO_BITSET2 = (1 << 8);
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IO_GIO_BITSET2 = (1 << 8);
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sleep_ms(1);
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sleep_ms(1);
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lcd_write_reg(1, 0x1D);
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lcd_write_reg(LTV_IFCTL, LTV_NL(29));
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lcd_write_reg(2, 0x0);
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lcd_write_reg(LTV_DATACTL, 0);
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lcd_write_reg(3, 0x0);
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lcd_write_reg(LTV_ENTRY_MODE,0);
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lcd_write_reg(4, 0x0);
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lcd_write_reg(LTV_GATECTL1, 0);
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lcd_write_reg(5, 0x40A3);
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lcd_write_reg(LTV_GATECTL2, (LTV_NW_INV_1LINE | LTV_FHN | LTV_FTI(2) | LTV_FWI(3)));
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lcd_write_reg(6, 0x0);
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lcd_write_reg(LTV_VBP, 0);
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lcd_write_reg(7, 0x0);
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lcd_write_reg(LTV_HBP, 0);
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lcd_write_reg(8, 0x0);
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lcd_write_reg(LTV_SOTCTL, 0);
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lcd_write_reg(9, 0x0);
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lcd_write_reg(LTV_PWRCTL1, 0);
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lcd_write_reg(10, 0x0);
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lcd_write_reg(LTV_PWRCTL2, 0);
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lcd_write_reg(16, 0x0);
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lcd_write_reg(LTV_GAMMA(0), 0);
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lcd_write_reg(17, 0x0);
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lcd_write_reg(LTV_GAMMA(1), 0);
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lcd_write_reg(18, 0x0);
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lcd_write_reg(LTV_GAMMA(2), 0);
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lcd_write_reg(19, 0x0);
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lcd_write_reg(LTV_GAMMA(3), 0);
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lcd_write_reg(20, 0x0);
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lcd_write_reg(LTV_GAMMA(4), 0);
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lcd_write_reg(21, 0x0);
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lcd_write_reg(LTV_GAMMA(5), 0);
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lcd_write_reg(22, 0x0);
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lcd_write_reg(LTV_GAMMA(6), 0);
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lcd_write_reg(23, 0x0);
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lcd_write_reg(LTV_GAMMA(7), 0);
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lcd_write_reg(24, 0x0);
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lcd_write_reg(LTV_GAMMA(8), 0);
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lcd_write_reg(25, 0x0);
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lcd_write_reg(LTV_GAMMA(9), 0);
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sleep_ms(10);
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sleep_ms(10);
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lcd_write_reg(9, 0x4055);
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lcd_write_reg(LTV_PWRCTL1, (LTV_VCOM_DISABLE | LTV_DRIVE_CURRENT(5) | LTV_SUPPLY_CURRENT(5)));
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lcd_write_reg(10, 0x0);
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lcd_write_reg(LTV_PWRCTL2, 0);
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sleep_ms(40);
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sleep_ms(40);
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lcd_write_reg(10, 0x2000);
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lcd_write_reg(LTV_PWRCTL2, LTV_VCOML_ENABLE);
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sleep_ms(40);
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sleep_ms(40);
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lcd_write_reg(1, 0x401D);
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lcd_write_reg(LTV_IFCTL, (LTV_NMD | LTV_NL(29)));
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lcd_write_reg(2, 0x204);
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lcd_write_reg(LTV_DATACTL, (LTV_DS_SAME | LTV_CHS_480 | LTV_DF_RGB | LTV_RGB_BGR));
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lcd_write_reg(3, 0x100);
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lcd_write_reg(LTV_ENTRY_MODE,(LTV_VSPL_ACTIVE_LOW | LTV_HSPL_ACTIVE_LOW | LTV_DPL_SAMPLE_RISING | LTV_EPL_ACTIVE_LOW | LTV_SS_RIGHT_TO_LEFT));
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lcd_write_reg(4, 0x1000);
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lcd_write_reg(LTV_GATECTL1, LTV_CLW(1));
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lcd_write_reg(5, 0x5033);
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lcd_write_reg(LTV_GATECTL2, (LTV_NW_INV_1LINE | LTV_DSC | LTV_FTI(3) | LTV_FWI(3)));
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lcd_write_reg(6, 0x5);
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lcd_write_reg(LTV_VBP, 0x5);
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lcd_write_reg(7, 0x1B);
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lcd_write_reg(LTV_HBP, 0x1B);
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lcd_write_reg(8, 0x800);
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lcd_write_reg(LTV_SOTCTL, LTV_SDT(2));
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lcd_write_reg(16, 0x203);
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lcd_write_reg(LTV_GAMMA(0), 0x203);
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lcd_write_reg(17, 0x302);
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lcd_write_reg(LTV_GAMMA(1), 0x302);
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lcd_write_reg(18, 0xC08);
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lcd_write_reg(LTV_GAMMA(2), 0xC08);
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lcd_write_reg(19, 0xC08);
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lcd_write_reg(LTV_GAMMA(3), 0xC08);
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lcd_write_reg(20, 0x707);
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lcd_write_reg(LTV_GAMMA(4), 0x707);
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lcd_write_reg(21, 0x707);
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lcd_write_reg(LTV_GAMMA(5), 0x707);
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lcd_write_reg(22, 0x104);
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lcd_write_reg(LTV_GAMMA(6), 0x104);
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lcd_write_reg(23, 0x306);
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lcd_write_reg(LTV_GAMMA(7), 0x306);
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lcd_write_reg(24, 0x0);
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lcd_write_reg(LTV_GAMMA(8), 0);
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lcd_write_reg(25, 0x0);
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lcd_write_reg(LTV_GAMMA(9), 0);
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sleep_ms(60);
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sleep_ms(60);
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lcd_write_reg(9, 0xA55);
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lcd_write_reg(LTV_PWRCTL1, (LTV_VCOMOUT_ENABLE | LTV_POWER_ON | LTV_DRIVE_CURRENT(5) | LTV_SUPPLY_CURRENT(5)));
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lcd_write_reg(10, 0x111A);
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lcd_write_reg(LTV_PWRCTL2, (LTV_VCOML_VOLTAGE(17) | LTV_VCOMH_VOLTAGE(26))); /* VCOML=0,0625V VCOMH=1,21875V */
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sleep_ms(10);
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sleep_ms(10);
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if(!reset)
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if(!reset)
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@ -194,15 +192,15 @@ static void lcd_display_on(bool reset)
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static void lcd_display_off(void)
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static void lcd_display_off(void)
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{
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{
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/* LQV shutdown sequence */
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/* LQV shutdown sequence */
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lcd_write_reg(9, 0x855);
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lcd_write_reg(LTV_PWRCTL1, (LTV_VCOMOUT_ENABLE | LTV_DRIVE_CURRENT(5) | LTV_SUPPLY_CURRENT(5)));
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sleep_ms(20);
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sleep_ms(20);
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lcd_write_reg(9, 0x55);
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lcd_write_reg(LTV_PWRCTL1, (LTV_DRIVE_CURRENT(5) | LTV_SUPPLY_CURRENT(5)));
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lcd_write_reg(5, 0x4033);
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lcd_write_reg(LTV_GATECTL2, (LTV_NW_INV_1LINE | LTV_FTI(3) | LTV_FWI(3)));
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lcd_write_reg(10, 0x0);
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lcd_write_reg(LTV_PWRCTL2, 0);
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sleep_ms(20);
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sleep_ms(20);
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lcd_write_reg(9, 0x0);
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lcd_write_reg(LTV_PWRCTL1, 0);
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sleep_ms(10);
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sleep_ms(10);
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unsigned char temp[1];
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unsigned char temp[1];
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temp[0] = 0;
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temp[0] = 0;
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