forked from len0rd/rockbox
imx31/mc13783: Do some housekeeping with register macros, function names and other defines. No functional changes (except to alter a couple int priorities).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20442 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
6a76ebbab1
commit
b7f7655dc2
23 changed files with 447 additions and 578 deletions
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@ -247,10 +247,10 @@
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#define SW_MUX_CTL_SIG3 (0x7f << 16)
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#define SW_MUX_CTL_SIG4 (0x7f << 24)
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/* Shift above flags into one of the four fields in each register */
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#define SW_MUX_CTL_SIG1w(x) (((x) << 0) & SW_MUX_CTL_SIG1)
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#define SW_MUX_CTL_SIG2w(x) (((x) << 8) & SW_MUX_CTL_SIG2)
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#define SW_MUX_CTL_SIG3w(x) (((x) << 16) & SW_MUX_CTL_SIG3)
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#define SW_MUX_CTL_SIG4w(x) (((x) << 24) & SW_MUX_CTL_SIG4)
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#define SW_MUX_CTL_SIG1_POS (0)
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#define SW_MUX_CTL_SIG2_POS (8)
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#define SW_MUX_CTL_SIG3_POS (16)
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#define SW_MUX_CTL_SIG4_POS (24)
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/* SW_PAD_CTL */
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#define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154)
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@ -395,9 +395,9 @@
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#define SW_PAD_CTL_IO3 (0x3ff << 20)
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/* Shift above flags into one of the three fields in each register */
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#define SW_PAD_CTL_IO1w(x) (((x) << 0) & SW_PAD_CTL_IO1)
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#define SW_PAD_CTL_IO2w(x) (((x) << 10) & SW_PAD_CTL_IO2)
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#define SW_PAD_CTL_IO3w(x) (((x) << 20) & SW_PAD_CTL_IO3)
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#define SW_PAD_CTL_IO1_POS (0)
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#define SW_PAD_CTL_IO2_POS (10)
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#define SW_PAD_CTL_IO3_POS (20)
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/* RNGA */
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#define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00))
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@ -530,7 +530,8 @@
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#define EPITCR_DBGEN (1 << 18)
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#define EPITCR_IOVW (1 << 17)
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#define EPITCR_SWR (1 << 16)
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#define EPITCR_PRESCALER(n) ((n) << 4) /* Divide by n+1 */
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#define EPITCR_PRESCALER (0xfff << 4) /* Divide by n+1 */
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#define EPITCR_PRESCALER_POS (4)
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#define EPITCR_RLD (1 << 3)
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#define EPITCR_OCIEN (1 << 2)
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#define EPITCR_ENMOD (1 << 1)
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@ -933,10 +934,10 @@
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#define AUDMUX_CNMCR_CLKPOL (1 << 16)
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#define AUDMUX_CNMCR_CNTHI (0xff << 8)
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#define AUDMUX_CNMCR_CNTHIw(x) (((x) << 8) & AUDMUX_CNMCR_CNTHI)
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#define AUDMUX_CNMCR_CNTHI_POS (8)
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#define AUDMUX_CNMCR_CNTLOW (0xff << 0)
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#define AUDMUX_CNMCR_CNTLOWw(x) (((x) << 0) & AUDMUX_CNMCR_CNTLOW)
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#define AUDMUX_CNMCR_CNTLOW_POS (0)
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/* SSI */
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#define SSI_STX0_1 (*(REG32_PTR_T)(SSI1_BASE_ADDR+0x00))
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@ -1080,57 +1081,39 @@
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#define SSI_STRCCR_WL24 (0xb << 13)
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#define SSI_STRCCR_DC (0x1f << 8)
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#define SSI_STRCCR_DCw(x) (((x) << 8) & SSI_STRCCR_DC)
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#define SSI_STRCCR_DCr(x) (((x) & SSI_SRCCR_DC) >> 8)
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#define SSI_STRCCR_DC_POS (8)
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#define SSI_STRCCR_PM (0xf << 0)
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#define SSI_STRCCR_PMw(x) (((x) << 0) & SSI_STRCCR_PM)
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#define SSI_STRCCR_PMr(x) (((x) & SSI_SRCCR_PM) >> 0)
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#define SSI_STRCCR_PM_POS (0)
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/* SSI SFCSR */
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#define SSI_SFCSR_RFCNT1 (0xf << 28)
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#define SSI_SFCSR_RFCNT1w(x) (((x) << 28) & SSI_SFCSR_RFCNT1)
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#define SSI_SFCSR_RFCNT1r(x) (((x) & SSI_SFCSR_RFCNT1) >> 28)
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#define SSI_SFCSR_RFCNT1_POS (28)
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#define SSI_SFCSR_TFCNT1 (0xf << 24)
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#define SSI_SFCSR_TFCNT1w(x) (((x) << 24) & SSI_SFCSR_TFCNT1)
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#define SSI_SFCSR_TFCNT1r(x) (((x) & SSI_SFCSR_TFCNT1) >> 24)
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#define SSI_SFCSR_TFCNN1_POS (24)
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#define SSI_SFCSR_RFWM1 (0xf << 20)
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#define SSI_SFCSR_RFWM1w(x) (((x) << 20) & SSI_SFCSR_RFWM1)
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#define SSI_SFCSR_RFWM1r(x) (((x) & SSI_SFCSR_RFWM1) >> 20)
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#define SSI_SFCSR_RFWM1_1 (0x1 << 20)
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#define SSI_SFCSR_RFWM1_2 (0x2 << 20)
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#define SSI_SFCSR_RFWM1_3 (0x3 << 20)
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#define SSI_SFCSR_RFWM1_4 (0x4 << 20)
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#define SSI_SFCSR_RFWM1_5 (0x5 << 20)
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#define SSI_SFCSR_RFWM1_6 (0x6 << 20)
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#define SSI_SFCSR_RFWM1_7 (0x7 << 20)
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#define SSI_SFCSR_RFWM1_POS (20)
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#define SSI_SFCSR_TFWM1 (0xf << 16)
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#define SSI_SFCSR_TFWM1w(x) (((x) << 16) & SSI_SFCSR_TFWM1)
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#define SSI_SFCSR_TFWM1r(x) (((x) & SSI_SFCSR_TFWM1) >> 16)
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#define SSI_SFCSR_TFWM1_POS (16)
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#define SSI_SFCSR_RFCNT0 (0xf << 12)
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#define SSI_SFCSR_RFCNT0w(x) (((x) << 12) & SSI_SFCSR_RFCNT0)
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#define SSI_SFCSR_RFCNT0r(x) (((x) & SSI_SFCSR_RFCNT0) >> 12)
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#define SSI_SFCSR_RFCNT0_POS (12)
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#define SSI_SFCSR_TFCNT0 (0xf << 8)
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#define SSI_SFCSR_TFCNT0w(x) (((x) << 8) & SSI_SFCSR_TFCNT0)
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#define SSI_SFCSR_TFCNT0r(x) (((x) & SSI_SFCSR_TFCNT0) >> 8)
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#define SSI_SFCSR_TFCNT0_POS (8)
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#define SSI_SFCSR_RFWM0 (0xf << 4)
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#define SSI_SFCSR_RFWM0w(x) (((x) << 4) & SSI_SFCSR_RFWM0)
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#define SSI_SFCSR_RFWM0r(x) (((x) & SSI_SFCSR_RFWM0) >> 4)
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#define SSI_SFCSR_RFWM0_POS (4)
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#define SSI_SFCSR_TFWM0 (0xf << 0)
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#define SSI_SFCSR_TFWM0w(x) (((x) << 0) & SSI_SFCSR_TFWM0)
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#define SSI_SFCSR_TFWM0r(x) (((x) & SSI_SFCSR_TFWM0) >> 0)
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#define SSI_SFCSR_TFWM0_POS (0)
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/* SACNT */
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#define SSI_SACNT_FRDIV (0x3f << 5)
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#define SSI_SACNT_FRDIVw(x) (((x) << 5) & SSI_SACNT_FRDIV)
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#define SSI_SACNT_FRDIVr(x) (((x) & SSI_SACNT_FRDIV) >> 5)
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#define SSI_SACNT_FRDIV_POS (5)
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#define SSI_SACNT_WR (0x1 << 4)
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#define SSI_SACNT_RD (0x1 << 3)
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@ -1156,8 +1139,7 @@
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#define WDOG_WRSR (*(REG16_PTR_T)(WDOG_BASE_ADDR+0x04))
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#define WDOG_WCR_WT (0xff << 8)
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#define WDOG_WCR_WTw(x) (((x) << 8) & WDOG_WCR_WT)
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#define WDOG_WCR_WTr(x) (((x) & WDOG_WCR_WT) >> 8)
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#define WDOG_WCR_WT_POS (8)
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#define WDOG_WCR_WOE (0x1 << 6)
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#define WDOG_WCR_WDA (0x1 << 5)
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@ -1245,45 +1227,45 @@
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/*
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* IRQ Controller Register Definitions.
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*/
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#define AVIC_BASE_ADDR 0x68000000
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#define INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
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#define NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
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#define INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
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#define INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
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#define INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
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#define INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
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#define INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
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#define INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
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#define NIPRIORITY(n) (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n])
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#define NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
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#define NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
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#define NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
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#define NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
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#define NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
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#define NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
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#define NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
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#define NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
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#define NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
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#define FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
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#define INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
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#define INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
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#define INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
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#define INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
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#define NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
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#define NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
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#define FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
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#define FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
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#define VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100)
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#define VECTOR(n) (((REG32_PTR_T)VECTOR_BASE_ADDR)[n])
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#define AVIC_BASE_ADDR 0x68000000
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#define AVIC_INTCNTL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x00))
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#define AVIC_NIMASK (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x04))
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#define AVIC_INTENNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x08))
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#define AVIC_INTDISNUM (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x0C))
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#define AVIC_INTENABLEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x10))
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#define AVIC_INTENABLEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x14))
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#define AVIC_INTTYPEH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x18))
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#define AVIC_INTTYPEL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x1C))
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#define AVIC_NIPRIORITY(n) (((REG32_PTR_T)(AVIC_BASE_ADDR+0x20))[n])
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#define AVIC_NIPRIORITY7 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x20))
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#define AVIC_NIPRIORITY6 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x24))
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#define AVIC_NIPRIORITY5 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x28))
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#define AVIC_NIPRIORITY4 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x2C))
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#define AVIC_NIPRIORITY3 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x30))
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#define AVIC_NIPRIORITY2 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x34))
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#define AVIC_NIPRIORITY1 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x38))
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#define AVIC_NIPRIORITY0 (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x3C))
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#define AVIC_NIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x40))
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#define AVIC_FIVECSR (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x44))
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#define AVIC_INTSRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x48))
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#define AVIC_INTSRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x4C))
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#define AVIC_INTFRCH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x50))
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#define AVIC_INTFRCL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x54))
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#define AVIC_NIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x58))
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#define AVIC_NIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x5C))
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#define AVIC_FIPNDH (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x60))
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#define AVIC_FIPNDL (*(REG32_PTR_T)(AVIC_BASE_ADDR+0x64))
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#define AVIC_VECTOR_BASE_ADDR (AVIC_BASE_ADDR+0x100)
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#define AVIC_VECTOR(n) (((REG32_PTR_T)VECTOR_BASE_ADDR)[n])
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/* The vectors go all the way up to 63. 4 bytes for each */
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#define INTCNTL_ABFLAG (1 << 25)
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#define INTCNTL_ABFEN (1 << 24)
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#define INTCNTL_NIDIS (1 << 22)
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#define INTCNTL_FIDIS (1 << 21)
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#define INTCNTL_NIAD (1 << 20)
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#define INTCNTL_FIAD (1 << 19)
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#define INTCNTL_NM (1 << 18)
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#define AVIC_INTCNTL_ABFLAG (1 << 25)
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#define AVIC_INTCNTL_ABFEN (1 << 24)
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#define AVIC_INTCNTL_NIDIS (1 << 22)
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#define AVIC_INTCNTL_FIDIS (1 << 21)
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#define AVIC_INTCNTL_NIAD (1 << 20)
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#define AVIC_INTCNTL_FIAD (1 << 19)
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#define AVIC_INTCNTL_NM (1 << 18)
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/* L210 */
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#define L2CC_BASE_ADDR 0x30000000
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@ -1299,224 +1281,167 @@
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#define L2CC_CACHE_SYNC (*(REG32_PTR_T)(L2CC_BASE_ADDR+L2_CACHE_SYNC_REG))
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/* CCM */
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#define CLKCTL_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
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#define CLKCTL_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
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#define CLKCTL_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
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#define CLKCTL_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
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#define CLKCTL_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
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#define CLKCTL_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
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#define CLKCTL_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
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#define CLKCTL_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
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#define CLKCTL_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
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#define CLKCTL_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
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#define CLKCTL_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
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#define CLKCTL_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
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#define CLKCTL_LDC (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30))
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#define CLKCTL_DCVR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34))
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#define CLKCTL_DCVR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38))
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#define CLKCTL_DCVR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C))
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#define CLKCTL_DCVR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40))
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#define CLKCTL_LTR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44))
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#define CLKCTL_LTR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48))
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#define CLKCTL_LTR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C))
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#define CLKCTL_LTR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50))
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#define CLKCTL_LTBR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54))
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#define CLKCTL_LTBR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58))
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#define CLKCTL_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
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#define CLKCTL_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60))
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#define CLKCTL_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
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#define CCM_CCMR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x00))
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#define CCM_PDR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x04))
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#define CCM_PDR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x08))
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#define CCM_RCSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x0C))
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#define CCM_MPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x10))
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#define CCM_UPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x14))
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#define CCM_SPCTL (*(REG32_PTR_T)(CCM_BASE_ADDR+0x18))
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#define CCM_COSR (*(REG32_PTR_T)(CCM_BASE_ADDR+0x1C))
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#define CCM_CGR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x20))
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#define CCM_CGR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x24))
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#define CCM_CGR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x28))
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#define CCM_WIMR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x2C))
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#define CCM_LDC (*(REG32_PTR_T)(CCM_BASE_ADDR+0x30))
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#define CCM_DCVR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x34))
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#define CCM_DCVR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x38))
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#define CCM_DCVR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x3C))
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#define CCM_DCVR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x40))
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#define CCM_LTR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x44))
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#define CCM_LTR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x48))
|
||||
#define CCM_LTR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x4C))
|
||||
#define CCM_LTR3 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x50))
|
||||
#define CCM_LTBR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x54))
|
||||
#define CCM_LTBR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x58))
|
||||
#define CCM_PMCR0 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x5C))
|
||||
#define CCM_PMCR1 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x60))
|
||||
#define CCM_PDR2 (*(REG32_PTR_T)(CCM_BASE_ADDR+0x64))
|
||||
|
||||
/* CCMR */
|
||||
#define CCMR_L2PG (0x1 << 29)
|
||||
#define CCMR_VSTBY (0x1 << 28)
|
||||
#define CCMR_WBEN (0x1 << 27)
|
||||
#define CCMR_FPMF (0x1 << 26)
|
||||
#define CCMR_CSCS (0x1 << 25)
|
||||
#define CCMR_PERCS (0x1 << 24)
|
||||
#define CCM_CCMR_L2PG (0x1 << 29)
|
||||
#define CCM_CCMR_VSTBY (0x1 << 28)
|
||||
#define CCM_CCMR_WBEN (0x1 << 27)
|
||||
#define CCM_CCMR_FPMF (0x1 << 26)
|
||||
#define CCM_CCMR_CSCS (0x1 << 25)
|
||||
#define CCM_CCMR_PERCS (0x1 << 24)
|
||||
|
||||
#define CCMR_SSI2S (0x3 << 21)
|
||||
#define CCMR_SSI2S_MCU_CLK (0x0 << 21)
|
||||
#define CCMR_SSI2S_USB_CLK (0x1 << 21)
|
||||
#define CCMR_SSI2S_SERIAL_CLK (0x2 << 21) /* default */
|
||||
#define CCM_CCMR_SSI2S (0x3 << 21)
|
||||
#define CCM_CCMR_SSI2S_MCU_CLK (0x0 << 21)
|
||||
#define CCM_CCMR_SSI2S_USB_CLK (0x1 << 21)
|
||||
#define CCM_CCMR_SSI2S_SERIAL_CLK (0x2 << 21) /* default */
|
||||
|
||||
#define CCMR_SSI1S (0x3 << 18)
|
||||
#define CCMR_SSI1S_MCU_CLK (0x0 << 18)
|
||||
#define CCMR_SSI1S_USB_CLK (0x1 << 18)
|
||||
#define CCMR_SSI1S_SERIAL_CLK (0x2 << 18) /* default */
|
||||
#define CCM_CCMR_SSI1S (0x3 << 18)
|
||||
#define CCM_CCMR_SSI1S_MCU_CLK (0x0 << 18)
|
||||
#define CCM_CCMR_SSI1S_USB_CLK (0x1 << 18)
|
||||
#define CCM_CCMR_SSI1S_SERIAL_CLK (0x2 << 18) /* default */
|
||||
|
||||
#define CCMR_RAMW (0x3 << 16)
|
||||
#define CCMR_RAMW_0ARM_0ALTMS (0x0 << 16)
|
||||
#define CCMR_RAMW_0ARM_1ALTMS (0x1 << 16) /* Not recommended */
|
||||
#define CCMR_RAMW_1ARM_0ALTMS (0x2 << 16) /* Not recommended */
|
||||
#define CCMR_RAMW_1ARM_1ALTMS (0x3 << 16)
|
||||
#define CCM_CCMR_RAMW (0x3 << 16)
|
||||
#define CCM_CCMR_RAMW_0ARM_0ALTMS (0x0 << 16)
|
||||
#define CCM_CCMR_RAMW_0ARM_1ALTMS (0x1 << 16) /* Not recommended */
|
||||
#define CCM_CCMR_RAMW_1ARM_0ALTMS (0x2 << 16) /* Not recommended */
|
||||
#define CCM_CCMR_RAMW_1ARM_1ALTMS (0x3 << 16)
|
||||
|
||||
#define CCMR_LPM (0x3 << 14)
|
||||
#define CCMR_LPM_WAIT_MODE (0x0 << 14)
|
||||
#define CCMR_LPM_DOZE_MODE (0x1 << 14)
|
||||
#define CCMR_LPM_SRM (0x2 << 14) /* State retention mode */
|
||||
#define CCMR_LPM_DSM (0x3 << 14) /* Deep sleep mode */
|
||||
#define CCM_CCMR_LPM (0x3 << 14)
|
||||
#define CCM_CCMR_LPM_WAIT_MODE (0x0 << 14)
|
||||
#define CCM_CCMR_LPM_DOZE_MODE (0x1 << 14)
|
||||
#define CCM_CCMR_LPM_SRM (0x2 << 14) /* State retention mode */
|
||||
#define CCM_CCMR_LPM_DSM (0x3 << 14) /* Deep sleep mode */
|
||||
|
||||
#define CCMR_FIRS (0x3 << 11)
|
||||
#define CCMR_FIRS_MCU_CLK (0x0 << 11)
|
||||
#define CCMR_FIRS_USB_CLK (0x1 << 11)
|
||||
#define CCMR_FIRS_SERIAL_CLK (0x2 << 11)
|
||||
#define CCM_CCMR_FIRS (0x3 << 11)
|
||||
#define CCM_CCMR_FIRS_MCU_CLK (0x0 << 11)
|
||||
#define CCM_CCMR_FIRS_USB_CLK (0x1 << 11)
|
||||
#define CCM_CCMR_FIRS_SERIAL_CLK (0x2 << 11)
|
||||
|
||||
#define CCMR_WAMO (0x1 << 10)
|
||||
#define CCMR_UPE (0x1 << 9)
|
||||
#define CCMR_SPE (0x1 << 8)
|
||||
#define CCMR_MDS (0x1 << 7)
|
||||
#define CCM_CCMR_WAMO (0x1 << 10)
|
||||
#define CCM_CCMR_UPE (0x1 << 9)
|
||||
#define CCM_CCMR_SPE (0x1 << 8)
|
||||
#define CCM_CCMR_MDS (0x1 << 7)
|
||||
|
||||
#define CCMR_ROMW (0x3 << 5)
|
||||
#define CCMR_ROMW_0ARM_0ALTMS (0x0 << 5)
|
||||
#define CCMR_ROMW_0ARM_1ALTMS (0x1 << 5) /* Not recommended */
|
||||
#define CCMR_ROMW_1ARM_0ALTMS (0x2 << 5) /* Not recommended */
|
||||
#define CCMR_ROMW_1ARM_1ALTMS (0x3 << 5)
|
||||
#define CCM_CCMR_ROMW (0x3 << 5)
|
||||
#define CCM_CCMR_ROMW_0ARM_0ALTMS (0x0 << 5)
|
||||
#define CCM_CCMR_ROMW_0ARM_1ALTMS (0x1 << 5) /* Not recommended */
|
||||
#define CCM_CCMR_ROMW_1ARM_0ALTMS (0x2 << 5) /* Not recommended */
|
||||
#define CCM_CCMR_ROMW_1ARM_1ALTMS (0x3 << 5)
|
||||
|
||||
#define CCMR_SBYCS (0x1 << 4)
|
||||
#define CCMR_MPE (0x1 << 3)
|
||||
#define CCM_CCMR_SBYCS (0x1 << 4)
|
||||
#define CCM_CCMR_MPE (0x1 << 3)
|
||||
|
||||
#define CCMR_PRCS (0x3 << 1)
|
||||
#define CCMR_PRCS_FPM (0x1 << 1)
|
||||
#define CCMR_PRCS_CKIH (0x2 << 1)
|
||||
#define CCM_CCMR_PRCS (0x3 << 1)
|
||||
#define CCM_CCMR_PRCS_FPM (0x1 << 1)
|
||||
#define CCM_CCMR_PRCS_CKIH (0x2 << 1)
|
||||
|
||||
#define CCMR_FPME (0x1 << 0)
|
||||
#define CCM_CCMR_FPME (0x1 << 0)
|
||||
|
||||
/* PDR0 */
|
||||
#define PDR0_CSI_PODF (0x1ff << 23)
|
||||
#define PDR0_CSI_PODFw(x) (((x) << 23) & PDR0_CSI_PODF)
|
||||
#define PDR0_CSI_PODFr(x) (((x) & PDR0_CSI_PODF) >> 23)
|
||||
#define CCM_PDR0_CSI_PODF (0x1ff << 23)
|
||||
#define CCM_PDR0_CSI_PODF_POS (23)
|
||||
|
||||
#define PDR0_PER_PODF (0x1f << 16)
|
||||
#define PDR0_PER_PODFw(x) (((x) << 16) & PDR0_PER_PODF)
|
||||
#define PDR0_PER_PODFr(x) (((x) & PDR0_PER_PODF) >> 16)
|
||||
#define CCM_PDR0_PER_PODF (0x1f << 16)
|
||||
#define CCM_PDR0_PER_PODF_POS (16)
|
||||
|
||||
#define PDR0_HSP_PODF (0x7 << 11)
|
||||
#define PDR0_HSP_PODFw(x) (((x) << 11) & PDR0_HSP_PODF)
|
||||
#define PDR0_HSP_PODFr(x) (((x) & PDR0_HSP_PODF) >> 11)
|
||||
#define CCM_PDR0_HSP_PODF (0x7 << 11)
|
||||
#define CCM_PDR0_HSP_PODF_POS (11)
|
||||
|
||||
#define PDR0_NFC_PODF (0x7 << 8)
|
||||
#define PDR0_NFC_PODFw(x) (((x) << 8) & PDR0_NFC_PODF)
|
||||
#define PDR0_NFC_PODFr(x) (((x) & PDR0_NFC_PODF) >> 8)
|
||||
#define CCM_PDR0_NFC_PODF (0x7 << 8)
|
||||
#define CCM_PDR0_NFC_PODF_POS (8)
|
||||
|
||||
#define PDR0_IPG_PODF (0x3 << 6)
|
||||
#define PDR0_IPG_PODFw(x) (((x) << 6) & PDR0_IPG_PODF)
|
||||
#define PDR0_IPG_PODFr(x) (((x) & PDR0_IPG_PODF) >> 6)
|
||||
#define CCM_PDR0_IPG_PODF (0x3 << 6)
|
||||
#define CCM_PDR0_IPG_PODF_POS (6)
|
||||
|
||||
#define PDR0_MAX_PODF (0x7 << 3)
|
||||
#define PDR0_MAX_PODFw(x) (((x) << 3) & PDR0_MAX_PODF)
|
||||
#define PDR0_MAX_PODFr(x) (((x) & PDR0_MAX_PODF) >> 3)
|
||||
#define CCM_PDR0_MAX_PODF (0x7 << 3)
|
||||
#define CCM_PDR0_MAX_PODF_POS (3)
|
||||
|
||||
#define PDR0_MCU_PODF (0x7 << 0)
|
||||
#define PDR0_MCU_PODFw(x) (((x) << 0) & PDR0_MCU_PODF)
|
||||
#define PDR0_MCU_PODFr(x) (((x) & PDR0_MCU_PODF) >> 0)
|
||||
#define CCM_PDR0_MCU_PODF (0x7 << 0)
|
||||
#define CCM_PDR0_MCU_PODF_POS (0)
|
||||
|
||||
/* PDR1 */
|
||||
#define PDR1_USB_PRDF (0x3 << 30)
|
||||
#define PDR1_USB_PRDFw(x) (((x) << 30) & PDR1_USB_PRDF)
|
||||
#define PDR1_USB_PRDFr(x) (((x) & PDR1_USB_PRDF) >> 30)
|
||||
#define CCM_PDR1_USB_PRDF (0x3 << 30)
|
||||
#define CCM_PDR1_USB_PRDF_POS (30)
|
||||
|
||||
#define PDR1_USB_PODF (0x7 << 27)
|
||||
#define PDR1_USB_PODFw(x) (((x) << 27) & PDR1_USB_PODF)
|
||||
#define PDR1_USB_PODFr(x) (((x) & PDR1_USB_PODF) >> 27)
|
||||
#define CCM_PDR1_USB_PODF (0x7 << 27)
|
||||
#define CCM_PDR1_USB_PODF_POS (27)
|
||||
|
||||
#define PDR1_FIRI_PRE_PODF (0x7 << 24)
|
||||
#define PDR1_FIRI_PRE_PODFw(x) (((x) << 24) & PDR1_FIRI_PRE_PODF)
|
||||
#define PDR1_FIRI_PRE_PODFr(x) (((x) & PDR1_FIRI_PRE_PODF) >> 24)
|
||||
#define CCM_PDR1_FIRI_PRE_PODF (0x7 << 24)
|
||||
#define CCM_PDR1_FIRI_PRE_PODF_POS (24)
|
||||
|
||||
#define PDR1_FIRI_PODF (0x3f << 18)
|
||||
#define PDR1_FIRI_PODFw(x) (((x) << 18) & PDR1_FIRI_PODF)
|
||||
#define PDR1_FIRI_PODFr(x) (((x) & PDR1_FIRI_PODF) >> 18)
|
||||
#define CCM_PDR1_FIRI_PODF (0x3f << 18)
|
||||
#define CCM_PDR1_FIRI_PODF_POS (18)
|
||||
|
||||
#define PDR1_SSI2_PRE_PODF (0x7 << 15)
|
||||
#define PDR1_SSI2_PRE_PODFw(x) (((x) << 15) & PDR1_SSI2_PRE_PODF)
|
||||
#define PDR1_SSI2_PRE_PODFr(x) (((x) & PDR1_SSI2_PRE_PODF) >> 15)
|
||||
#define CCM_PDR1_SSI2_PRE_PODF (0x7 << 15)
|
||||
#define CCM_PDR1_SSI2_PRE_PODF_POS (15)
|
||||
|
||||
#define PDR1_SSI2_PODF (0x3f << 9)
|
||||
#define PDR1_SSI2_PODFw(x) (((x) << 9) & PDR1_SSI2_PODF)
|
||||
#define PDR1_SSI2_PODFr(x) (((x) & PDR1_SSI2_PODF) >> 9)
|
||||
#define CCM_PDR1_SSI2_PODF (0x3f << 9)
|
||||
#define CCM_PDR1_SSI2_PODF_POS (9)
|
||||
|
||||
#define PDR1_SSI1_PRE_PODF (0x7 << 6)
|
||||
#define PDR1_SSI1_PRE_PODFw(x) (((x) << 6) & PDR1_SSI1_PRE_PODF)
|
||||
#define PDR1_SSI1_PRE_PODFr(x) (((x) & PDR1_SSI1_PRE_PODF) >> 6)
|
||||
#define CCM_PDR1_SSI1_PRE_PODF (0x7 << 6)
|
||||
#define CCM_PDR1_SSI1_PRE_PODF_POS (6)
|
||||
|
||||
#define PDR1_SSI1_PODF (0x3f << 0)
|
||||
#define PDR1_SSI1_PODFw(x) (((x) << 0) & PDR1_SSI1_PODF)
|
||||
#define PDR1_SSI1_PODFr(x) (((x) & PDR1_SSI1_PODF) >> 0)
|
||||
#define CCM_PDR1_SSI1_PODF (0x3f << 0)
|
||||
#define CCM_PDR1_SSI1_PODF_POS (0)
|
||||
|
||||
#define CGR0_SD_MMC1(cg) ((cg) << 0*2)
|
||||
#define CGR0_SD_MMC2(cg) ((cg) << 1*2)
|
||||
#define CGR0_GPT(cg) ((cg) << 2*2)
|
||||
#define CGR0_EPIT1(cg) ((cg) << 3*2)
|
||||
#define CGR0_EPIT2(cg) ((cg) << 4*2)
|
||||
#define CGR0_IIM(cg) ((cg) << 5*2)
|
||||
#define CGR0_ATA(cg) ((cg) << 6*2)
|
||||
#define CGR0_SDMA(cg) ((cg) << 7*2)
|
||||
#define CGR0_CSPI3(cg) ((cg) << 8*2)
|
||||
#define CGR0_RNG(cg) ((cg) << 9*2)
|
||||
#define CGR0_UART1(cg) ((cg) << 10*2)
|
||||
#define CGR0_UART2(cg) ((cg) << 11*2)
|
||||
#define CGR0_SSI1(cg) ((cg) << 12*2)
|
||||
#define CGR0_I2C1(cg) ((cg) << 13*2)
|
||||
#define CGR0_I2C2(cg) ((cg) << 14*2)
|
||||
#define CGR0_I2C3(cg) ((cg) << 15*2)
|
||||
|
||||
#define CGR1_HANTRO(cg) ((cg) << 0*2)
|
||||
#define CGR1_MEMSTICK1(cg) ((cg) << 1*2)
|
||||
#define CGR1_MEMSTICK2(cg) ((cg) << 2*2)
|
||||
#define CGR1_CSI(cg) ((cg) << 3*2)
|
||||
#define CGR1_RTC(cg) ((cg) << 4*2)
|
||||
#define CGR1_WDOG(cg) ((cg) << 5*2)
|
||||
#define CGR1_PWM(cg) ((cg) << 6*2)
|
||||
#define CGR1_SIM(cg) ((cg) << 7*2)
|
||||
#define CGR1_ECT(cg) ((cg) << 8*2)
|
||||
#define CGR1_USBOTG(cg) ((cg) << 9*2)
|
||||
#define CGR1_KPP(cg) ((cg) << 10*2)
|
||||
#define CGR1_IPU(cg) ((cg) << 11*2)
|
||||
#define CGR1_UART3(cg) ((cg) << 12*2)
|
||||
#define CGR1_UART4(cg) ((cg) << 13*2)
|
||||
#define CGR1_UART5(cg) ((cg) << 14*2)
|
||||
#define CGR1_1_WIRE(cg) ((cg) << 15*2)
|
||||
|
||||
#define CGR2_SSI2(cg) ((cg) << 0*2)
|
||||
#define CGR2_CSPI1(cg) ((cg) << 1*2)
|
||||
#define CGR2_CSPI2(cg) ((cg) << 2*2)
|
||||
#define CGR2_GACC(cg) ((cg) << 3*2)
|
||||
#define CGR2_EMI(cg) ((cg) << 4*2)
|
||||
#define CGR2_RTIC(cg) ((cg) << 5*2)
|
||||
#define CGR2_FIR(cg) ((cg) << 6*2)
|
||||
|
||||
#define WIM_GPIO3 (1 << 0)
|
||||
#define WIM_GPIO2 (1 << 1)
|
||||
#define WIM_GPIO1 (1 << 2)
|
||||
#define WIM_PCMCIA (1 << 3)
|
||||
#define WIM_WDT (1 << 4)
|
||||
#define WIM_USB_OTG (1 << 5)
|
||||
#define WIM_IPI_INT_UH2 (1 << 6)
|
||||
#define WIM_IPI_INT_UH1 (1 << 7)
|
||||
#define WIM_IPI_INT_UART5_ANDED (1 << 8)
|
||||
#define WIM_IPI_INT_UART4_ANDED (1 << 9)
|
||||
#define WIM_IPI_INT_UART3_ANDED (1 << 10)
|
||||
#define WIM_IPI_INT_UART2_ANDED (1 << 11)
|
||||
#define WIM_IPI_INT_UART1_ANDED (1 << 12)
|
||||
#define WIM_IPI_INT_SIM_DATA_IRQ (1 << 13)
|
||||
#define WIM_IPI_INT_SDHC2 (1 << 14)
|
||||
#define WIM_IPI_INT_SDHC1 (1 << 15)
|
||||
#define WIM_IPI_INT_RTC (1 << 16)
|
||||
#define WIM_IPI_INT_PWM (1 << 17)
|
||||
#define WIM_IPI_INT_KPP (1 << 18)
|
||||
#define WIM_IPI_INT_IIM (1 << 19)
|
||||
#define WIM_IPI_INT_GPT (1 << 20)
|
||||
#define WIM_IPI_INT_FIR (1 << 21)
|
||||
#define WIM_IPI_INT_EPIT2 (1 << 22)
|
||||
#define WIM_IPI_INT_EPIT1 (1 << 23)
|
||||
#define WIM_IPI_INT_CSPI2 (1 << 24)
|
||||
#define WIM_IPI_INT_CSPI1 (1 << 25)
|
||||
#define WIM_IPI_INT_POWER_FAIL (1 << 26)
|
||||
#define WIM_IPI_INT_CSPI3 (1 << 27)
|
||||
#define WIM_RESERVED28 (1 << 28)
|
||||
#define WIM_RESERVED29 (1 << 29)
|
||||
#define WIM_RESERVED30 (1 << 30)
|
||||
#define WIM_RESERVED31 (1 << 31)
|
||||
#define CCM_WIMR0_GPIO3 (1 << 0)
|
||||
#define CCM_WIMR0_GPIO2 (1 << 1)
|
||||
#define CCM_WIMR0_GPIO1 (1 << 2)
|
||||
#define CCM_WIMR0_PCMCIA (1 << 3)
|
||||
#define CCM_WIMR0_WDT (1 << 4)
|
||||
#define CCM_WIMR0_USB_OTG (1 << 5)
|
||||
#define CCM_WIMR0_IPI_INT_UH2 (1 << 6)
|
||||
#define CCM_WIMR0_IPI_INT_UH1 (1 << 7)
|
||||
#define CCM_WIMR0_IPI_INT_UART5_ANDED (1 << 8)
|
||||
#define CCM_WIMR0_IPI_INT_UART4_ANDED (1 << 9)
|
||||
#define CCM_WIMR0_IPI_INT_UART3_ANDED (1 << 10)
|
||||
#define CCM_WIMR0_IPI_INT_UART2_ANDED (1 << 11)
|
||||
#define CCM_WIMR0_IPI_INT_UART1_ANDED (1 << 12)
|
||||
#define CCM_WIMR0_IPI_INT_SIM_DATA_IRQ (1 << 13)
|
||||
#define CCM_WIMR0_IPI_INT_SDHC2 (1 << 14)
|
||||
#define CCM_WIMR0_IPI_INT_SDHC1 (1 << 15)
|
||||
#define CCM_WIMR0_IPI_INT_RTC (1 << 16)
|
||||
#define CCM_WIMR0_IPI_INT_PWM (1 << 17)
|
||||
#define CCM_WIMR0_IPI_INT_KPP (1 << 18)
|
||||
#define CCM_WIMR0_IPI_INT_IIM (1 << 19)
|
||||
#define CCM_WIMR0_IPI_INT_GPT (1 << 20)
|
||||
#define CCM_WIMR0_IPI_INT_FIR (1 << 21)
|
||||
#define CCM_WIMR0_IPI_INT_EPIT2 (1 << 22)
|
||||
#define CCM_WIMR0_IPI_INT_EPIT1 (1 << 23)
|
||||
#define CCM_WIMR0_IPI_INT_CSPI2 (1 << 24)
|
||||
#define CCM_WIMR0_IPI_INT_CSPI1 (1 << 25)
|
||||
#define CCM_WIMR0_IPI_INT_POWER_FAIL (1 << 26)
|
||||
#define CCM_WIMR0_IPI_INT_CSPI3 (1 << 27)
|
||||
#define CCM_WIMR0_RESERVED28 (1 << 28)
|
||||
#define CCM_WIMR0_RESERVED29 (1 << 29)
|
||||
#define CCM_WIMR0_RESERVED30 (1 << 30)
|
||||
#define CCM_WIMR0_RESERVED31 (1 << 31)
|
||||
|
||||
/* WEIM - CS0 */
|
||||
#define CSCRU 0x00
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue