diff --git a/firmware/drivers/audio/wm8721.c b/firmware/drivers/audio/wm8721.c
index 9b58454ca8..c175d2d74a 100644
--- a/firmware/drivers/audio/wm8721.c
+++ b/firmware/drivers/audio/wm8721.c
@@ -82,10 +82,10 @@ void audiohw_mute(bool mute)
     if (mute)
     {
         /* Set DACMU = 1 to soft-mute the audio DACs. */
-        wmcodec_write(DACCTRL, 0x8);
+        wmcodec_write(DAPCTRL, 0x8);
     } else {
         /* Set DACMU = 0 to soft-un-mute the audio DACs. */
-        wmcodec_write(DACCTRL, 0x0);
+        wmcodec_write(DAPCTRL, 0x0);
     }
 }
 
@@ -117,7 +117,7 @@ void audiohw_enable_output(bool enable)
         wmcodec_write(0x4, 0x10);
     
         /* set power register to POWEROFF=0 on OUTPD=0, DACPD=0 */
-        wmcodec_write(PWRMGMT, 0x67);
+        wmcodec_write(PDCTRL, 0x67);
 
         /* BCLKINV=0(Dont invert BCLK) MS=1(Enable Master) LRSWAP=0 LRP=0 */
         /* IWL=00(16 bit) FORMAT=10(I2S format) */
@@ -133,7 +133,7 @@ void audiohw_enable_output(bool enable)
         codec_set_active(1);
 
         /* 5. Set DACMU = 0 to soft-un-mute the audio DACs. */
-        wmcodec_write(DACCTRL, 0x0);
+        wmcodec_write(DAPCTRL, 0x0);
         
         audiohw_mute(0);
     } else {
@@ -158,22 +158,19 @@ int audiohw_set_master_vol(int vol_l, int vol_r)
 void audiohw_close(void)
 {
    /* set DACMU=1 DEEMPH=0 */
-    wmcodec_write(DACCTRL, 0x8);
+    wmcodec_write(DAPCTRL, 0x8);
 
     /* ACTIVE=0 */
     codec_set_active(0x0);
 
-    /* line in mute left & right*/
-    wmcodec_write(LINVOL, 0x100 | 0x80);
-
     /* set DACSEL=0, MUTEMIC=1 */
     wmcodec_write(0x4, 0x2);
 
     /* set POWEROFF=0 OUTPD=0 DACPD=1 */
-    wmcodec_write(PWRMGMT, 0x6f);
+    wmcodec_write(PDCTRL, 0x6f);
 
     /* set POWEROFF=1 OUTPD=1 DACPD=1 */
-    wmcodec_write(PWRMGMT, 0xff);
+    wmcodec_write(PDCTRL, 0xff);
 }
 
 /* Change the order of the noise shaper, 5th order is recommended above 32kHz */
diff --git a/firmware/export/wm8721.h b/firmware/export/wm8721.h
index fb9cc535ab..223c3e1a0e 100644
--- a/firmware/export/wm8721.h
+++ b/firmware/export/wm8721.h
@@ -61,23 +61,23 @@ extern void audiohw_set_sample_rate(int sampling_control);
 #define PDCTRL_POWEROFF         (1 << 7)
 
 #define AINTFCE                 0x07
-#define AINTFCE_FORMAT_MSB_RJUST(0 << 0)
-#define AINTFCE_FORMAT_MSB_LJUST(1 << 0)
-#define AINTFCE_FORMAT_I2S      (2 << 0)
-#define AINTFCE_FORMAT_DSP      (3 << 0)
-#define AINTFCE_FORMAT_MASK     (3 << 0)
-#define AINTFCE_IWL_16BIT       (0 << 2)
-#define AINTFCE_IWL_20BIT       (1 << 2)
-#define AINTFCE_IWL_24BIT       (2 << 2)
-#define AINTFCE_IWL_32BIT       (3 << 2)
-#define AINTFCE_IWL_MASK        (3 << 2)
-#define AINTFCE_LRP_I2S_RLO     (0 << 4)
-#define AINTFCE_LRP_I2S_RHI     (1 << 4)
-#define AINTFCE_DSP_MODE_A      (0 << 4)
-#define AINTFCE_DSP_MODE_B      (1 << 4)
-#define AINTFCE_LRSWAP          (1 << 5)
-#define AINTFCE_MS              (1 << 6)
-#define AINTFCE_BCLKINV         (1 << 7)
+#define AINTFCE_FORMAT_MSB_RJUST (0 << 0)
+#define AINTFCE_FORMAT_MSB_LJUST (1 << 0)
+#define AINTFCE_FORMAT_I2S       (2 << 0)
+#define AINTFCE_FORMAT_DSP       (3 << 0)
+#define AINTFCE_FORMAT_MASK      (3 << 0)
+#define AINTFCE_IWL_16BIT        (0 << 2)
+#define AINTFCE_IWL_20BIT        (1 << 2)
+#define AINTFCE_IWL_24BIT        (2 << 2)
+#define AINTFCE_IWL_32BIT        (3 << 2)
+#define AINTFCE_IWL_MASK         (3 << 2)
+#define AINTFCE_LRP_I2S_RLO      (0 << 4)
+#define AINTFCE_LRP_I2S_RHI      (1 << 4)
+#define AINTFCE_DSP_MODE_A       (0 << 4)
+#define AINTFCE_DSP_MODE_B       (1 << 4)
+#define AINTFCE_LRSWAP           (1 << 5)
+#define AINTFCE_MS               (1 << 6)
+#define AINTFCE_BCLKINV          (1 << 7)
 
 #define SAMPCTRL                0x08
 #define SAMPCTRL_USB            (1 << 0)
@@ -86,7 +86,7 @@ extern void audiohw_set_sample_rate(int sampling_control);
 #define SAMPCTRL_BOSR_USB_250fs (0 << 1)
 #define SAMPCTRL_BOSR_USB_272fs (1 << 1)
 /* Bits 2-5:
- * Sample rate setting are device-specific. See WM8731(L) datasheet
+ * Sample rate setting are device-specific. See WM8721 datasheet
  * for proper settings for the device's clocking */
 #define SAMPCTRL_SR_MASK        (0xf << 2)
 #define SAMPCTRL_CLKIDIV2       (1 << 6)