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HD200 - change how adc is scanned (inspired by amiconn)

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26138 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Marcin Bukat 2010-05-18 12:29:21 +00:00
parent 6cbc701d2a
commit b627106392
2 changed files with 21 additions and 22 deletions
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28
firmware/target/coldfire/mpio/hd200/adc-hd200.c
View file

@ -29,18 +29,16 @@
volatile unsigned short adc_data[NUM_ADC_CHANNELS] IBSS_ATTR; volatile unsigned short adc_data[NUM_ADC_CHANNELS] IBSS_ATTR;
/* Reading takes 4096 adclk ticks /* Reading takes 4096 adclk ticks
* We do read one channel at once * 1) tick task is created that enables ADC interrupt
* * 2) On interrupt single channel is readed and
* state FCPU Fbus Fadc bus/Fadc Fchannelread * ADC is prepared for next channel
* default 11.2896 MHz 5.6448 MHz 5.6448 MHz 2 172.2656 Hz * 3) When all 4 channels are scanned ADC interrupt is disabled
* normal 45.1584 MHz 22.5792 MHz 2.8224 MHz 8 172.2656 Hz
* max 124.1856 MHz 62.0928 MHz 1.9404 MHz 32 118.4326 Hz
*/ */
void ADC(void) __attribute__ ((interrupt_handler,section(".icode"))); void ADC(void) __attribute__ ((interrupt_handler,section(".icode")));
void ADC(void) void ADC(void)
{ {
static unsigned int channel IBSS_ATTR; static unsigned char channel IBSS_ATTR;
/* read current value */ /* read current value */
adc_data[(channel & 0x03)] = ADVALUE; adc_data[(channel & 0x03)] = ADVALUE;
@ -56,6 +54,9 @@ void ADC(void)
and_l(~(3<<24),&ADCONFIG); and_l(~(3<<24),&ADCONFIG);
or_l( (((channel & 0x03) << 8 )|(1<<7))<<16, &ADCONFIG); or_l( (((channel & 0x03) << 8 )|(1<<7))<<16, &ADCONFIG);
if ( (channel & 0x03) == 0 )
/* disable ADC interrupt */
and_l((~(1<<6))<<16,&ADCONFIG);
} }
unsigned short adc_scan(int channel) unsigned short adc_scan(int channel)
@ -64,6 +65,12 @@ unsigned short adc_scan(int channel)
return adc_data[(channel&0x03)]; return adc_data[(channel&0x03)];
} }
void adc_tick(void)
{
/* enable ADC interrupt */
or_l( ((1<<6))<<16, &ADCONFIG);
}
void adc_init(void) void adc_init(void)
{ {
/* GPIO38 GPIO39 */ /* GPIO38 GPIO39 */
@ -72,13 +79,16 @@ void adc_init(void)
/* ADOUT_SEL = 01 /* ADOUT_SEL = 01
* SOURCE SELECT = 000 * SOURCE SELECT = 000
* CLEAR INTERRUPT FLAG * CLEAR INTERRUPT FLAG
* ENABLE INTERRUPT = 1 * ENABLE INTERRUPT = 0
* ADOUT_DRIVE = 00 * ADOUT_DRIVE = 00
* ADCLK_SEL = 011 (busclk/8) * ADCLK_SEL = 011 (busclk/8)
*/ */
ADCONFIG = (1<<10)|(1<<7)|(1<<6)|(1<<1)|(1<<0); ADCONFIG = (1<<10)|(1<<7)|(1<<1)|(1<<0);
/* ADC interrupt level 4.0 */ /* ADC interrupt level 4.0 */
or_l((4<<28), &INTPRI8); or_l((4<<28), &INTPRI8);
/* create tick task which enables ADC interrupt */
tick_add_task(adc_tick);
} }

13
firmware/target/coldfire/mpio/hd200/system-hd200.c
View file

@ -77,10 +77,6 @@ void cf_set_cpu_frequency(long frequency)
IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(3<<10); IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(3<<10);
/* BUFEN2 enable on /CS2 | CS2Post 1 clock| CS2Pre 3 clocks*/ /* BUFEN2 enable on /CS2 | CS2Post 1 clock| CS2Pre 3 clocks*/
IDECONFIG2 = (1<<18)|(1<<16)|(1<<8)|(1<<0); /* TA /CS2 enable + CS2wait */ IDECONFIG2 = (1<<18)|(1<<16)|(1<<8)|(1<<0); /* TA /CS2 enable + CS2wait */
and_l(~(0x07<<16), &ADCONFIG);
or_l(((1<<7)|(1<<2)|(1<<0))<<16, &ADCONFIG); /* adclk = busclk/32 */
break; break;
case CPUFREQ_NORMAL: case CPUFREQ_NORMAL:
@ -98,11 +94,8 @@ void cf_set_cpu_frequency(long frequency)
cpu_frequency = CPUFREQ_NORMAL; cpu_frequency = CPUFREQ_NORMAL;
IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(1<<10); IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(1<<10);
IDECONFIG2 = (1<<18)|(1<<16); IDECONFIG2 = (1<<18)|(1<<16);
and_l(~(0x07<<16), &ADCONFIG);
or_l(((1<<7)|(1<<1)|(1<<0))<<16, &ADCONFIG); /* adclk = busclk/8 */
break; break;
default: default:
DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;
/* Refresh timer for bypass frequency */ /* Refresh timer for bypass frequency */
@ -116,10 +109,6 @@ void cf_set_cpu_frequency(long frequency)
cpu_frequency = CPUFREQ_DEFAULT; cpu_frequency = CPUFREQ_DEFAULT;
IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(1<<10); IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(1<<10);
IDECONFIG2 = (1<<18)|(1<<16); IDECONFIG2 = (1<<18)|(1<<16);
and_l(~(0x07<<16), &ADCONFIG);
or_l(((1<<7)|(1<<0))<<16, &ADCONFIG); /* adclk = busclk/2 */
break; break;
} }
} }