devs/foxbox
1
0
Fork 0
forked from len0rd/rockbox
Code Pull requests Activity

Use STORAGE_WANTS_ALIGN to make clear it's not a strict necessity

Browse source 
Define PROC_NEEDS_CACHEALIGN only for PP

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25339 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré 2010-03-26 00:11:50 +00:00
parent e108d571ba
commit b6065a8ceb
3 changed files with 15 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

29
firmware/export/system.h
View file

@ -293,11 +293,13 @@ static inline void cpucache_flush(void)
} }
#endif #endif
#ifdef PROC_NEEDS_CACHEALIGN #ifdef CACHEALIGN_BITS
/* Cache alignment attributes and sizes are enabled */
/* 2^CACHEALIGN_BITS = the byte size */ /* 2^CACHEALIGN_BITS = the byte size */
#define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS) #define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS)
#endif
#ifdef PROC_NEEDS_CACHEALIGN
/* Cache alignment attributes and sizes are enabled */
#define CACHEALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE))) #define CACHEALIGN_ATTR __attribute__((aligned(CACHEALIGN_SIZE)))
/* Aligns x up to a CACHEALIGN_SIZE boundary */ /* Aligns x up to a CACHEALIGN_SIZE boundary */
@ -312,16 +314,6 @@ static inline void cpucache_flush(void)
/* Aligns a buffer pointer and size to proper boundaries */ /* Aligns a buffer pointer and size to proper boundaries */
#define CACHEALIGN_BUFFER(start, size) \ #define CACHEALIGN_BUFFER(start, size) \
ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE) ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE)
/* Pad a size so the buffer can be aligned later */
#define CACHE_PAD(x) ((x) + CACHEALIGN_SIZE - 1)
/* Number of bytes in the last cacheline assuming buffer of size x is aligned */
#define CACHE_OVERLAP(x) ((x) & (CACHEALIGN_SIZE - 1))
#ifdef NEEDS_STORAGE_ALIGN
#define STORAGE_ALIGN_DOWN(x) CACHEALIGN_DOWN(x)
#define STORAGE_PAD(x) CACHE_PAD(x)
#define STORAGE_OVERLAP(x) CACHE_OVERLAP(x)
#endif
#else /* ndef PROC_NEEDS_CACHEALIGN */ #else /* ndef PROC_NEEDS_CACHEALIGN */
@ -333,12 +325,17 @@ static inline void cpucache_flush(void)
#define CACHEALIGN_DOWN(x) (x) #define CACHEALIGN_DOWN(x) (x)
/* Make no adjustments */ /* Make no adjustments */
#define CACHEALIGN_BUFFER(start, size) #define CACHEALIGN_BUFFER(start, size)
#define CACHE_PAD(x) (x)
#define CACHE_OVERLAP(x) 0
#endif /* PROC_NEEDS_CACHEALIGN */ #endif /* PROC_NEEDS_CACHEALIGN */
#if !defined(PROC_NEEDS_CACHEALIGN) || !defined(NEEDS_STORAGE_ALIGN) #ifdef STORAGE_WANTS_ALIGN
#define STORAGE_ALIGN_DOWN(x) \
((typeof (x))ALIGN_DOWN_P2((uintptr_t)(x), CACHEALIGN_BITS))
/* Pad a size so the buffer can be aligned later */
#define STORAGE_PAD(x) ((x) + CACHEALIGN_SIZE - 1)
/* Number of bytes in the last cacheline assuming buffer of size x is aligned */
#define STORAGE_OVERLAP(x) ((x) & (CACHEALIGN_SIZE - 1))
#else
#define STORAGE_ALIGN_DOWN(x) (x) #define STORAGE_ALIGN_DOWN(x) (x)
#define STORAGE_PAD(x) (x) #define STORAGE_PAD(x) (x)
#define STORAGE_OVERLAP(x) 0 #define STORAGE_OVERLAP(x) 0

4
firmware/target/arm/s5l8700/system-target.h
View file

@ -29,10 +29,8 @@
#define CPUFREQ_NORMAL 47923200 #define CPUFREQ_NORMAL 47923200
#define CPUFREQ_MAX 191692800 #define CPUFREQ_MAX 191692800
/* DMA engine needs aligned addresses */
#define PROC_NEEDS_CACHEALIGN
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
#define NEEDS_STORAGE_ALIGN #define WANTS_STORAGE_ALIGN
#define inl(a) (*(volatile unsigned long *) (a)) #define inl(a) (*(volatile unsigned long *) (a))
#define outl(a,b) (*(volatile unsigned long *) (b) = (a)) #define outl(a,b) (*(volatile unsigned long *) (b) = (a))

2
firmware/target/arm/system-target.h
View file

@ -164,7 +164,7 @@ static inline void wake_core(int core)
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
#if defined(CPU_PP502x) && defined(HAVE_ATA_DMA) #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA)
#define NEEDS_STORAGE_ALIGN #define STORAGE_WANTS_ALIGN
#endif #endif
/** cache functions **/ /** cache functions **/