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Forgot that the X5/M5 use a 64/64KB IRAM split, so they can't use the previous optimization.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17854 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Giacomelli 2008-06-28 19:21:38 +00:00
parent a06f651c3e
commit b50b38ae58

View file

@ -56,8 +56,8 @@
/*define IRAM for targets with 48k/80k IRAM split*/
#ifndef IBSS_ATTR_WMA_LARGE_IRAM
#if (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) || (CONFIG_CPU == MCF5250)
/* PP5022/24 and MCF5250 have 128KB of IRAM, with 80KB allocated for codecs */
#if (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
/* PP5022/24 and MCF5250 have 128KB of IRAM, but only PP5022+ have 80KB allocated for codecs */
#define IBSS_ATTR_WMA_LARGE_IRAM IBSS_ATTR
#else
/* other PP's and MCF5249 have 96KB of IRAM */