Move SH7034 timer code in the target tree

Add an argument int_prio to TIMER_START() macro because SH7034 needs it
Leaves a target specific code in timer_register (could be given to target code through timer_set and __timer_set() )

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21556 a1c6a512-1295-4272-9138-f99709370657

firmware/SOURCES

@@ -461,6 +461,7 @@ drivers/i2c.c
 #ifdef ARCHOS_PLAYER
 #ifndef SIMULATOR
 target/sh/archos/ata-archos.c
+target/sh/archos/timer-archos.c
 target/sh/archos/ata-as-archos.S
 target/sh/archos/player/button-player.c
 target/sh/archos/player/hwcompat-player.c
@@ -475,6 +476,7 @@ target/sh/archos/player/usb-player.c
 #ifdef ARCHOS_RECORDER
 #ifndef SIMULATOR
 target/sh/archos/ata-archos.c
+target/sh/archos/timer-archos.c
 target/sh/archos/ata-as-archos.S
 target/sh/archos/lcd-archos-bitmap.c
 target/sh/archos/lcd-as-archos-bitmap.S   
@@ -488,6 +490,7 @@ target/sh/archos/recorder/usb-recorder.c
 #if defined(ARCHOS_FMRECORDER) || defined(ARCHOS_RECORDERV2)
 #ifndef SIMULATOR
 target/sh/archos/ata-archos.c
+target/sh/archos/timer-archos.c
 target/sh/archos/ata-as-archos.S
 target/sh/archos/lcd-archos-bitmap.c
 target/sh/archos/lcd-as-archos-bitmap.S

firmware/export/timer.h

@@ -31,11 +31,13 @@
 #elif CONFIG_CPU == S3C2440 || CONFIG_CPU == DM320 || CONFIG_CPU == TCC7801 \
       || defined(CPU_TCC77X) || CONFIG_CPU == AS3525 || CONFIG_CPU == IMX31L \
       || CONFIG_CPU == JZ4732 || CONFIG_CPU == PNX0101 \
-      || defined(CPU_COLDFIRE)
+      || defined(CPU_COLDFIRE) || CONFIG_CPU == SH7034
  #include "timer-target.h"
 #elif defined(SIMULATOR)
  #define TIMER_FREQ 1000000
-#else
+#endif
+
+#ifndef TIMER_FREQ
  #define TIMER_FREQ CPU_FREQ
 #endif
 bool timer_register(int reg_prio, void (*unregister_callback)(void),

firmware/target/arm/as3525/timer-target.h

@@ -30,7 +30,7 @@ void __timer_stop(void);
 #define __TIMER_SET(cycles, set) \
     __timer_set(cycles, set)
 
-#define __TIMER_START() \
+#define __TIMER_START(int_prio) \
     __timer_start()
 
 #define __TIMER_STOP(...) \

firmware/target/arm/at91sam/lyre_proto1/timer-target.h

@@ -32,7 +32,7 @@ void __timer_stop(void);
 #define __TIMER_SET(cycles, set) \
     __timer_set(cycles, set)
 
-#define __TIMER_START() \
+#define __TIMER_START(int_prio) \
     __timer_start()
 
 #define __TIMER_STOP(...) \

firmware/target/arm/imx31/gigabeat-s/timer-target.h

@@ -31,7 +31,7 @@ void _timer_stop(void);
 #define __TIMER_SET(cycles, set) \
     _timer_set(cycles, set)
 
-#define __TIMER_START() \
+#define __TIMER_START(int_prio) \
     _timer_start()
 
 #define __TIMER_STOP(...) \

firmware/target/arm/pnx0101/timer-target.h

@@ -30,7 +30,7 @@ void __timer_stop(void);
 #define __TIMER_SET(cycles, set) \
     __timer_set(cycles, set)
 
-#define __TIMER_START() \
+#define __TIMER_START(int_prio) \
     __timer_start()
 
 #define __TIMER_STOP(...) \

firmware/target/arm/s3c2440/gigabeat-fx/timer-target.h

@@ -32,7 +32,7 @@ void __timer_stop(void);
 #define __TIMER_SET(cycles, set) \
     __timer_set(cycles, set)
 
-#define __TIMER_START() \
+#define __TIMER_START(int_prio) \
     __timer_start()
 
 #define __TIMER_STOP(...) \

firmware/target/arm/tcc780x/timer-target.h

@@ -31,7 +31,7 @@ void __timer_stop(void);
 #define __TIMER_SET(cycles, set) \
     __timer_set(cycles, set)
 
-#define __TIMER_START() \
+#define __TIMER_START(int_prio) \
     __timer_start()
 
 #define __TIMER_STOP(...) \

firmware/target/arm/tms320dm320/timer-target.h

@@ -31,7 +31,7 @@ void __timer_stop(void);
 #define __TIMER_SET(cycles, set) \
     __timer_set(cycles, set)
 
-#define __TIMER_START() \
+#define __TIMER_START(int_prio) \
     __timer_start()
 
 #define __TIMER_STOP(...) \

firmware/target/coldfire/timer-target.h

@@ -31,7 +31,7 @@ void __timer_stop(void);
 #define __TIMER_SET(cycles, set) \
     __timer_set(cycles, set)
 
-#define __TIMER_START() \
+#define __TIMER_START(int_prio) \
     __timer_start()
 
 #define __TIMER_STOP(...) \

firmware/target/mips/ingenic_jz47xx/timer-target.h

@@ -33,7 +33,7 @@ void __timer_stop(void);
 #define __TIMER_SET(cycles, set) \
     __timer_set(cycles, set)
 
-#define __TIMER_START() \
+#define __TIMER_START(int_prio) \
     __timer_start()
 
 #define __TIMER_STOP(...) \

firmware/target/sh/archos/timer-archos.c

@@ -0,0 +1,85 @@
+/***************************************************************************
+*             __________               __   ___.
+*   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+*   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+*   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+*   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+*                     \/            \/     \/    \/            \/
+* $Id$
+*
+* Copyright (C) 2005 Jens Arnold
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+* KIND, either express or implied.
+*
+****************************************************************************/
+
+#include "cpu.h"
+#include "system.h"
+#include "timer.h"
+#include "timer-target.h"
+
+void IMIA4(void) __attribute__((interrupt_handler));
+void IMIA4(void)
+{
+    if (pfn_timer != NULL)
+        pfn_timer();
+    and_b(~0x01, &TSR4); /* clear the interrupt */
+}
+
+bool __timer_set(long cycles, bool start)
+{
+    int phi = 0; /* bits for the prescaler */
+    int prescale = 1;
+
+    while (cycles > 0x10000)
+    {   /* work out the smallest prescaler that makes it fit */
+        phi++;
+        prescale <<= 1;
+        cycles >>= 1;
+    }
+
+    if (prescale > 8)
+        return false;
+
+    if (start)
+    {
+        if (pfn_unregister != NULL)
+        {
+            pfn_unregister();
+            pfn_unregister = NULL;
+        }
+
+        and_b(~0x10, &TSTR); /* Stop the timer 4 */
+        and_b(~0x10, &TSNC); /* No synchronization */
+        and_b(~0x10, &TMDR); /* Operate normally */
+
+        TIER4 = 0xF9;        /* Enable GRA match interrupt */
+    }
+
+    TCR4 = 0x20 | phi;   /* clear at GRA match, set prescaler */
+    GRA4 = (unsigned short)(cycles - 1);
+    if (start || (TCNT4 >= GRA4))
+        TCNT4 = 0;
+    and_b(~0x01, &TSR4); /* clear an eventual interrupt */
+
+    return true;
+}
+
+bool __timer_start(int int_prio)
+{
+    IPRD = (IPRD & 0xFF0F) | int_prio << 4;  /* interrupt priority */
+    or_b(0x10, &TSTR); /* start timer 4 */
+    return true;
+}
+
+void __timer_stop(void)
+{
+    and_b(~0x10, &TSTR);    /* stop the timer 4 */
+    IPRD = (IPRD & 0xFF0F); /* disable interrupt */
+}

firmware/target/sh/archos/timer-target.h

@@ -0,0 +1,41 @@
+/***************************************************************************
+*             __________               __   ___.
+*   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+*   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+*   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+*   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+*                     \/            \/     \/    \/            \/
+* $Id$
+*
+* Copyright (C) 2005 Jens Arnold
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+*
+* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+* KIND, either express or implied.
+*
+****************************************************************************/
+#ifndef TIMER_TARGET_H
+#define TIMER_TARGET_H
+
+#include "config.h"
+
+bool __timer_set(long cycles, bool start);
+bool __timer_start(int int_prio);
+void __timer_stop(void);
+
+#define TIMER_FREQ CPU_FREQ
+
+#define __TIMER_SET(cycles, set) \
+    __timer_set(cycles, set)
+
+#define __TIMER_START(int_prio) \
+    __timer_start(int_prio)
+
+#define __TIMER_STOP(...) \
+    __timer_stop()
+
+#endif /* TIMER_TARGET_H */

firmware/timer.c

@@ -42,15 +42,7 @@ static long SHAREDBSS_ATTR cycles_new = 0;
 #endif
 
 /* interrupt handler */
-#if CONFIG_CPU == SH7034
+#if defined(CPU_PP)
-void IMIA4(void) __attribute__((interrupt_handler));
-void IMIA4(void)
-{
-    if (pfn_timer != NULL)
-        pfn_timer();
-    and_b(~0x01, &TSR4); /* clear the interrupt */
-}
-#elif defined(CPU_PP)
 void TIMER2(void)
 {
     TIMER2_VAL; /* ACK interrupt */
@@ -72,43 +64,7 @@ void TIMER2(void)
 
 static bool timer_set(long cycles, bool start)
 {
-#if CONFIG_CPU == SH7034
+#if defined(CPU_PP)
-    int phi = 0; /* bits for the prescaler */
-    int prescale = 1;
-
-    while (cycles > 0x10000)
-    {   /* work out the smallest prescaler that makes it fit */
-        phi++;
-        prescale <<= 1;
-        cycles >>= 1;
-    }
-
-    if (prescale > 8)
-        return false;
-
-    if (start)
-    {
-        if (pfn_unregister != NULL)
-        {
-            pfn_unregister();
-            pfn_unregister = NULL;
-        }
-
-        and_b(~0x10, &TSTR); /* Stop the timer 4 */
-        and_b(~0x10, &TSNC); /* No synchronization */
-        and_b(~0x10, &TMDR); /* Operate normally */
-
-        TIER4 = 0xF9;        /* Enable GRA match interrupt */
-    }
-
-    TCR4 = 0x20 | phi;   /* clear at GRA match, set prescaler */
-    GRA4 = (unsigned short)(cycles - 1);
-    if (start || (TCNT4 >= GRA4))
-        TCNT4 = 0;
-    and_b(~0x01, &TSR4); /* clear an eventual interrupt */
-
-    return true;
-#elif defined(CPU_PP)
     if (cycles > 0x20000000 || cycles < 2)
         return false;
 
@@ -153,11 +109,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void),
     pfn_unregister = unregister_callback;
     timer_prio = reg_prio;
 
-#if CONFIG_CPU == SH7034
+#if defined(CPU_PP)
-    IPRD = (IPRD & 0xFF0F) | int_prio << 4;  /* interrupt priority */
-    or_b(0x10, &TSTR); /* start timer 4 */
-    return true;
-#elif defined(CPU_PP)
     /* unmask interrupt source */
 #if NUM_CORES > 1
     if (core == COP)
@@ -167,7 +119,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void),
         CPU_INT_EN = TIMER2_MASK;
     return true;
 #else
-    return __TIMER_START();
+    return __TIMER_START(int_prio);
 #endif
     /* Cover for targets that don't use all these */
     (void)reg_prio;
@@ -185,10 +137,7 @@ bool timer_set_period(long cycles)
 
 void timer_unregister(void)
 {
-#if CONFIG_CPU == SH7034
+#if defined(CPU_PP)
-    and_b(~0x10, &TSTR);    /* stop the timer 4 */
-    IPRD = (IPRD & 0xFF0F); /* disable interrupt */
-#elif defined(CPU_PP)
     TIMER2_CFG = 0;         /* stop timer 2 */
     CPU_INT_DIS = TIMER2_MASK;
     COP_INT_DIS = TIMER2_MASK;