forked from len0rd/rockbox
PP502x: Improve accuracy of header file. It looks as though DMA channels share the same interrupt enable (tested that 0 and 2 do at least).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20089 a1c6a512-1295-4272-9138-f99709370657
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2 changed files with 6 additions and 12 deletions
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@ -107,10 +107,7 @@
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#define USB_IRQ 20
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#define IDE_IRQ 23
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#define FIREWIRE_IRQ 25
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#define DMA0_IRQ 26
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#define DMA1_IRQ 27 /* guess */
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#define DMA2_IRQ 28 /* guess */
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#define DMA3_IRQ 29 /* guess */
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#define DMA_IRQ 26
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#define HI_IRQ 30
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#define GPIO0_IRQ (32+0) /* Ports A..D */
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#define GPIO1_IRQ (32+1) /* Ports E..H */
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@ -126,10 +123,7 @@
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#define IDE_MASK (1 << IDE_IRQ)
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#define USB_MASK (1 << USB_IRQ)
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#define FIREWIRE_MASK (1 << FIREWIRE_IRQ)
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#define DMA0_MASK (1 << DMA0_IRQ)
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#define DMA1_MASK (1 << DMA1_IRQ)
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#define DMA2_MASK (1 << DMA2_IRQ)
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#define DMA3_MASK (1 << DMA3_IRQ)
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#define DMA_MASK (1 << DMA_IRQ)
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#define HI_MASK (1 << HI_IRQ)
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#define GPIO0_MASK (1 << (GPIO0_IRQ-32))
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#define GPIO1_MASK (1 << (GPIO1_IRQ-32))
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@ -328,7 +328,7 @@ void pcm_play_lock(void)
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if (++dma_play_data.locked == 1) {
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#ifdef CPU_PP502x
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CPU_INT_DIS = DMA0_MASK;
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CPU_INT_DIS = DMA_MASK;
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#else
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IIS_IRQTX_REG &= ~IIS_IRQTX;
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#endif
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@ -343,7 +343,7 @@ void pcm_play_unlock(void)
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if (--dma_play_data.locked == 0 && dma_play_data.state != 0) {
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#ifdef CPU_PP502x
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CPU_INT_EN = DMA0_MASK;
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CPU_INT_EN = DMA_MASK;
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#else
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IIS_IRQTX_REG |= IIS_IRQTX;
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#endif
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@ -493,8 +493,8 @@ void pcm_play_dma_init(void)
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#ifdef CPU_PP502x
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/* Enable DMA controller */
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DMA_MASTER_CONTROL |= DMA_MASTER_CONTROL_EN;
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/* FIQ priority for DMA0 */
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CPU_INT_PRIORITY |= DMA0_MASK;
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/* FIQ priority for DMA */
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CPU_INT_PRIORITY |= DMA_MASK;
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/* Enable request?? Not setting or clearing everything doesn't seem to
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* prevent it operating. Perhaps important for reliability (how requests
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* are handled). */
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