forked from len0rd/rockbox
RTC s35380a - cleanup and more comments
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28772 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Marcin Bukat
parent
f6297c1f3e
commit
aff90a9db7
1 changed files with 77 additions and 39 deletions
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@ -42,29 +42,25 @@
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#define CLOCK_CORR_REG 6
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#define FREE_REG 7
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/* STATUS_REG1 flags
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* bits order is reversed
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*/
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#define STATUS_REG1_POC 0x01
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#define STATUS_REG1_BLD 0x02
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#define STATUS_REG1_INT2 0x04
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#define STATUS_REG1_INT1 0x08
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#define STATUS_REG1_SC1 0x10
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#define STATUS_REG1_SC0 0x20
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#define STATUS_REG1_H1224 0x40
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#define STATUS_REG1_RESET 0x80
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/* STATUS_REG1 flags */
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#define STATUS_REG1_POC 0x80
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#define STATUS_REG1_BLD 0x40
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#define STATUS_REG1_INT2 0x20
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#define STATUS_REG1_INT1 0x10
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#define STATUS_REG1_SC1 0x08
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#define STATUS_REG1_SC0 0x04
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#define STATUS_REG1_H1224 0x02
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#define STATUS_REG1_RESET 0x01
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/* STATUS_REG2 flags
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* bits order is reversed
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*/
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#define STATUS_REG2_TEST 0x01
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#define STATUS_REG2_INT2AE 0x02
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#define STATUS_REG2_INT2ME 0x04
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#define STATUS_REG2_INT2FE 0x08
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#define STATUS_REG2_32kE 0x10
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#define STATUS_REG2_INT1AE 0x20
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#define STATUS_REG2_INT1ME 0x40
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#define STATUS_REG2_INT1FE 0x80
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/* STATUS_REG2 flags */
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#define STATUS_REG2_TEST 0x80
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#define STATUS_REG2_INT2AE 0x40
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#define STATUS_REG2_INT2ME 0x20
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#define STATUS_REG2_INT2FE 0x10
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#define STATUS_REG2_32kE 0x08
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#define STATUS_REG2_INT1AE 0x04
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#define STATUS_REG2_INT1ME 0x02
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#define STATUS_REG2_INT1FE 0x01
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/* REALTIME_DATA register bytes */
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#define TIME_YEAR 0
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@ -95,6 +91,9 @@
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static bool int_flag;
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/* s35380a chip has reversed bits order in byte
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* This is little helper function to deal with
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*/
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static void reverse_bits(unsigned char* v, int size)
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{
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static const unsigned char flipnibble[] =
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@ -108,12 +107,40 @@ static void reverse_bits(unsigned char* v, int size)
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}
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}
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/* Read 'size' bytes from RTC 'reg' and put data in 'buf'
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* bits are reversed in data bytes afterwards so they appear in regular order
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* return i2c transfer code
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*/
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static int rtc_read(unsigned char reg, unsigned char *buf, int size)
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{
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int rc;
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rc = i2c_read(I2C_IFACE_1, RTC_ADDR|(reg<<1), buf, size);
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reverse_bits(buf, size);
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return rc;
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}
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/* Write 'size' bytes to RTC 'reg' and put data in 'buf'
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* bits are reversed in data bytes prior to sending them to RTC
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* return i2c transfer code
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*/
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static int rtc_write(unsigned char reg, unsigned char *buf, int size)
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{
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int rc;
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reverse_bits(buf, size);
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rc = i2c_write(I2C_IFACE_1, RTC_ADDR|(reg<<1), buf, size);
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return rc;
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}
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/* Reset RTC by writing '1' to RESET bit in STATUS_REG1 */
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static inline void rtc_reset(void)
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{
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unsigned char reg = STATUS_REG1_RESET;
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i2c_write(I2C_IFACE_1, RTC_ADDR|(STATUS_REG1<<1), ®, 1);
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rtc_write(STATUS_REG1, ®, 1);
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}
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/* Initialize RTC (according to scheme outlined in datasheet).
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* Configure chip to 24h time format.
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*/
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void rtc_init(void)
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{
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unsigned char reg;
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@ -122,7 +149,7 @@ void rtc_init(void)
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if ( initialized )
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return;
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i2c_read(I2C_IFACE_1, RTC_ADDR|(STATUS_REG1<<1), ®, 1);
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rtc_read(STATUS_REG1, ®, 1);
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/* cache INT1, INT2 flags as reading the register seem to clear
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* this bits (which is not described in datasheet)
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@ -133,7 +160,7 @@ void rtc_init(void)
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if ( (reg & STATUS_REG1_POC) || (reg & STATUS_REG1_BLD))
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rtc_reset();
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i2c_read(I2C_IFACE_1, RTC_ADDR|(STATUS_REG2<<1), ®, 1);
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rtc_read(STATUS_REG2, ®, 1);
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/* test TEST flag */
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if ( reg & STATUS_REG2_TEST )
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@ -141,19 +168,19 @@ void rtc_init(void)
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/* setup 24h time format */
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reg = STATUS_REG1_H1224;
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i2c_write(I2C_IFACE_1, RTC_ADDR|(STATUS_REG1<<1), ®, 1);
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rtc_write(STATUS_REG1, ®, 1);
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initialized = true;
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}
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/* Read realtime data register */
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int rtc_read_datetime(struct tm *tm)
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{
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unsigned char buf[TIME_REG_SIZE];
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unsigned int i;
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int ret;
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ret = i2c_read(I2C_IFACE_1, RTC_ADDR|(REALTIME_DATA1<<1), buf, sizeof(buf));
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reverse_bits(buf, sizeof(buf));
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ret = rtc_read(REALTIME_DATA1, buf, sizeof(buf));
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buf[TIME_HOUR] &= 0x3f; /* mask out p.m. flag */
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@ -171,6 +198,7 @@ int rtc_read_datetime(struct tm *tm)
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return ret;
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}
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/* Write to realtime data register */
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int rtc_write_datetime(const struct tm *tm)
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{
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unsigned char buf[TIME_REG_SIZE];
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@ -188,13 +216,13 @@ int rtc_write_datetime(const struct tm *tm)
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for (i = 0; i < sizeof(buf); i++)
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buf[i] = DEC2BCD(buf[i]);
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reverse_bits(buf, sizeof(buf));
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ret = i2c_write(I2C_IFACE_1, RTC_ADDR|(REALTIME_DATA1<<1), buf, sizeof(buf));
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ret = rtc_write(REALTIME_DATA1, buf, sizeof(buf));
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return ret;
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}
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#ifdef HAVE_RTC_ALARM
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/* Set alarm (INT1) data register */
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void rtc_set_alarm(int h, int m)
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{
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unsigned char buf[ALARM_REG_SIZE];
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@ -207,7 +235,7 @@ void rtc_set_alarm(int h, int m)
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buf[ALARM_HOUR] = DEC2BCD(h) | A1HE;
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buf[ALARM_WEEKDAY] = 0;
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/* AM/PM flag have to be set properly regardles of
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/* AM/PM flag has to be set properly regardles of
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* time format used (H1224 flag in STATUS_REG1)
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* this is not described in datasheet for s35380a
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* but is somehow described in datasheet for s35390a
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@ -215,10 +243,10 @@ void rtc_set_alarm(int h, int m)
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if ( h >= 12 )
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buf[ALARM_HOUR] |= AMPM;
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reverse_bits(buf, sizeof(buf));
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i2c_write(I2C_IFACE_1, RTC_ADDR|(INT1_REG<<1), buf, sizeof(buf));
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rtc_write(INT1_REG, buf, sizeof(buf));
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}
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/* Read alarm (INT1) data register */
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void rtc_get_alarm(int *h, int *m)
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{
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unsigned char buf[ALARM_REG_SIZE];
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@ -227,23 +255,32 @@ void rtc_get_alarm(int *h, int *m)
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rtc_enable_alarm(true);
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/* read the content of INT1 register */
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i2c_read(I2C_IFACE_1, RTC_ADDR|(INT1_REG<<1), buf, sizeof(buf));
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reverse_bits(buf, sizeof(buf));
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rtc_read(INT1_REG, buf, sizeof(buf));
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*h = BCD2DEC(buf[ALARM_HOUR] & 0x3f); /* mask out A1HE and PM/AM flag */
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*m = BCD2DEC(buf[ALARM_MINUTE] & 0x7f); /* mask out A1mE */
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*h = BCD2DEC(buf[ALARM_HOUR] & 0x3f); /* mask out A1HE and PM/AM bits */
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*m = BCD2DEC(buf[ALARM_MINUTE] & 0x7f); /* mask out A1mE bit */
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/* Disable alarm - this is not strictly needed in rockbox
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* as after rtc_get_alarm() rtc_set_alarm() or rtc_enable_alarm(false)
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* are called. I just found this weird that simple reading register
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* changes alarm settings.
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*/
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rtc_enable_alarm(false);
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}
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/* Check if we just triggered alarm.
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* We check both INT1 and INT2. Rockbox uses only INT1 but
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* OF in MPIO HD300 uses both
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*/
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bool rtc_check_alarm_flag(void)
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{
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unsigned char reg;
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i2c_read(I2C_IFACE_1, RTC_ADDR|(STATUS_REG1<<1), ®, 1);
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rtc_read(STATUS_REG1, ®, 1);
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return ((reg & STATUS_REG1_INT1) || (reg & STATUS_REG1_INT2));
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}
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/* Enable/disable alarm function */
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void rtc_enable_alarm(bool enable)
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{
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unsigned char reg = 0;
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@ -251,9 +288,10 @@ void rtc_enable_alarm(bool enable)
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if (enable)
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reg = STATUS_REG2_INT1AE;
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i2c_write(I2C_IFACE_1, RTC_ADDR|(STATUS_REG2<<1), ®, 1);
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rtc_write(STATUS_REG2, ®, 1);
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}
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/* Return true if wakeup is due to RTC alarm */
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bool rtc_check_alarm_started(bool release_alarm)
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{
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static bool run_before;
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