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as3525v2: document PLL bits and show current PLL frequency in the debug menu

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26930 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Bertrik Sikken 2010-06-18 18:32:38 +00:00
parent 3e690ac60d
commit ae64b59afa
2 changed files with 27 additions and 4 deletions
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12
firmware/target/arm/as3525/clock-target.h
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@ -62,10 +62,20 @@
#if CONFIG_CPU == AS3525v2
/* PLLA & PLLB registers differ from AS3525(v1)
* so we use a setting with a known frequency */
* PLL bits:
* - bit 0-6 = F-1 (F=multiplier)
* - bit 7-9 = R-1 (R=divisor)
* - bit 10 = OD (output divider)? Divides by 2 if set.
* - bit 11 = unknown (no effect)
* - bit 12 = unknown (always set to 1)
* Fpll = Fin * F / (R * OD), where Fin = 12 MHz
*/
#define AS3525_PLLA_FREQ 240000000
#define AS3525_PLLA_SETTING 0x113B
#define AS3525_PLLB_FREQ 192000000
#define AS3525_PLLB_SETTING 0x155F
#define AS3525_FCLK_PREDIV 0
#define AS3525_FCLK_FREQ AS3525_PLLA_FREQ

19
firmware/target/arm/as3525/debug-as3525.c
View file

@ -112,14 +112,27 @@ static int calc_freq(int clk)
(((CGU_PLLB>>8) & 0x1f)*out_div);
return 0;
#else
int od, f, r;
/* AS3525v2 */
switch(clk) {
/* we're using a known setting for PLLA = 240 MHz and PLLB inop */
case CLK_PLLA:
return 240000000;
if(CGU_PLLASUP & (1<<3))
return 0;
f = (CGU_PLLA & 0x7F) + 1;
r = ((CGU_PLLA >> 7) & 0x7) + 1;
od = (CGU_PLLA >> 10) & 1 ? 2 : 1;
return (CLK_MAIN / 2) * f / (r * od);
case CLK_PLLB:
return 0;
if(CGU_PLLBSUP & (1<<3))
return 0;
f = (CGU_PLLB & 0x7F) + 1;
r = ((CGU_PLLB >> 7) & 0x7) + 1;
od = (CGU_PLLB >> 10) & 1 ? 2 : 1;
return (CLK_MAIN / 2) * f / (r * od);
#endif
case CLK_PROC:
#if CONFIG_CPU == AS3525 /* not in arm926-ejs */