forked from len0rd/rockbox
as3525v2: document PLL bits and show current PLL frequency in the debug menu
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26930 a1c6a512-1295-4272-9138-f99709370657
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2 changed files with 27 additions and 4 deletions
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@ -62,10 +62,20 @@
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#if CONFIG_CPU == AS3525v2
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#if CONFIG_CPU == AS3525v2
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/* PLLA & PLLB registers differ from AS3525(v1)
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/* PLLA & PLLB registers differ from AS3525(v1)
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* so we use a setting with a known frequency */
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* PLL bits:
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* - bit 0-6 = F-1 (F=multiplier)
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* - bit 7-9 = R-1 (R=divisor)
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* - bit 10 = OD (output divider)? Divides by 2 if set.
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* - bit 11 = unknown (no effect)
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* - bit 12 = unknown (always set to 1)
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* Fpll = Fin * F / (R * OD), where Fin = 12 MHz
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*/
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#define AS3525_PLLA_FREQ 240000000
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#define AS3525_PLLA_FREQ 240000000
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#define AS3525_PLLA_SETTING 0x113B
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#define AS3525_PLLA_SETTING 0x113B
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#define AS3525_PLLB_FREQ 192000000
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#define AS3525_PLLB_SETTING 0x155F
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#define AS3525_FCLK_PREDIV 0
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#define AS3525_FCLK_PREDIV 0
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#define AS3525_FCLK_FREQ AS3525_PLLA_FREQ
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#define AS3525_FCLK_FREQ AS3525_PLLA_FREQ
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@ -112,14 +112,27 @@ static int calc_freq(int clk)
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(((CGU_PLLB>>8) & 0x1f)*out_div);
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(((CGU_PLLB>>8) & 0x1f)*out_div);
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return 0;
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return 0;
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#else
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#else
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int od, f, r;
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/* AS3525v2 */
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/* AS3525v2 */
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switch(clk) {
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switch(clk) {
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/* we're using a known setting for PLLA = 240 MHz and PLLB inop */
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case CLK_PLLA:
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case CLK_PLLA:
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return 240000000;
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if(CGU_PLLASUP & (1<<3))
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return 0;
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f = (CGU_PLLA & 0x7F) + 1;
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r = ((CGU_PLLA >> 7) & 0x7) + 1;
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od = (CGU_PLLA >> 10) & 1 ? 2 : 1;
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return (CLK_MAIN / 2) * f / (r * od);
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case CLK_PLLB:
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case CLK_PLLB:
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return 0;
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if(CGU_PLLBSUP & (1<<3))
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return 0;
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f = (CGU_PLLB & 0x7F) + 1;
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r = ((CGU_PLLB >> 7) & 0x7) + 1;
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od = (CGU_PLLB >> 10) & 1 ? 2 : 1;
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return (CLK_MAIN / 2) * f / (r * od);
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#endif
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#endif
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case CLK_PROC:
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case CLK_PROC:
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#if CONFIG_CPU == AS3525 /* not in arm926-ejs */
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#if CONFIG_CPU == AS3525 /* not in arm926-ejs */
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