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Enable dualcore for the pp5002 processor by adding the needed cache handling and sleep/wakeup sync to the kernel. Refine some handling of fw/bl startup for all.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15827 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2007-11-27 01:20:26 +00:00
parent 0ade09bd6b
commit a8b388fb86
8 changed files with 362 additions and 146 deletions
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18
firmware/target/arm/system-target.h
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@ -77,7 +77,7 @@ static inline unsigned int current_core(void)
/* Return the actual ID instead of core index */
static inline unsigned int processor_id(void)
{
unsigned char id;
unsigned int id;
asm volatile (
"ldrb %0, [%1] \n"
@ -92,12 +92,18 @@ static inline unsigned int processor_id(void)
/* All addresses within rockbox are in IRAM in the bootloader so
are therefore uncached */
#define UNCACHED_ADDR(a) (a)
#else
#define UNCACHED_ADDR(a) \
((typeof (a))((uintptr_t)(a) | 0x10000000))
#else /* !BOOTLOADER */
#if CONFIG_CPU == PP5002
#define UNCACHED_BASE_ADDR 0x28000000
#else /* PP502x */
#define UNCACHED_BASE_ADDR 0x10000000
#endif
#ifdef CPU_PP502x
#define UNCACHED_ADDR(a) \
((typeof (a))((uintptr_t)(a) | UNCACHED_BASE_ADDR))
#endif /* BOOTLOADER */
/* Certain data needs to be out of the way of cache line interference
* such as data for COP use or for use with UNCACHED_ADDR */
@ -115,8 +121,6 @@ void invalidate_icache(void);
void flush_icache(void);
#endif
#endif /* CPU_PP502x */
#endif /* CPU_PP */
#endif /* SYSTEM_TARGET_H */