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Enable IRAM on TCC7801 (Cowon D2) for a 6-12% speedup in codecs that use it, and a small increase in battery life.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26436 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rob Purchase 2010-05-31 21:00:25 +00:00
parent 64adb32cbf
commit a6c1b54d46
4 changed files with 11 additions and 10 deletions

View file

@ -120,10 +120,13 @@ OUTPUT_FORMAT(elf32-littlemips)
#elif defined(CPU_TCC780X) || defined(CPU_TCC77X) #elif defined(CPU_TCC780X) || defined(CPU_TCC77X)
#define DRAMORIG 0x20000000 #define DRAMORIG 0x20000000
/*#define IRAMORIG 0x1000c000 #if CONFIG_CPU==TCC7801
#define IRAMSIZE 0xc000*/ #define IRAMORIG 0x1000c000
#define IRAMSIZE 0xc000
#else
#define IRAM DRAM #define IRAM DRAM
#define IRAMSIZE 0 #define IRAMSIZE 0
#endif
#elif CONFIG_CPU==AS3525 || CONFIG_CPU==AS3525v2 #elif CONFIG_CPU==AS3525 || CONFIG_CPU==AS3525v2
#if defined(AMS_LOWMEM) || (CONFIG_CPU == AS3525v2) #if defined(AMS_LOWMEM) || (CONFIG_CPU == AS3525v2)

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@ -727,6 +727,7 @@ Lyre prototype 1 */
(CONFIG_CPU == AS3525 && MEMORYSIZE <= 2 && !defined(PLUGIN) && !defined(CODEC)) || /* AS3525 2MB: core only */ \ (CONFIG_CPU == AS3525 && MEMORYSIZE <= 2 && !defined(PLUGIN) && !defined(CODEC)) || /* AS3525 2MB: core only */ \
(CONFIG_CPU == AS3525v2 && !defined(PLUGIN) && !defined(CODEC)) || /* AS3525v2: core only */ \ (CONFIG_CPU == AS3525v2 && !defined(PLUGIN) && !defined(CODEC)) || /* AS3525v2: core only */ \
(CONFIG_CPU == PNX0101) || \ (CONFIG_CPU == PNX0101) || \
(CONFIG_CPU == TCC7801) || \
defined(CPU_S5L870X)) || /* Samsung S5L8700: core, plugins, codecs */ \ defined(CPU_S5L870X)) || /* Samsung S5L8700: core, plugins, codecs */ \
(CONFIG_CPU == JZ4732 && !defined(PLUGIN) && !defined(CODEC)) /* Jz4740: core only */ (CONFIG_CPU == JZ4732 && !defined(PLUGIN) && !defined(CODEC)) /* Jz4740: core only */
#define ICODE_ATTR __attribute__ ((section(".icode"))) #define ICODE_ATTR __attribute__ ((section(".icode")))

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@ -116,8 +116,7 @@ SECTIONS
*(.icode) *(.icode)
. = ALIGN(0x4); . = ALIGN(0x4);
_iramend = .; _iramend = .;
/* } > SRAM AT> DRAM */ } > SRAM AT> DRAM
} > DRAM
_iramcopy = LOADADDR(.iram); _iramcopy = LOADADDR(.iram);
@ -127,8 +126,7 @@ SECTIONS
*(.ibss) *(.ibss)
. = ALIGN(0x4); . = ALIGN(0x4);
_iend = .; _iend = .;
/* } > SRAM */ } > SRAM
} > DRAM
.stack : .stack :
{ {
@ -136,8 +134,7 @@ SECTIONS
stackbegin = .; stackbegin = .;
. += 0x2000; . += 0x2000;
stackend = .; stackend = .;
/* } > SRAM */ } > SRAM
} > DRAM
.bss : .bss :
{ {

View file

@ -155,8 +155,8 @@ copied_start:
ldr r0, =0x8001eec0 /* Region 6: 0x80000000-0xffffffff (2Gb) */ ldr r0, =0x8001eec0 /* Region 6: 0x80000000-0xffffffff (2Gb) */
str r0, [r1,#0x18] /* AP: 3 EN: 1 DO: 6 CACHE_NONE */ str r0, [r1,#0x18] /* AP: 3 EN: 1 DO: 6 CACHE_NONE */
ldr r0, =0x1001aee0 /* Region 7: 0x10000000-0x17ffffff (128Mb) */ ldr r0, =0x1001aeec /* Region 7: 0x10000000-0x17ffffff (128Mb) */
str r0, [r1,#0x1c] /* AP: 3 EN: 1 DO: 7 CACHE_NONE */ str r0, [r1,#0x1c] /* AP: 3 EN: 1 DO: 7 CACHE_ALL */
add r1, r1, #0x8000 add r1, r1, #0x8000
mcr p15, 0, r1, c2, c0, 0 /* Set TTBR = TABBASE (Virtual TLB) */ mcr p15, 0, r1, c2, c0, 0 /* Set TTBR = TABBASE (Virtual TLB) */