forked from len0rd/rockbox
Onda VX747:
* Add YUV support * Clean up LCD driver a bit and speed it up git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20730 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere
parent
14a510aff2
commit
a54e0b6dba
5 changed files with 177 additions and 105 deletions
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@ -1305,10 +1305,10 @@
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#define ICDC_CDCCR1_SUSPD (1 << 1)
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#define ICDC_CDCCR1_RST (1 << 0)
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#define ICDC_CDCCR2_AINVOL(n) ((n & 5) << 16)
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#define ICDC_CDCCR2_SMPR(n) ((n & 4) << 8)
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#define ICDC_CDCCR2_MICBG(n) ((n & 2) << 4)
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#define ICDC_CDCCR2_HPVOL(n) ((n & 2) << 0)
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#define ICDC_CDCCR2_AINVOL(n) ((n & 0x1F) << 16)
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#define ICDC_CDCCR2_SMPR(n) ((n & 0xF) << 8)
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#define ICDC_CDCCR2_MICBG(n) ((n & 0x3) << 4)
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#define ICDC_CDCCR2_HPVOL(n) ((n & 0x3) << 0)
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#define ICDC_CDCCR2_AINVOL_DB(n) ((n+34.5)/1.5)
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@ -1423,7 +1423,7 @@
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#define SSI_CR1_MULTS (1 << 22)
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#define SSI_CR1_FMAT_BIT 20
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#define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
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#define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
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#define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
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#define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
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#define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
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#define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
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@ -4984,7 +4984,7 @@ do{ \
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// IPU_REG_BASE
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#define IPU_P_BASE 0x13080000
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#define IPU__OFFSET 0x13080000
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#define IPU_V_BASE 0xB3080000
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#define IPU__SIZE 0x00001000
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struct ipu_module
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@ -5069,10 +5069,12 @@ struct Ration2m
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#define INFMT_YCbCr422 (5 << 0)
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#define INFMT_YCbCr444 (6 << 0)
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#define INFMT_YCbCr411 (7 << 0)
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#define INFMT_MASK (7)
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#define OUTFMT_RGB555 (0 << 16)
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#define OUTFMT_RGB565 (1 << 16)
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#define OUTFMT_RGB888 (2 << 16)
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#define OUTFMT_MASK (3 << 16)
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// REG_IN_FM_GS field define
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#define IN_FM_W(val) ((val) << 16)
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@ -5086,7 +5088,6 @@ struct Ration2m
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#define U_STRIDE(val) ((val) << 16)
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#define V_STRIDE(val) ((val) << 0)
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#define VE_IDX_SFT 0
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#define HE_IDX_SFT 16
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@ -5099,53 +5100,106 @@ struct Ration2m
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#define W_COEF_MSK 0xFF
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// function about REG_CTRL
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#define IPU_STOP_IPU(IPU_V_BASE) \
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#define IPU_STOP_IPU() \
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REG32(IPU_V_BASE + REG_CTRL) &= ~IPU_EN;
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#define IPU_RUN_IPU(IPU_V_BASE) \
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#define IPU_RUN_IPU() \
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REG32(IPU_V_BASE + REG_CTRL) |= IPU_EN;
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#define IPU_RESET_IPU(IPU_V_BASE) \
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#define IPU_RESET_IPU() \
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REG32(IPU_V_BASE + REG_CTRL) |= IPU_RESET;
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#define IPU_DISABLE_IRQ(IPU_V_BASE) \
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#define IPU_DISABLE_IRQ() \
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REG32(IPU_V_BASE + REG_CTRL) &= ~FM_IRQ_EN;
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#define IPU_DISABLE_RSIZE(IPU_V_BASE) \
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#define IPU_DISABLE_RSIZE() \
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REG32(IPU_V_BASE + REG_CTRL) &= ~RSZ_EN;
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#define IPU_ENABLE_RSIZE(IPU_V_BASE) \
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#define IPU_ENABLE_RSIZE() \
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REG32(IPU_V_BASE + REG_CTRL) |= RSZ_EN;
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#define IPU_IS_ENABLED(IPU_V_BASE) \
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#define IPU_IS_ENABLED() \
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(REG32(IPU_V_BASE + REG_CTRL) & IPU_EN)
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// function about REG_STATUS
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#define IPU_CLEAR_END_FLAG(IPU_V_BASE) \
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#define IPU_CLEAR_END_FLAG() \
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REG32(IPU_V_BASE + REG_STATUS) &= ~OUT_END;
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#define IPU_POLLING_END_FLAG(IPU_V_BASE) \
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#define IPU_POLLING_END_FLAG() \
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(REG32(IPU_V_BASE + REG_STATUS) & OUT_END)
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#define IPU_SET_INFMT(fmt) \
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REG32(IPU_V_BASE + REG_D_FMT) = (REG32(IPU_V_BASE + REG_D_FMT) & ~INFMT_MASK) | (fmt);
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#define IPU_SET_OUTFMT(fmt) \
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REG32(IPU_V_BASE + REG_D_FMT) = (REG32(IPU_V_BASE + REG_D_FMT) & ~OUTFMT_MASK) | (fmt);
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#define IPU_SET_IN_FM(w, h) \
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REG32(IPU_V_BASE + REG_IN_FM_GS) = IN_FM_W(w) | IN_FM_H(h);
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#define IPU_SET_Y_STRIDE(stride) \
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REG32(IPU_V_BASE + REG_Y_STRIDE) = (stride);
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#define IPU_SET_UV_STRIDE(u, v) \
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REG32(IPU_V_BASE + REG_UV_STRIDE) = U_STRIDE(u) | V_STRIDE(v);
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#define IPU_SET_Y_ADDR(addr) \
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REG32(IPU_V_BASE + REG_Y_ADDR) = (addr);
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#define IPU_SET_U_ADDR(addr) \
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REG32(IPU_V_BASE + REG_U_ADDR) = (addr);
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#define IPU_SET_V_ADDR(addr) \
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REG32(IPU_V_BASE + REG_V_ADDR) = (addr);
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#define IPU_SET_OUT_ADDR(addr) \
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REG32(IPU_V_BASE + REG_OUT_ADDR) = (addr);
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#define IPU_SET_OUT_FM(w, h) \
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REG32(IPU_V_BASE + REG_OUT_GS) = OUT_FM_W(w) | OUT_FM_H(h);
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#define IPU_SET_OUT_STRIDE(stride) \
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REG32(IPU_V_BASE + REG_OUT_STRIDE) = (stride);
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#define IPU_SET_CSC_C0_COEF(coef) \
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REG32(IPU_V_BASE + REG_CSC_C0_COEF) = (coef);
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#define IPU_SET_CSC_C1_COEF(coef) \
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REG32(IPU_V_BASE + REG_CSC_C1_COEF) = (coef);
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#define IPU_SET_CSC_C2_COEF(coef) \
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REG32(IPU_V_BASE + REG_CSC_C2_COEF) = (coef);
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#define IPU_SET_CSC_C3_COEF(coef) \
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REG32(IPU_V_BASE + REG_CSC_C3_COEF) = (coef);
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#define IPU_SET_CSC_C4_COEF(coef) \
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REG32(IPU_V_BASE + REG_CSC_C4_COEF) = (coef);
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/* YCbCr */
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/* parameter
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R = 1.164 * (Y - 16) + 1.596 * (cr - 128) {C0, C1}
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G = 1.164 * (Y - 16) - 0.392 * (cb -128) - 0.813 * (cr - 128) {C0, C2, C3}
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B = 1.164 * (Y - 16) + 2.017 * (cb - 128) {C0, C4}
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*/
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#define YCBCR_CSC_C0 0x4A8 /* 1.164 * 1024 */
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#define YCBCR_CSC_C1 0x662 /* 1.596 * 1024 */
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#define YCBCR_CSC_C2 0x191 /* 0.392 * 1024 */
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#define YCBCR_CSC_C3 0x341 /* 0.813 * 1024 */
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#define YCBCR_CSC_C4 0x811 /* 2.017 * 1024 */
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#if 1
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#define YUV_CSC_C0 0x4A8 /* 1.164 * 1024 */
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#define YUV_CSC_C1 0x662 /* 1.596 * 1024 */
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#define YUV_CSC_C2 0x191 /* 0.392 * 1024 */
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#define YUV_CSC_C3 0x341 /* 0.813 * 1024 */
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#define YUV_CSC_C4 0x811 /* 2.017 * 1024 */
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#else
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/* YUV */
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/* parameter
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R = 1 * (Y – 0) + 1.4026 * (V - 128) {C0, C1}
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G = 1 * (Y – 0) – 0.3444 * (U - 128) – 0.7144 * (V - 128) {C0, C2, C3}
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B = 1 * (Y – 0) + 1.7730 * (U - 128) {C0, C4}
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*/
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#define YUV_CSC_C0 0x400
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#define YUV_CSC_C1 0x59C
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#define YUV_CSC_C2 0x161
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#define YUV_CSC_C3 0x2DC
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#define YUV_CSC_C4 0x718
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#endif
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#endif /* _IPU_H_ */
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