forked from len0rd/rockbox
Ported interrupt vector handling to Coldfire
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@5285 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Linus Nielsen Feltzing
parent
82fb2ace77
commit
a5117f0bb6
2 changed files with 176 additions and 3 deletions
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@ -18,7 +18,181 @@
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****************************************************************************/
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#include <stdio.h>
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#include "config.h"
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#include <stdbool.h>
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#if CONFIG_CPU == MCF5249
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIE"))) void name (void);
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static const char* const irqname[] = {
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"", "", "AccessErr","AddrErr","IllInstr", "", "","",
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"PrivVio","Trace","Line-A", "Line-F","Debug","","FormErr","Uninit",
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"","","","","","","","",
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"Spurious","Level1","Level2","Level3","Level4","Level5","Level6","Level7",
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"Trap0","Trap1","Trap2","Trap3","Trap4","Trap5","Trap6","Trap7",
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"Trap8","Trap9","Trap10","Trap11","Trap12","Trap13","Trap14","Trap15",
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"SWT","Timer0","Timer1","I2C","UART1","UART2","DMA0","DMA1",
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"DMA2","DMA3","QSPI","","","","","",
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"PDIR1FULL","PDIR2FULL","EBUTXEMPTY","IIS2TXEMPTY",
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"IIS1TXEMPTY","PDIR3FULL","PDIR3RESYN","UQ2CHANERR",
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"AUDIOTICK","PDIR2RESYN","PDIR2UNOV","PDIR1RESYN",
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"PDIR1UNOV","UQ1CHANERR","IEC2BUFATTEN","IEC2PARERR",
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"IEC2VALNOGOOD","IEC2CNEW","IEC1BUFATTEN","UCHANTXNF",
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"UCHANTXUNDER","UCHANTXEMPTY","PDIR3UNOV","IEC1PARERR",
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"IEC1VALNOGOOD","IEC1CNEW","EBUTXRESYN","EBUTXUNOV",
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"IIS2TXRESYN","IIS2TXUNOV","IIS1TXRESYN","IIS1TXUNOV",
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"GPIO0","GPI1","GPI2","GPI3","GPI4","GPI5","GPI6","GPI7",
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"","","","","","","","SOFTINT0",
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"SOFTINT1","SOFTINT2","SOFTINT3","",
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"","CDROMCRCERR","CDROMNOSYNC","CDROMILSYNC",
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"CDROMNEWBLK","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","","",
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"","","","","","","",""
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};
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default_interrupt (TRAP0); /* Trap #0 */
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default_interrupt (TRAP1); /* Trap #1 */
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default_interrupt (TRAP2); /* Trap #2 */
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default_interrupt (TRAP3); /* Trap #3 */
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default_interrupt (TRAP4); /* Trap #4 */
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default_interrupt (TRAP5); /* Trap #5 */
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default_interrupt (TRAP6); /* Trap #6 */
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default_interrupt (TRAP7); /* Trap #7 */
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default_interrupt (TRAP8); /* Trap #8 */
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default_interrupt (TRAP9); /* Trap #9 */
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default_interrupt (TRAP10); /* Trap #10 */
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default_interrupt (TRAP11); /* Trap #11 */
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default_interrupt (TRAP12); /* Trap #12 */
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default_interrupt (TRAP13); /* Trap #13 */
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default_interrupt (TRAP14); /* Trap #14 */
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default_interrupt (TRAP15); /* Trap #15 */
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default_interrupt (SWT); /* Software Watchdog Timer */
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default_interrupt (TIMER0); /* Timer 0 */
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default_interrupt (TIMER1); /* Timer 1 */
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default_interrupt (I2C); /* I2C */
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default_interrupt (UART1); /* UART 1 */
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default_interrupt (UART2); /* UART 2 */
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default_interrupt (DMA0); /* DMA 0 */
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default_interrupt (DMA1); /* DMA 1 */
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default_interrupt (DMA2); /* DMA 2 */
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default_interrupt (DMA3); /* DMA 3 */
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default_interrupt (QSPI); /* QSPI */
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default_interrupt (PDIR1FULL); /* Processor data in 1 full */
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default_interrupt (PDIR2FULL); /* Processor data in 2 full */
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default_interrupt (EBUTXEMPTY); /* EBU transmit FIFO empty */
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default_interrupt (IIS2TXEMPTY); /* IIS2 transmit FIFO empty */
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default_interrupt (IIS1TXEMPTY); /* IIS1 transmit FIFO empty */
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default_interrupt (PDIR3FULL); /* Processor data in 3 full */
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default_interrupt (PDIR3RESYN); /* Processor data in 3 resync */
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default_interrupt (UQ2CHANERR); /* IEC958-2 Rx U/Q channel error */
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default_interrupt (AUDIOTICK); /* "tick" interrupt */
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default_interrupt (PDIR2RESYN); /* Processor data in 2 resync */
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default_interrupt (PDIR2UNOV); /* Processor data in 2 under/overrun */
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default_interrupt (PDIR1RESYN); /* Processor data in 1 resync */
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default_interrupt (PDIR1UNOV); /* Processor data in 1 under/overrun */
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default_interrupt (UQ1CHANERR); /* IEC958-1 Rx U/Q channel error */
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default_interrupt (IEC2BUFATTEN);/* IEC958-2 channel buffer full */
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default_interrupt (IEC2PARERR); /* IEC958-2 Rx parity or symbol error */
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default_interrupt (IEC2VALNOGOOD);/* IEC958-2 flag not good */
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default_interrupt (IEC2CNEW); /* IEC958-2 New C-channel received */
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default_interrupt (IEC1BUFATTEN);/* IEC958-1 channel buffer full */
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default_interrupt (UCHANTXNF); /* U channel Tx reg next byte is first */
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default_interrupt (UCHANTXUNDER);/* U channel Tx reg underrun */
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default_interrupt (UCHANTXEMPTY);/* U channel Tx reg is empty */
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default_interrupt (PDIR3UNOV); /* Processor data in 3 under/overrun */
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default_interrupt (IEC1PARERR); /* IEC958-1 Rx parity or symbol error */
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default_interrupt (IEC1VALNOGOOD);/* IEC958-1 flag not good */
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default_interrupt (IEC1CNEW); /* IEC958-1 New C-channel received */
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default_interrupt (EBUTXRESYN); /* EBU Tx FIFO resync */
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default_interrupt (EBUTXUNOV); /* EBU Tx FIFO under/overrun */
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default_interrupt (IIS2TXRESYN); /* IIS2 Tx FIFO resync */
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default_interrupt (IIS2TXUNOV); /* IIS2 Tx FIFO under/overrun */
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default_interrupt (IIS1TXRESYN); /* IIS1 Tx FIFO resync */
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default_interrupt (IIS1TXUNOV); /* IIS1 Tx FIFO under/overrun */
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default_interrupt (GPI0); /* GPIO interrupt 0 */
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default_interrupt (GPI1); /* GPIO interrupt 1 */
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default_interrupt (GPI2); /* GPIO interrupt 2 */
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default_interrupt (GPI3); /* GPIO interrupt 3 */
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default_interrupt (GPI4); /* GPIO interrupt 4 */
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default_interrupt (GPI5); /* GPIO interrupt 5 */
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default_interrupt (GPI6); /* GPIO interrupt 6 */
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default_interrupt (GPI7); /* GPIO interrupt 7 */
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default_interrupt (SOFTINT0); /* Software interrupt 0 */
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default_interrupt (SOFTINT1); /* Software interrupt 1 */
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default_interrupt (SOFTINT2); /* Software interrupt 2 */
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default_interrupt (SOFTINT3); /* Software interrupt 3 */
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default_interrupt (CDROMCRCERR); /* CD-ROM CRC error */
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default_interrupt (CDROMNOSYNC); /* CD-ROM No sync */
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default_interrupt (CDROMILSYNC); /* CD-ROM Illegal sync */
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default_interrupt (CDROMNEWBLK); /* CD-ROM New block */
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void UIE (void) /* Unexpected Interrupt or Exception */
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{
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unsigned int format_vector, pc;
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int vector;
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asm volatile ("move.l (0,%%sp),%0": "=r"(format_vector));
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asm volatile ("move.l (4,%%sp),%0": "=r"(pc));
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vector = (format_vector >> 16) & 0xff;
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while (1)
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{
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}
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}
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/* reset vectors are handled in crt0.S */
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void (* const vbr[]) (void) __attribute__ ((section (".vectors"))) =
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{
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UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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TRAP0,TRAP1,TRAP2,TRAP3,TRAP4,TRAP5,TRAP6,TRAP7,
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TRAP8,TRAP9,TRAP10,TRAP11,TRAP12,TRAP13,TRAP14,TRAP15,
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SWT,TIMER0,TIMER1,I2C,UART1,UART2,DMA0,DMA1,
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DMA2,DMA3,QSPI,UIE,UIE,UIE,UIE,UIE,
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PDIR1FULL,PDIR2FULL,EBUTXEMPTY,IIS2TXEMPTY,
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IIS1TXEMPTY,PDIR3FULL,PDIR3RESYN,UQ2CHANERR,
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AUDIOTICK,PDIR2RESYN,PDIR2UNOV,PDIR1RESYN,
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PDIR1UNOV,UQ1CHANERR,IEC2BUFATTEN,IEC2PARERR,
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IEC2VALNOGOOD,IEC2CNEW,IEC1BUFATTEN,UCHANTXNF,
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UCHANTXUNDER,UCHANTXEMPTY,PDIR3UNOV,IEC1PARERR,
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IEC1VALNOGOOD,IEC1CNEW,EBUTXRESYN,EBUTXUNOV,
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IIS2TXRESYN,IIS2TXUNOV,IIS1TXRESYN,IIS1TXUNOV,
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GPI0,GPI1,GPI2,GPI3,GPI4,GPI5,GPI6,GPI7,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,SOFTINT0,
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SOFTINT1,SOFTINT2,SOFTINT3,UIE,
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UIE,CDROMCRCERR,CDROMNOSYNC,CDROMILSYNC,
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CDROMNEWBLK,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
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UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE
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};
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void system_init(void)
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{
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}
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#elif CONFIG_CPU == SH7034
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#include "lcd.h"
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#include "font.h"
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#include "led.h"
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@ -30,9 +204,6 @@
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#define reserve_interrupt(number) \
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void UIE##number (void)
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extern void reset_pc (void);
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extern void reset_sp (void);
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static const char* const irqname[] = {
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"", "", "", "", "IllInstr", "", "IllSltIn","","",
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"CPUAdrEr", "DMAAdrEr", "NMI", "UserBrk",
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@ -541,3 +712,4 @@ int system_memory_guard(int newmode)
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return oldmode;
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}
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#endif
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