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Mini 2nd Gen: Almost doubled LCD update speed when not boosted (68.5->129fps @30MHz) by handling the serial LCD clock divider.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15524 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2007-11-08 06:52:48 +00:00
parent 57d71e4267
commit a50a80e1a3
2 changed files with 11 additions and 0 deletions
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2
firmware/export/pp5020.h
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@ -147,6 +147,8 @@
/* clock control */ /* clock control */
#define CLOCK_SOURCE (*(volatile unsigned long *)(0x60006020)) #define CLOCK_SOURCE (*(volatile unsigned long *)(0x60006020))
#define MLCD_SCLK_DIV (*(volatile unsigned long *)(0x6000602c))
/* bits 0..1: Mono LCD bridge serial clock divider: 1 / (n+1) */
#define PLL_CONTROL (*(volatile unsigned long *)(0x60006034)) #define PLL_CONTROL (*(volatile unsigned long *)(0x60006034))
#define PLL_STATUS (*(volatile unsigned long *)(0x6000603c)) #define PLL_STATUS (*(volatile unsigned long *)(0x6000603c))
#define ADC_CLOCK_SRC (*(volatile unsigned long *)(0x60006094)) #define ADC_CLOCK_SRC (*(volatile unsigned long *)(0x60006094))

9
firmware/target/arm/system-pp502x.c
View file

@ -178,6 +178,9 @@ static void pp_set_cpu_frequency(long frequency)
case CPUFREQ_MAX: case CPUFREQ_MAX:
CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */
DEV_TIMING1 = 0x00000303; DEV_TIMING1 = 0x00000303;
#ifdef IPOD_MINI2G
MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */
#endif
#if CONFIG_CPU == PP5020 #if CONFIG_CPU == PP5020
PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */ PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */
PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */ PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */
@ -196,6 +199,9 @@ static void pp_set_cpu_frequency(long frequency)
case CPUFREQ_NORMAL: case CPUFREQ_NORMAL:
CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */
DEV_TIMING1 = 0x00000303; DEV_TIMING1 = 0x00000303;
#ifdef IPOD_MINI2G
MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
#endif
#if CONFIG_CPU == PP5020 #if CONFIG_CPU == PP5020
PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */ PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */
scale_suspend_core(false); scale_suspend_core(false);
@ -220,6 +226,9 @@ static void pp_set_cpu_frequency(long frequency)
default: default:
CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */ CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */
DEV_TIMING1 = 0x00000303; DEV_TIMING1 = 0x00000303;
#ifdef IPOD_MINI2G
MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */
#endif
PLL_CONTROL &= ~0x80000000; /* disable PLL */ PLL_CONTROL &= ~0x80000000; /* disable PLL */
cpu_frequency = CPUFREQ_DEFAULT; cpu_frequency = CPUFREQ_DEFAULT;
PROC_CTL(CURRENT_CORE) = 0x4800001f; nop; PROC_CTL(CURRENT_CORE) = 0x4800001f; nop;