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iRiver: Clearing CRSEL bit when using default CPU frequency caused audio chip to run at half frequency when radio screen called cpu_idle_mode(true) and corresponding high end loss after kepress timeout. CRSEL was originally preserved when bypassing PLL. CRSEL shouldn't have any bearing on PSTCLK or SCLK when PLL is bypassed since the dividers are bypassed as well (except for the divX2 for SCLK).

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11695 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2006-12-08 23:33:22 +00:00
parent 4ccbcc8071
commit 9b720239a3
1 changed files with 2 additions and 2 deletions
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4
firmware/target/coldfire/iriver/system-iriver.c
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@ -134,8 +134,8 @@ void set_cpu_frequency(long frequency)
PLLCR &= ~1; /* Bypass mode */
timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
RECALC_DELAYS(CPUFREQ_DEFAULT);
/* Power down PLL, but keep CLSEL */
PLLCR = 0x00000200 | (PLLCR & 0x70400000);
/* Power down PLL, but keep CRSEL and CLSEL */
PLLCR = 0x00800200 | (PLLCR & 0x70400000);
CSCR0 = 0x00000180; /* Flash: 0 wait states */
CSCR1 = 0x00000180; /* LCD: 0 wait states */
#if CONFIG_USBOTG == USBOTG_ISP1362