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Cache functions should include data and instruction barriers.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17150 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2008-04-17 00:07:06 +00:00
parent 7fee4868f9
commit 99a65dfc1e
2 changed files with 18 additions and 7 deletions
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9
firmware/target/arm/imx31/gigabeat-s/system-target.h
View file

@ -42,8 +42,13 @@ static inline void invalidate_icache(void)
asm volatile(
/* Clean and invalidate entire data cache */
"mcr p15, 0, %0, c7, c14, 0 \n"
/* Invalidate entire instruction cache */
/* Invalidate entire intruction cache
* Also flushes the branch target cache */
"mcr p15, 0, %0, c7, c5, 0 \n"
/* Data synchronization barrier */
"mcr p15, 0, %0, c7, c10, 4 \n"
/* Flush prefetch buffer */
"mcr p15, 0, %0, c7, c5, 4 \n"
: : "r"(0)
);
}
@ -54,6 +59,8 @@ static inline void flush_icache(void)
asm volatile (
/* Clean entire data cache */
"mcr p15, 0, %0, c7, c10, 0 \n"
/* Data synchronization barrier */
"mcr p15, 0, r2, c7, c10, 4 \n"
: : "r"(0)
);
}

8
firmware/target/arm/mmu-arm.c
View file

@ -91,7 +91,9 @@ void __attribute__((naked)) invalidate_dcache_range(const void *base, unsigned i
{
asm volatile(
"add r1, r1, r0 \n"
"mcrr p15, 0, r1, r0, c14 \n"
"mov r2, #0 \n"
"mcrr p15, 0, r1, r0, c14 \n" /* Clean and invalidate dcache range */
"mcr p15, 0, r2, c7, c10, 4 \n" /* Data synchronization barrier */
"bx lr \n"
);
(void)base; (void)size;
@ -141,7 +143,9 @@ void __attribute__((naked)) clean_dcache_range(const void *base, unsigned int si
{
asm volatile(
"add r1, r1, r0 \n"
"mcrr p15, 0, r1, r0, c12 \n"
"mov r2, #0 \n"
"mcrr p15, 0, r1, r0, c12 \n" /* Clean dcache range */
"mcr p15, 0, r2, c7, c10, 4 \n" /* Data synchronization barrier */
"bx lr \n"
);
(void)base; (void)size;