forked from len0rd/rockbox
H300: Rudimentary driver for the ISP1362 USB on-the-go controller. For now it just sends the chip to sleep, solving the poor battery runtime issue.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@10128 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
cd69996450
commit
977169ea7a
8 changed files with 355 additions and 7 deletions
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@ -88,6 +88,10 @@
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#include "lcd-remote.h"
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#include "lcd-remote.h"
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#endif
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#endif
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#if CONFIG_USBOTG == USBOTG_ISP1362
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#include "isp1362.h"
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#endif
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/*#define AUTOROCK*/ /* define this to check for "autostart.rock" on boot */
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/*#define AUTOROCK*/ /* define this to check for "autostart.rock" on boot */
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const char appsversion[]=APPSVERSION;
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const char appsversion[]=APPSVERSION;
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@ -276,6 +280,9 @@ void init(void)
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adc_init();
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adc_init();
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usb_init();
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usb_init();
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#if CONFIG_USBOTG == USBOTG_ISP1362
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isp1362_init();
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#endif
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backlight_init();
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backlight_init();
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@ -203,6 +203,10 @@ sound.c
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common/sscanf.c
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common/sscanf.c
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usb_serial.c
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usb_serial.c
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#endif
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#endif
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#if CONFIG_USBOTG == USBOTG_ISP1362
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drivers/isp1362.c
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#endif
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#ifndef SIMULATOR
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#ifndef SIMULATOR
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#ifdef IAUDIO_X5
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#ifdef IAUDIO_X5
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@ -531,7 +531,7 @@ irq_handler:
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/* Chip select 1 - LCD controller */
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/* Chip select 1 - LCD controller */
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move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */
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move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */
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move.l %d0,(0x08c,%a0)
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move.l %d0,(0x08c,%a0)
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moveq.l #0x1,%d0 /* CSMR1 - 64K */
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moveq.l #0x1,%d0 /* CSMR1 - 64K */
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move.l %d0,(0x090,%a0)
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move.l %d0,(0x090,%a0)
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move.l #0x00000180,%d0 /* CSCR1 - no wait states, 16 bits, no bursts */
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move.l #0x00000180,%d0 /* CSCR1 - no wait states, 16 bits, no bursts */
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move.l %d0,(0x094,%a0)
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move.l %d0,(0x094,%a0)
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@ -545,7 +545,16 @@ irq_handler:
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move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states.
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move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states.
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We have to be careful with the access times,
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We have to be careful with the access times,
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since IORDY isn't connected to the HDD. */
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since IORDY isn't connected to the HDD. */
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#if CONFIG_USBOTG == USBOTG_ISP1362
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/* Chip select 3 - USBOTG controller */
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move.l #0xc0000000,%d0 /* CSAR3 - Base = 0xc0000000 */
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move.l %d0,(0x0a4,%a0)
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moveq.l #0x1,%d0 /* CSMR3 - 64K */
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move.l %d0,(0x0a8,%a0)
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move.l #0x00000180,%d0 /* CSCR3 - no wait states, 16 bits, no bursts */
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move.l %d0,(0x0ac,%a0)
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#endif
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#ifdef BOOTLOADER
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#ifdef BOOTLOADER
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/* The cookie is not reset. This must mean that the boot loader
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/* The cookie is not reset. This must mean that the boot loader
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177
firmware/drivers/isp1362.c
Executable file
177
firmware/drivers/isp1362.c
Executable file
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@ -0,0 +1,177 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 Jens Arnold
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "kernel.h"
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#include "isp1362.h"
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#define HC_DATA (*((volatile unsigned short*)0xc0000000))
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#define HC_CMD (*((volatile unsigned short*)0xc0000002))
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#define DC_DATA (*((volatile unsigned short*)0xc0000004))
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#define DC_CMD (*((volatile unsigned short*)0xc0000006))
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/* host controller access */
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unsigned isp1362_read_hc_reg16(unsigned reg)
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{
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HC_CMD = reg;
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asm ("nop\n nop\n nop\n nop\n");
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asm ("nop\n nop\n nop\n nop\n");
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asm ("nop\n nop\n nop\n nop\n");
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return HC_DATA;
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}
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unsigned isp1362_read_hc_reg32(unsigned reg)
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{
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unsigned data;
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HC_CMD = reg;
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asm ("nop\n nop\n nop\n nop\n");
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asm ("nop\n nop\n nop\n nop\n");
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asm ("nop\n nop\n nop\n nop\n");
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data = HC_DATA;
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data |= HC_DATA << 16;
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return data;
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}
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void isp1362_write_hc_reg16(unsigned reg, unsigned data)
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{
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HC_CMD = reg | 0x80;
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asm ("nop\n nop\n nop\n");
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HC_DATA = data;
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}
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void isp1362_write_hc_reg32(unsigned reg, unsigned data)
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{
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HC_CMD = reg | 0x80;
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asm ("nop\n nop\n nop\n");
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HC_DATA = data;
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HC_DATA = data >> 16;
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}
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/* device controller access */
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unsigned isp1362_read_dc_reg16(unsigned reg)
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{
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DC_CMD = reg;
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asm ("nop\n nop\n nop\n nop\n");
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asm ("nop\n nop\n nop\n nop\n");
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asm ("nop\n nop\n nop\n nop\n");
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return DC_DATA;
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}
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unsigned isp1362_read_dc_reg32(unsigned reg)
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{
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unsigned data;
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DC_CMD = reg;
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asm ("nop\n nop\n nop\n nop\n");
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asm ("nop\n nop\n nop\n nop\n");
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asm ("nop\n nop\n nop\n nop\n");
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data = DC_DATA;
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data |= DC_DATA << 16;
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return data;
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}
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void isp1362_write_dc_reg16(unsigned reg, unsigned data)
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{
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DC_CMD = reg;
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asm ("nop\n nop\n nop\n");
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DC_DATA = data;
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}
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void isp1362_write_dc_reg32(unsigned reg, unsigned data)
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{
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DC_CMD = reg;
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asm ("nop\n nop\n nop\n");
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DC_DATA = data;
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DC_DATA = data >> 16;
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}
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static void isp1362_suspend(void)
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{
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unsigned data;
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data = isp1362_read_hc_reg16(ISP1362_OTG_CONTROL);
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data &= ~0x0001; /* DRV_VBUS = 0 */
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isp1362_write_hc_reg16(ISP1362_OTG_CONTROL, data);
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/* prepare the DC */
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data = isp1362_read_dc_reg16(ISP1362_DC_HARDWARE_CONFIG_R);
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data &= ~0x1008; /* CLKRUN = WKUPCS = 0. Wakeup is still possible via /D_WAKEUP */
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isp1362_write_dc_reg16(ISP1362_DC_HARDWARE_CONFIG_W, data);
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/* send the DC to sleep */
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data = isp1362_read_dc_reg16(ISP1362_DC_MODE_R);
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data |= 0x20; /* GOSUSP = 1 */
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isp1362_write_dc_reg16(ISP1362_DC_MODE_W, data);
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data &= ~0x20; /* GOSUSP = 0 */
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isp1362_write_dc_reg16(ISP1362_DC_MODE_W, data);
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/* prepare the HC */
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data = isp1362_read_hc_reg16(ISP1362_HC_HARDWARE_CONFIG);
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data &= ~0x0800; /* SuspendClkNotStop = 0 */
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data |= 0x4001; /* GlobalPowerDown = InterruptPinEnable = 1 */
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isp1362_write_hc_reg16(ISP1362_HC_HARDWARE_CONFIG, data);
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/* TODO: OTG wake-up cfg */
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/* TODO: Interrupt setup */
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/* set the HC to operational */
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isp1362_write_hc_reg32(ISP1362_HC_CONTROL, 0x0680);
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/* RWE = RWC = 1, HCFS = 0b10 (USBOperational) */
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/* ..then send it to sleep */
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isp1362_write_hc_reg32(ISP1362_HC_CONTROL, 0x06c0);
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/* RWE = RWC = 1, HCFS = 0b11 (USBSuspend) */
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}
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/* init */
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void isp1362_init(void)
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{
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and_l(~0x00200080, &GPIO1_OUT); /* disable 5V USB host power and ??? */
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or_l( 0x00200080, &GPIO1_ENABLE);
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or_l( 0x00200080, &GPIO1_FUNCTION);
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or_l( 0x20600000, &GPIO_OUT); /* ID = D_SUSPEND = /OTGMODE = 1 */
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and_l(~0x04000000, &GPIO_OUT); /* ?R26? = 0 */
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or_l( 0x24600000, &GPIO_ENABLE); /* ID, ?R26?, D_SUSPEND, /OTGMODE outputs */
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and_l(~0x000000a8, &GPIO_ENABLE); /* /INT2, /INT1, /RESET inputs */
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or_l( 0x246000a8, &GPIO_FUNCTION); /* GPIO for these pins */
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sleep(HZ/5);
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isp1362_suspend();
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}
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@ -110,6 +110,9 @@
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#define USB_IRIVERSTYLE
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#define USB_IRIVERSTYLE
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/* USB On-the-go */
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#define CONFIG_USBOTG USBOTG_ISP1362
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/* Define this if you have adjustable CPU frequency */
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/* Define this if you have adjustable CPU frequency */
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#define HAVE_ADJUSTABLE_CPU_FREQ
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#define HAVE_ADJUSTABLE_CPU_FREQ
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@ -122,6 +122,7 @@
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/* CONFIG_LED */
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/* CONFIG_LED */
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#define LED_REAL 1 /* SW controlled LED (Archos recorders, player, Gmini) */
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#define LED_REAL 1 /* SW controlled LED (Archos recorders, player, Gmini) */
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#define LED_VIRTUAL 2 /* Virtual LED (icon) (Archos Ondio) */
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#define LED_VIRTUAL 2 /* Virtual LED (icon) (Archos Ondio) */
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/* else HW controlled LED (iRiver H1x0) */
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/* CONFIG_FLASH */
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/* CONFIG_FLASH */
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#define FLASH_IFP7XX 1
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#define FLASH_IFP7XX 1
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@ -132,7 +133,8 @@
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#define RTC_PCF50606 3 /* iriver H300 */
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#define RTC_PCF50606 3 /* iriver H300 */
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#define RTC_S3C2440 4
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#define RTC_S3C2440 4
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/* else HW controlled LED (iRiver H1x0) */
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/* USB On-the-go */
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#define USBOTG_ISP1362 1362
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/* now go and pick yours */
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/* now go and pick yours */
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#if defined(ARCHOS_PLAYER)
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#if defined(ARCHOS_PLAYER)
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134
firmware/export/isp1362.h
Executable file
134
firmware/export/isp1362.h
Executable file
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 Jens Arnold
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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unsigned isp1362_read_hc_reg16(unsigned reg);
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unsigned isp1362_read_hc_reg32(unsigned reg);
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void isp1362_write_hc_reg16(unsigned reg, unsigned data);
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void isp1362_write_hc_reg32(unsigned reg, unsigned data);
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#define ISP1362_OTG_CONTROL 0x62
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#define ISP1362_OTG_STATUS 0x67 /* read only */
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#define ISP1362_OTG_INTERRUPT 0x68
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#define ISP1362_OTG_INT_ENABLE 0x69
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#define ISP1362_OTG_TIMER 0x6a
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#define ISP1362_OTG_ALT_TIMER 0x6c
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#define ISP1362_HC_REVISION 0x00 /* read only */
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#define ISP1362_HC_CONTROL 0x01
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#define ISP1362_HC_COMMAND_STATUS 0x02
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#define ISP1362_HC_INT_STATUS 0x03
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#define ISP1362_HC_INT_ENABLE 0x04
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#define ISP1362_HC_INT_DISABLE 0x05
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#define ISP1362_HC_FM_INTERVAL 0x0d
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#define ISP1362_HC_FM_REMAINING 0x0e
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#define ISP1362_HC_FM_NUMBER 0x0f
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#define ISP1362_HC_LS_THRESHOLD 0x11
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#define ISP1362_HC_RH_DESCRIPTOR_A 0x12
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#define ISP1362_HC_RH_DESCRIPTOR_B 0x13
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#define ISP1362_HC_RH_STATUS 0x14
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#define ISP1362_HC_RH_PORT_STATUS1 0x15
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#define ISP1362_HC_RH_PORT_STATUS2 0x16
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#define ISP1362_HC_HARDWARE_CONFIG 0x20
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#define ISP1362_HC_DMA_CONFIG 0x21
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#define ISP1362_HC_TRANSFER_COUNTER 0x22
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#define ISP1362_HC_UP_INTERRUPT 0x24
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#define ISP1362_HC_UP_INT_ENABLE 0x25
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#define ISP1362_HC_CHIP_ID 0x27 /* read only */
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#define ISP1362_HC_SCRATCH 0x28
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#define ISP1362_HC_SOFTWARE_RESET 0x29 /* write only */
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#define ISP1362_HC_BUFFER_STATUS 0x2c
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#define ISP1362_HC_DIRECT_ADDR_LEN 0x32
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#define ISP1362_HC_DIRECT_ADDR_DATA 0x45
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#define ISP1362_HC_ISTL_BUF_SIZE 0x30
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#define ISP1362_HC_ISTL0_BUF_PORT 0x40
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#define ISP1362_HC_ISTL1_BUF_PORT 0x42
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#define ISP1362_HC_ISTL_TOGGLE_RATE 0x47
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#define ISP1362_HC_INTL_BUF_SIZE 0x33
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#define ISP1362_HC_INTL_BUF_PORT 0x43
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||||||
|
#define ISP1362_HC_INTL_BLK_SIZE 0x53
|
||||||
|
#define ISP1362_HC_INTL_PRD_DONE_MAP 0x17 /* read only */
|
||||||
|
#define ISP1362_HC_INTL_PTD_SKIP_MAP 0x18
|
||||||
|
#define ISP1362_HC_INTL_LAST_PTD 0x19
|
||||||
|
#define ISP1362_HC_INTL_CUR_ACT_PTD 0x1a /* read only */
|
||||||
|
#define ISP1362_HC_ATL_BUF_SIZE 0x34
|
||||||
|
#define ISP1362_HC_ATL_BUF_PORT 0x44
|
||||||
|
#define ISP1362_HC_ATL_BLK_SIZE 0x54
|
||||||
|
#define ISP1362_HC_ATL_PTD_DONE_MAP 0x1b /* read only */
|
||||||
|
#define ISP1362_HC_ATL_PTD_SKIP_MAP 0x1c
|
||||||
|
#define ISP1362_HC_ATL_LAST_PTD 0x1d
|
||||||
|
#define ISP1362_HC_ATL_CUR_ACT_PTD 0x1e /* read only */
|
||||||
|
#define ISP1362_HC_ATL_PTD_DONE_THR_CNT 0x51
|
||||||
|
#define ISP1362_HC_ATL_PTD_DONE_THR_TMO 0x52
|
||||||
|
|
||||||
|
unsigned isp1362_read_dc_reg16(unsigned reg);
|
||||||
|
unsigned isp1362_read_dc_reg32(unsigned reg);
|
||||||
|
void isp1362_write_dc_reg16(unsigned reg, unsigned data);
|
||||||
|
void isp1362_write_dc_reg32(unsigned reg, unsigned data);
|
||||||
|
|
||||||
|
#define ISP1362_DC_CTRL_OUT_CFG_W 0x20
|
||||||
|
#define ISP1362_DC_CTRL_IN_CFG_W 0x21
|
||||||
|
#define ISP1362_DC_ENDPOINT_CFG_BASE_W 0x22
|
||||||
|
#define ISP1362_DC_CTRL_OUT_CFG_R 0x30
|
||||||
|
#define ISP1362_DC_CTRL_IN_CFG_R 0x31
|
||||||
|
#define ISP1362_DC_ENDPOINT_CFG_BASE_R 0x32
|
||||||
|
#define ISP1362_DC_ADDRESS_W 0xb6
|
||||||
|
#define ISP1362_DC_ADDRESS_R 0xb7
|
||||||
|
#define ISP1362_DC_MODE_W 0xb8
|
||||||
|
#define ISP1362_DC_MODE_R 0xb9
|
||||||
|
#define ISP1362_DC_HARDWARE_CONFIG_W 0xba
|
||||||
|
#define ISP1362_DC_HARDWARE_CONFIG_R 0xbb
|
||||||
|
#define ISP1362_DC_INT_ENABLE_W 0xc2
|
||||||
|
#define ISP1362_DC_INT_ENABLE_R 0xc3
|
||||||
|
#define ISP1362_DC_DMA_CONFIG_W 0xf0
|
||||||
|
#define ISP1362_DC_DMA_CONFIG_R 0xf1
|
||||||
|
#define ISP1362_DC_DMA_COUNTER_W 0xf2
|
||||||
|
#define ISP1362_DC_DMA_COUNTER_R 0xf3
|
||||||
|
#define ISP1362_DC_RESET 0xf6
|
||||||
|
#define ISP1362_DC_CTRL_IN_BUF_W 0x01
|
||||||
|
#define ISP1362_DC_ENDPOINT_BUF_BASE_W 0x02
|
||||||
|
#define ISP1362_DC_CTRL_OUT_BUF_R 0x10
|
||||||
|
#define ISP1362_DC_ENDPOINT_BUF_BASE_R 0x12
|
||||||
|
#define ISP1362_DC_CTRL_OUT_STALL 0x40
|
||||||
|
#define ISP1362_DC_CTRL_IN_STALL 0x41
|
||||||
|
#define ISP1362_DC_ENDPOINT_STALL_BASE 0x42
|
||||||
|
#define ISP1362_DC_CTRL_OUT_STATUS_R 0x50
|
||||||
|
#define ISP1362_DC_CTRL_IN_STATUS_R 0x51
|
||||||
|
#define ISP1362_DC_ENDPOINT_STATUS_BASE_R 0x52
|
||||||
|
#define ISP1362_DC_CTRL_IN_VALIDATE 0x61
|
||||||
|
#define ISP1362_DC_ENDPOINT_VALIDATE_BASE 0x62
|
||||||
|
#define ISP1362_DC_CTRL_OUT_CLEAR 0x70
|
||||||
|
#define ISP1362_DC_ENDPOINT_CLEAR_BASE 0x72
|
||||||
|
#define ISP1362_DC_CTRL_OUT_UNSTALL 0x80
|
||||||
|
#define ISP1362_DC_CTRL_IN_UNSTALL 0x81
|
||||||
|
#define ISP1362_DC_ENDPOINT_UNSTALL_BASE 0x82
|
||||||
|
#define ISP1362_DC_CTRL_OUT_STAT_IMG_R 0xd0
|
||||||
|
#define ISP1362_DC_CTRL_IN_STAT_IMG_R 0xd1
|
||||||
|
#define ISP1362_DC_ENDPOINT_STAT_IMG_BASE_R 0xd2
|
||||||
|
#define ISP1362_DC_SETUP_ACK 0xf4
|
||||||
|
#define ISP1362_DC_CTRL_OUT_ERROR_R 0xa0
|
||||||
|
#define ISP1362_DC_CTRL_IN_ERROR_R 0xa1
|
||||||
|
#define ISP1362_DC_ENDPOINT_ERROR_BASE_R 0xa2
|
||||||
|
#define ISP1362_DC_UNLOCK_DEVICE 0xb0
|
||||||
|
#define ISP1362_DC_SCRATCH_W 0xb2
|
||||||
|
#define ISP1362_DC_SCRATCH_R 0xb3
|
||||||
|
#define ISP1362_DC_FRAME_NUMBER_R 0xb4
|
||||||
|
#define ISP1362_DC_CHIP_ID_R 0xb5
|
||||||
|
#define ISP1362_DC_INTERRUPT_R 0xc0
|
||||||
|
|
||||||
|
void isp1362_init(void);
|
||||||
|
|
@ -616,13 +616,17 @@ void set_cpu_frequency(long frequency)
|
||||||
PLLCR = 0x11c56005;
|
PLLCR = 0x11c56005;
|
||||||
CSCR0 = 0x00001180; /* Flash: 4 wait states */
|
CSCR0 = 0x00001180; /* Flash: 4 wait states */
|
||||||
CSCR1 = 0x00000980; /* LCD: 2 wait states */
|
CSCR1 = 0x00000980; /* LCD: 2 wait states */
|
||||||
|
#if CONFIG_USBOTG == USBOTG_ISP1362
|
||||||
|
CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
|
||||||
|
#endif
|
||||||
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
|
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
|
||||||
This may take up to 10ms! */
|
This may take up to 10ms! */
|
||||||
timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
|
timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
|
||||||
DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
|
DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
|
||||||
cpu_frequency = CPUFREQ_MAX;
|
cpu_frequency = CPUFREQ_MAX;
|
||||||
IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
|
IDECONFIG1 = 0x10100000 | (3 << 13) | (5 << 10);
|
||||||
IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
|
/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
|
||||||
|
IDECONFIG2 = 0x40000 | (2 << 8); /* TA enable + CS2wait */
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case CPUFREQ_NORMAL:
|
case CPUFREQ_NORMAL:
|
||||||
|
|
@ -634,12 +638,16 @@ void set_cpu_frequency(long frequency)
|
||||||
PLLCR = 0x13c5e005;
|
PLLCR = 0x13c5e005;
|
||||||
CSCR0 = 0x00000580; /* Flash: 1 wait state */
|
CSCR0 = 0x00000580; /* Flash: 1 wait state */
|
||||||
CSCR1 = 0x00000180; /* LCD: 0 wait states */
|
CSCR1 = 0x00000180; /* LCD: 0 wait states */
|
||||||
|
#if CONFIG_USBOTG == USBOTG_ISP1362
|
||||||
|
CSCR3 = 0x00000580; /* USBOTG: 1 wait state */
|
||||||
|
#endif
|
||||||
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
|
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
|
||||||
This may take up to 10ms! */
|
This may take up to 10ms! */
|
||||||
timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
|
timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
|
||||||
DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
|
DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
|
||||||
cpu_frequency = CPUFREQ_NORMAL;
|
cpu_frequency = CPUFREQ_NORMAL;
|
||||||
IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
|
IDECONFIG1 = 0x10100000 | (3 << 13) | (5 << 10);
|
||||||
|
/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
|
||||||
IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
|
IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
|
@ -651,9 +659,13 @@ void set_cpu_frequency(long frequency)
|
||||||
PLLCR = 0x10c00200; /* Power down PLL, but keep CLSEL and CRSEL */
|
PLLCR = 0x10c00200; /* Power down PLL, but keep CLSEL and CRSEL */
|
||||||
CSCR0 = 0x00000180; /* Flash: 0 wait states */
|
CSCR0 = 0x00000180; /* Flash: 0 wait states */
|
||||||
CSCR1 = 0x00000180; /* LCD: 0 wait states */
|
CSCR1 = 0x00000180; /* LCD: 0 wait states */
|
||||||
|
#if CONFIG_USBOTG == USBOTG_ISP1362
|
||||||
|
CSCR3 = 0x00000180; /* USBOTG: 0 wait states */
|
||||||
|
#endif
|
||||||
DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
|
DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
|
||||||
cpu_frequency = CPUFREQ_DEFAULT;
|
cpu_frequency = CPUFREQ_DEFAULT;
|
||||||
IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
|
IDECONFIG1 = 0x10100000 | (3 << 13) | (1 << 10);
|
||||||
|
/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
|
||||||
IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
|
IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue