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H300: Rudimentary driver for the ISP1362 USB on-the-go controller. For now it just sends the chip to sleep, solving the poor battery runtime issue.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@10128 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2006-06-16 17:34:18 +00:00
parent cd69996450
commit 977169ea7a
8 changed files with 355 additions and 7 deletions
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20
firmware/system.c
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@ -616,13 +616,17 @@ void set_cpu_frequency(long frequency)
PLLCR = 0x11c56005;
CSCR0 = 0x00001180; /* Flash: 4 wait states */
CSCR1 = 0x00000980; /* LCD: 2 wait states */
#if CONFIG_USBOTG == USBOTG_ISP1362
CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
#endif
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
This may take up to 10ms! */
timers_adjust_prescale(CPUFREQ_MAX_MULT, true);
DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */
cpu_frequency = CPUFREQ_MAX;
IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */
IDECONFIG1 = 0x10100000 | (3 << 13) | (5 << 10);
/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
IDECONFIG2 = 0x40000 | (2 << 8); /* TA enable + CS2wait */
break;
case CPUFREQ_NORMAL:
@ -634,12 +638,16 @@ void set_cpu_frequency(long frequency)
PLLCR = 0x13c5e005;
CSCR0 = 0x00000580; /* Flash: 1 wait state */
CSCR1 = 0x00000180; /* LCD: 0 wait states */
#if CONFIG_USBOTG == USBOTG_ISP1362
CSCR3 = 0x00000580; /* USBOTG: 1 wait state */
#endif
while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked.
This may take up to 10ms! */
timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true);
DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */
cpu_frequency = CPUFREQ_NORMAL;
IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
IDECONFIG1 = 0x10100000 | (3 << 13) | (5 << 10);
/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
break;
default:
@ -651,9 +659,13 @@ void set_cpu_frequency(long frequency)
PLLCR = 0x10c00200; /* Power down PLL, but keep CLSEL and CRSEL */
CSCR0 = 0x00000180; /* Flash: 0 wait states */
CSCR1 = 0x00000180; /* LCD: 0 wait states */
#if CONFIG_USBOTG == USBOTG_ISP1362
CSCR3 = 0x00000180; /* USBOTG: 0 wait states */
#endif
DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */
cpu_frequency = CPUFREQ_DEFAULT;
IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */
IDECONFIG1 = 0x10100000 | (3 << 13) | (1 << 10);
/* SRE active on write (H300 USBOTG) | BUFEN2 enable | CS2Post | CS2Pre */
IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */
break;
}