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imx233: rewrite digctl using new register headers

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Change-Id: I910a09e07b9f5a82bb6cb150739fcebc942cb7c1
This commit is contained in:
Amaury Pouly 2013-06-16 17:56:10 +02:00
parent a759242b55
commit 96b1d02b05
2 changed files with 12 additions and 39 deletions
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22
firmware/target/arm/imx233/system-imx233.c
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@ -167,12 +167,8 @@ void udelay(unsigned us)
void imx233_digctl_set_arm_cache_timings(unsigned timings) void imx233_digctl_set_arm_cache_timings(unsigned timings)
{ {
HW_DIGCTL_ARMCACHE = HW_DIGCTL_ARMCACHE = BF_OR5(DIGCTL_ARMCACHE, ITAG_SS(timings),
timings << HW_DIGCTL_ARMCACHE__ITAG_SS_BP | DTAG_SS(timings), CACHE_SS(timings), DRTY_SS(timings), VALID_SS(timings));
timings << HW_DIGCTL_ARMCACHE__DTAG_SS_BP |
timings << HW_DIGCTL_ARMCACHE__CACHE_SS_BP |
timings << HW_DIGCTL_ARMCACHE__DRTY_SS_BP |
timings << HW_DIGCTL_ARMCACHE__VALID_SS_BP;
} }
#ifdef HAVE_ADJUSTABLE_CPU_FREQ #ifdef HAVE_ADJUSTABLE_CPU_FREQ
@ -264,21 +260,23 @@ void set_cpu_frequency(long frequency)
void imx233_enable_usb_controller(bool enable) void imx233_enable_usb_controller(bool enable)
{ {
if(enable) if(enable)
__REG_CLR(HW_DIGCTL_CTRL) = HW_DIGCTL_CTRL__USB_CLKGATE; BF_CLR(DIGCTL_CTRL, USB_CLKGATE);
else else
__REG_SET(HW_DIGCTL_CTRL) = HW_DIGCTL_CTRL__USB_CLKGATE; BF_SET(DIGCTL_CTRL, USB_CLKGATE);
} }
void imx233_enable_usb_phy(bool enable) void imx233_enable_usb_phy(bool enable)
{ {
if(enable) if(enable)
{ {
__REG_CLR(HW_USBPHY_CTRL) = __BLOCK_CLKGATE | __BLOCK_SFTRST; BF_CLR(USBPHY_CTRL, SFTRST);
__REG_CLR(HW_USBPHY_PWD) = HW_USBPHY_PWD__ALL; BF_CLR(USBPHY_CTRL, CLKGATE);
HW_USBPHY_PWD_CLR = 0xffffffff;
} }
else else
{ {
__REG_SET(HW_USBPHY_PWD) = HW_USBPHY_PWD__ALL; HW_USBPHY_PWD_SET = 0xffffffff;
__REG_SET(HW_USBPHY_CTRL) = __BLOCK_CLKGATE | __BLOCK_SFTRST; BF_SET(USBPHY_CTRL, SFTRST);
BF_SET(USBPHY_CTRL, CLKGATE);
} }
} }

29
firmware/target/arm/imx233/system-target.h
View file

@ -28,33 +28,8 @@
#include "icoll-imx233.h" #include "icoll-imx233.h"
#include "clock-target.h" /* CPUFREQ_* are defined here */ #include "clock-target.h" /* CPUFREQ_* are defined here */
/* Digital control */ #include "regs/regs-digctl.h"
#define HW_DIGCTL_BASE 0x8001C000 #include "regs/regs-usbphy.h"
#define HW_DIGCTL_CTRL (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0))
#define HW_DIGCTL_CTRL__USB_CLKGATE (1 << 2)
#define HW_DIGCTL_HCLKCOUNT (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0x20))
#define HW_DIGCTL_MICROSECONDS (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0xC0))
#define HW_DIGCTL_ARMCACHE (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0x2b0))
#define HW_DIGCTL_ARMCACHE__ITAG_SS_BP 0
#define HW_DIGCTL_ARMCACHE__ITAG_SS_BM (3 << 0)
#define HW_DIGCTL_ARMCACHE__DTAG_SS_BP 4
#define HW_DIGCTL_ARMCACHE__DTAG_SS_BM (3 << 4)
#define HW_DIGCTL_ARMCACHE__CACHE_SS_BP 8
#define HW_DIGCTL_ARMCACHE__CACHE_SS_BM (3 << 8)
#define HW_DIGCTL_ARMCACHE__DRTY_SS_BP 12
#define HW_DIGCTL_ARMCACHE__DRTY_SS_BM (3 << 12)
#define HW_DIGCTL_ARMCACHE__VALID_SS_BP 16
#define HW_DIGCTL_ARMCACHE__VALID_SS_BM (3 << 16)
/* USB Phy */
#define HW_USBPHY_BASE 0x8007C000
#define HW_USBPHY_PWD (*(volatile uint32_t *)(HW_USBPHY_BASE + 0))
#define HW_USBPHY_PWD__ALL (7 << 10 | 0xf << 17)
#define HW_USBPHY_CTRL (*(volatile uint32_t *)(HW_USBPHY_BASE + 0x30))
/** /**
* Absolute maximum CPU speed: 454.74 MHz * Absolute maximum CPU speed: 454.74 MHz