forked from len0rd/rockbox
Gigabeat S: Implement an SDMA API and use it in the PCM driver. Some other miscellaneous adjustments to recording and PCM buffer to accomodate use of physical addresses and cache coherency.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19949 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
0222d0a5eb
commit
94537f954e
21 changed files with 3002 additions and 141 deletions
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@ -118,6 +118,22 @@
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#define WDOG1_BASE_ADDR WDOG_BASE_ADDR
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#define CRM_MCU_BASE_ADDR CCM_BASE_ADDR
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/* IIM */
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#define IIM_PREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x20))
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#define IIM_PREV_SIG (0x1f << 3)
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#define IIM_PREV_SIG_IMX31 (0x01 << 3) /* i.MX31 */
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#define IIM_SREV (*(REG32_PTR_T)(IIM_BASE_ADDR + 0x24))
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#define IIM_SREV_SREV (0xff << 0)
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#define IIM_SREV_1_0 0x00 /* i.MX31/L 1.0, L38W */
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#define IIM_SREV_1_1 0x10 /* i.MX31 1.1, 2L38W */
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#define IIM_SREV_1_1L 0x11 /* i.MX31L 1.1, 2L38W */
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#define IIM_SREV_1_15 0x12 /* i.MX31 1.15, 2L38W/3L38W */
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#define IIM_SREV_1_15L 0x13 /* i.MX31L 1.15, 2L38W/3L38W */
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#define IIM_SREV_1_2 0x14 /* i.MX31 1.2, 3L38W, M45G */
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#define IIM_SREV_1_2L 0x15 /* i.MX31L 1.2, 3L38W, M45G */
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#define IIM_SREV_2_0_1 0x28 /* i.MX31 2.0/2.0.1, M91E */
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#define IIM_SREV_2_0_1L 0x29 /* i.MX31L 2.0/2.0.1, M91E */
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/* IOMUXC */
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#define IOMUXC_(o) (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o)))
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@ -1618,6 +1634,141 @@
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#define EUARTUTS_RXFULL (1 << 3) // RxFIFO full
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#define EUARTUTS_SOFTRST (1 << 0) // Software reset
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/* SDMA */
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#define SDMA_MC0PTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x000))
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#define SDMA_INTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x004))
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#define SDMA_STOP_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x008))
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#define SDMA_HSTART (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x00C))
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#define SDMA_EVTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x010))
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#define SDMA_DSPOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x014))
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#define SDMA_HOSTOVR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x018))
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#define SDMA_EVTPEND (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x01C))
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#define SDMA_DSPENBL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x020))
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#define SDMA_RESET (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x024))
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#define SDMA_EVTERR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x028))
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#define SDMA_INTRMSK (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x02C))
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#define SDMA_PSW (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x030))
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#define SDMA_EVTERRDBG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x034))
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#define SDMA_CONFIG (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x038))
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#define SDMA_ONCE_ENB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x040))
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#define SDMA_ONCE_DATA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x044))
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#define SDMA_ONCE_INSTR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x048))
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#define SDMA_ONCE_STAT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x04C))
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#define SDMA_ONCE_CMD (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x050))
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#define SDMA_EVT_MIRROR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x054))
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#define SDMA_ILLINSTADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x058))
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#define SDMA_CHN0ADDR (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x05C))
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#define SDMA_ONCE_RTB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x060))
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#define SDMA_XTRIG_CONF1 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x070))
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#define SDMA_XTRIG_CONF2 (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x074))
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/* SDMA_CHNENBL: 0x080 - 0x0FC */
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#define SDMA_CHNENBL(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x080))[n]) /* 0..31 */
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/* SDMA_CHNPRI: 0x100 - 0x17C */
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#define SDMA_CHNPRI(n) (((REG32_PTR_T)(SDMA_BASE_ADDR + 0x100))[n]) /* 0..31 */
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#define SDMA_ONCE_COUNT (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x200))
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#define SDMA_ONCE_ECTL (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x204))
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#define SDMA_ONCE_EAA (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x208))
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#define SDMA_ONCE_EAB (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x20C))
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#define SDMA_ONCE_EAM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x210))
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#define SDMA_ONCE_ED (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x214))
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#define SDMA_ONCE_EDM (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x218))
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#define SDMA_ONCE_PCMATCH (*(REG32_PTR_T)(SDMA_BASE_ADDR + 0x21C))
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/* SDMA_RESET */
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#define SDMA_RESET_RESCHED (0x1 << 1)
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#define SDMA_RESET_RESET (0x1 << 0)
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/* SDMA_PSW */
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#define SDMA_PSW_NCP (0x7 << 13)
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#define SDMA_PSW_NCR (0x1f << 8)
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#define SDMA_PSW_CCP (0x7 << 5)
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#define SDMA_PSW_CCR (0x1f << 0)
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/* SDMA_CONFIG */
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#define SDMA_CONFIG_DSPDMA (0x1 << 12)
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#define SDMA_CONFIG_RTDOBS (0x1 << 11)
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#define SDMA_CONFIG_ACR (0x1 << 4)
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#define SDMA_CONFIG_CSM (0x3 << 0)
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#define SDMA_CONFIG_CSM_STATIC (0x0 << 0)
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#define SDMA_CONFIG_CSM_DYNAMIC_LOW_POWER (0x1 << 0)
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#define SDMA_CONFIG_CSM_DYNAMIC_NO_LOOP (0x2 << 0)
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#define SDMA_CONFIG_CSM_DYNAMIC (0x3 << 0)
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/* SDMA_ONCE_ENB */
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#define SDMA_ONCE_ENB_ENB (0x1 << 0)
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/* SDMA_ONCE_STAT */
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#define SDMA_ONCE_STAT_PST (0xf << 12)
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#define SDMA_ONCE_STAT_PST_PROGRAM (0x0 << 12)
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#define SDMA_ONCE_STAT_PST_DATA (0x1 << 12)
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#define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW (0x2 << 12)
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#define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP (0x3 << 12)
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#define SDMA_ONCE_STAT_PST_DEBUG (0x4 << 12)
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#define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT (0x5 << 12)
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#define SDMA_ONCE_STAT_PST_SLEEP (0x6 << 12)
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#define SDMA_ONCE_STAT_PST_SAVE (0x7 << 12)
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#define SDMA_ONCE_STAT_PST_PROGRAM_IN_SLEEP (0x8 << 12)
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#define SDMA_ONCE_STAT_PST_DATA_IN_SLEEP (0x9 << 12)
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#define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_SLEEP (0xa << 12)
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#define SDMA_ONCE_STAT_PST_CHANGE_OF_FLOW_IN_LOOP_IN_SLEEP (0xb << 12)
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#define SDMA_ONCE_STAT_PST_DEBUG_IN_SLEEP (0xc << 12)
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#define SDMA_ONCE_STAT_PST_FUNCTIONAL_UNIT_IN_SLEEP (0xd << 12)
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#define SDMA_ONCE_STAT_PST_SLEEP_AFTER_RESET (0xe << 12)
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#define SDMA_ONCE_STAT_PST_RESTORE (0xf << 12)
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#define SDMA_ONCE_STAT_RCV (0x1 << 11)
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#define SDMA_ONCE_STAT_EDR (0x1 << 10)
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#define SDMA_ONCE_STAT_ODR (0x1 << 9)
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#define SDMA_ONCE_STAT_SWB (0x1 << 8)
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#define SDMA_ONCE_STAT_MST (0x1 << 7)
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#define SDMA_ONCE_STAT_ECDR (0x7 << 0)
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#define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRA_COND (0x1 << 0)
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#define SDMA_ONCE_STAT_ECDR_MATCHED_ADDRB_COND (0x1 << 1)
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#define SDMA_ONCE_STAT_ECDR_MATCHED_DATA_COND (0x1 << 2)
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/* SDMA_ONCE_CMD */
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#define SDMA_ONCE_CMD_RSTATUS 0x0
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#define SDMA_ONCE_CMD_DMOV 0x1
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#define SDMA_ONCE_CMD_EXEC_ONCE 0x2
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#define SDMA_ONCE_CMD_RUN_CORE 0x3
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#define SDMA_ONCE_CMD_EXEC_CORE 0x4
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#define SDMA_ONCE_CMD_DEBUG_RQST 0x5
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#define SDMA_ONCE_CMD_RBUFFER 0x6
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/* 7-15 reserved */
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/* SDMA_CHN0ADDR */
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#define SDMA_CHN0ADDR_SMSZ (0x1 << 14)
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/* 13:0 = 0x0050 by default (std. boot code) */
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/* SDMA_EVT_MIRROR */
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#define SDMA_EVT_MIRROR_EVENTS(n) (0x1 << (n))
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/* SDMA_XTRIG_CONF1 */
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#define SDMA_XTRIG_CONF1_CNF3 (0x1 << 30)
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#define SDMA_XTRIG_CONF1_NUM3 (0x1f << 24)
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#define SDMA_XTRIG_CONF1_CNF2 (0x1 << 22)
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#define SDMA_XTRIG_CONF1_NUM2 (0x1f << 16)
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#define SDMA_XTRIG_CONF1_CNF1 (0x1 << 14)
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#define SDMA_XTRIG_CONF1_NUM1 (0x1f << 8)
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#define SDMA_XTRIG_CONF1_CNF0 (0x1 << 6)
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#define SDMA_XTRIG_CONF1_NUM0 (0x1f << 0)
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/* SDMA_XTRIG_CONF2 */
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#define SDMA_XTRIG_CONF2_CNF7 (0x1 << 30)
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#define SDMA_XTRIG_CONF2_NUM7 (0x1f << 24)
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#define SDMA_XTRIG_CONF2_CNF6 (0x1 << 22)
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#define SDMA_XTRIG_CONF2_NUM6 (0x1f << 16)
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#define SDMA_XTRIG_CONF2_CNF5 (0x1 << 14)
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#define SDMA_XTRIG_CONF2_NUM5 (0x1f << 8)
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#define SDMA_XTRIG_CONF2_CNF4 (0x1 << 6)
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#define SDMA_XTRIG_CONF2_NUM4 (0x1f << 0)
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/* SDMA_CHNENBL(n) */
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#define SDMA_CHNENBL_ENBL(n) (0x1 << (n))
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#define L2CC_ENABLED
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/* Assuming 26MHz input clock */
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