From 93220094465f16f6138b851f3a868be231cb32d3 Mon Sep 17 00:00:00 2001
From: Jens Arnold <amiconn@rockbox.org>
Date: Fri, 14 Oct 2005 05:52:24 +0000
Subject: [PATCH] Coldfire: (1) Keep the correct CRSEL and CLSEL values in the
 PLLCR register for CPUFREQ_DEFAULT. Fixes non-working treble & bass controls
 in radio screen. (2) Save a bit more power by powering down the PLL at
 CPUFREQ_DEFAULT.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7629 a1c6a512-1295-4272-9138-f99709370657
---
 firmware/system.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/firmware/system.c b/firmware/system.c
index 2eddc49a77..5694f60505 100644
--- a/firmware/system.c
+++ b/firmware/system.c
@@ -584,6 +584,8 @@ int system_memory_guard(int newmode)
 void set_cpu_frequency (long) __attribute__ ((section (".icode")));
 void set_cpu_frequency(long frequency)
 {
+    int i;
+
     switch(frequency)
     {
     case CPUFREQ_MAX:
@@ -622,8 +624,9 @@ void set_cpu_frequency(long frequency)
     default:
         DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER;  
               /* Refresh timer for bypass frequency */
-        PLLCR = 0x00000000;  /* Bypass mode */
+        PLLCR &= ~1;  /* Bypass mode */
         timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true);
+        PLLCR = 0x10800200; /* Power down PLL, but keep CLSEL and CRSEL */
         CSCR0 = 0x00000180; /* Flash: 0 wait states */
         CSCR1 = 0x00000180; /* LCD: 0 wait states */
         cpu_frequency = CPUFREQ_DEFAULT;