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Define CACHEALIGN_BITS for missing ARM CPUs for later use.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28619 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Andree Buschmann 2010-11-19 07:17:20 +00:00
parent 1abc5b8ea8
commit 90a5a8a068
4 changed files with 6 additions and 1 deletions
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1
firmware/export/imx31l.h
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@ -38,7 +38,6 @@
#define FRAME ((void *)(FRAME_PHYS_ADDR+0x100000-CSD0_BASE_ADDR))
#define CACHEALIGN_BITS 5
#define CACHEALIGN_SIZE 32
#define NOCACHE_BASE CSD0_BASE_ADDR
/* USBOTG */