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Really fix the MIPS cache bug this time

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In fixing the original bug I tried to optimize discard_dcache_range()
to minimize writeback and inadvertently introduced a second bug, which
typically ends in a TLB refill panic.

It occurs only if the range fits within one cache line, and when both
the start and end of the range are not aligned to a cache line. This
causes ptr to be incremented and end to be decremented, so ptr > end,
and the loop can't terminate.

Change-Id: Ibaac072f1369268d3327d534ad08ef9dcee3db65
This commit is contained in:
Aidan MacDonald 2021-03-03 23:48:49 +00:00
parent cde5ae755f
commit 8cb4c18310
1 changed files with 1 additions and 1 deletions
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2
firmware/target/mips/mmu-mips.c
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@ -235,7 +235,7 @@ void discard_dcache_range(const void *base, unsigned int size)
}
/* Interior of region is safe to discard */
for(; ptr != end; ptr += CACHEALIGN_SIZE)
for(; ptr <= end; ptr += CACHEALIGN_SIZE)
__CACHE_OP(DCHitInv, ptr);
SYNC_WB();