forked from len0rd/rockbox
* Add basic (non-working) support for NAND flash
* Add panicf() handling * Add not-yet-enabled dma acceleration * Other (minor) fixes git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18203 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Maurus Cuelenaere
parent
496e1f7e85
commit
88ae9024e4
10 changed files with 455 additions and 135 deletions
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@ -42,86 +42,6 @@ static void audiotest(void)
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__aic_enable_loopback();
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}
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#define JZ_NAND_SELECT(n) (REG_EMC_NFCSR |= (EMC_NFCSR_NFCE##n | EMC_NFCSR_NFE##n) )
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#define JZ_NAND_DESELECT(n) (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE##n | EMC_NFCSR_NFE##n) )
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#define NAND_CMD_READ1_00 0x00
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#define NAND_CMD_READ_ID1 0x90
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#define NAND_CMD_READ_ID2 0x91
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#define NANDFLASH_CLE 0x00008000 //PA[15]
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#define NANDFLASH_ALE 0x00010000 //PA[16]
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#define NANDFLASH_BASE 0xB8000000
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#define REG_NAND_DATA (*((volatile unsigned char *) NANDFLASH_BASE))
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#define REG_NAND_CMD (*((volatile unsigned char *) (NANDFLASH_BASE + NANDFLASH_CLE)))
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#define REG_NAND_ADDR (*((volatile unsigned char *) (NANDFLASH_BASE + NANDFLASH_ALE)))
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static void jz_nand_scan_id(void)
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{
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unsigned char cData[5];
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unsigned int dwNandID;
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REG_EMC_NFCSR = 0;
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JZ_NAND_SELECT(1);
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REG_NAND_CMD = NAND_CMD_READ_ID1;
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REG_NAND_ADDR = NAND_CMD_READ1_00;
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cData[0] = REG_NAND_DATA;
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cData[1] = REG_NAND_DATA;
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cData[2] = REG_NAND_DATA;
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cData[3] = REG_NAND_DATA;
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cData[4] = REG_NAND_DATA;
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JZ_NAND_DESELECT(1);
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dwNandID = ((cData[0] & 0xff) << 8) | (cData[1] & 0xff);
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printf("NAND Flash 1: 0x%x is found [0x%x 0x%x 0x%x]", dwNandID, cData[2], cData[3], cData[4]);
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JZ_NAND_SELECT(2);
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REG_NAND_CMD = NAND_CMD_READ_ID1;
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REG_NAND_ADDR = NAND_CMD_READ1_00;
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cData[0] = REG_NAND_DATA;
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cData[1] = REG_NAND_DATA;
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cData[2] = REG_NAND_DATA;
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cData[3] = REG_NAND_DATA;
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cData[4] = REG_NAND_DATA;
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JZ_NAND_DESELECT(2);
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dwNandID = ((cData[0] & 0xff) << 8) | (cData[1] & 0xff);
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printf("NAND Flash 2: 0x%x is found [0x%x 0x%x 0x%x]", dwNandID, cData[2], cData[3], cData[4]);
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JZ_NAND_SELECT(3);
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REG_NAND_CMD = NAND_CMD_READ_ID1;
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REG_NAND_ADDR = NAND_CMD_READ1_00;
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cData[0] = REG_NAND_DATA;
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cData[1] = REG_NAND_DATA;
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cData[2] = REG_NAND_DATA;
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cData[3] = REG_NAND_DATA;
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cData[4] = REG_NAND_DATA;
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JZ_NAND_DESELECT(3);
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dwNandID = ((cData[0] & 0xff) << 8) | (cData[1] & 0xff);
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printf("NAND Flash 3: 0x%x is found [0x%x 0x%x 0x%x]", dwNandID, cData[2], cData[3], cData[4]);
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JZ_NAND_SELECT(4);
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REG_NAND_CMD = NAND_CMD_READ_ID1;
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REG_NAND_ADDR = NAND_CMD_READ1_00;
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cData[0] = REG_NAND_DATA;
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cData[1] = REG_NAND_DATA;
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cData[2] = REG_NAND_DATA;
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cData[3] = REG_NAND_DATA;
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cData[4] = REG_NAND_DATA;
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JZ_NAND_DESELECT(4);
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dwNandID = ((cData[0] & 0xff) << 8) | (cData[1] & 0xff);
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printf("NAND Flash 4: 0x%x is found [0x%x 0x%x 0x%x]", dwNandID, cData[2], cData[3], cData[4]);
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}
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int main(void)
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{
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kernel_init();
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@ -133,20 +53,21 @@ int main(void)
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backlight_init();
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/* To make the Windows say "ding-dong".. */
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ata_init();
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/* To make Windows say "ding-dong".. */
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REG8(USB_REG_POWER) &= ~USB_POWER_SOFTCONN;
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int touch, btn;
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char datetime[30];
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reset_screen();
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printf("Rockbox bootloader v0.000001");
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jz_nand_scan_id();
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printf("REG_EMC_SACR0: 0x%x", REG_EMC_SACR0 >> EMC_SACR_BASE_BIT);
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printf("REG_EMC_SACR1: 0x%x", REG_EMC_SACR1 >> EMC_SACR_BASE_BIT);
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printf("REG_EMC_SACR2: 0x%x", REG_EMC_SACR2 >> EMC_SACR_BASE_BIT);
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printf("REG_EMC_SACR3: 0x%x", REG_EMC_SACR3 >> EMC_SACR_BASE_BIT);
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printf("REG_EMC_SACR4: 0x%x", REG_EMC_SACR4 >> EMC_SACR_BASE_BIT);
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printf("REG_EMC_DMAR0: 0x%x", REG_EMC_DMAR0 >> EMC_DMAR_BASE_BIT);
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printf("REG_EMC_SACR0: 0x%x", REG_EMC_SACR0);
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printf("REG_EMC_SACR1: 0x%x", REG_EMC_SACR1);
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printf("REG_EMC_SACR2: 0x%x", REG_EMC_SACR2);
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printf("REG_EMC_SACR3: 0x%x", REG_EMC_SACR3);
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printf("REG_EMC_SACR4: 0x%x", REG_EMC_SACR4);
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printf("REG_EMC_DMAR0: 0x%x", REG_EMC_DMAR0);
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unsigned int cpu_id = read_c0_prid();
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printf("CPU_ID: 0x%x", cpu_id);
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printf(" * Company ID: 0x%x", (cpu_id >> 16) & 7);
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@ -165,6 +86,29 @@ int main(void)
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if(read_c0_config1() & (1 << 5)) printf(" * MDMX available");
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if(read_c0_config1() & (1 << 6)) printf(" * CP2 available");
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printf("C0_STATUS: 0x%x", read_c0_status());
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unsigned char testdata[4096];
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char msg[30];
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int j = 0;
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while(1)
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{
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memset(testdata, 0, 4096);
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jz_nand_read_page(j, &testdata);
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reset_screen();
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printf("Page %d", j);
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int i;
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for(i=0; i<16; i+=8)
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{
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snprintf(msg, 30, "%x%x%x%x%x%x%x%x", testdata[i], testdata[i+1], testdata[i+2], testdata[i+3], testdata[i+4], testdata[i+5], testdata[i+6], testdata[i+7]);
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printf(msg);
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}
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while(!((btn = button_read_device(&touch)) & (BUTTON_VOL_UP|BUTTON_VOL_DOWN)));
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if(btn & BUTTON_VOL_UP)
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j++;
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if(btn & BUTTON_VOL_DOWN)
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j--;
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if(j<0)
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j = 0;
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}
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while(1)
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{
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btn = button_read_device(&touch);
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@ -1662,13 +1662,13 @@
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#define EMC_SMCR_TAS_BIT 8
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#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
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#define EMC_SMCR_BW_BIT 6
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#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
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#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) /* Bus Width? */
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#define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
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#define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
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#define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
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#define EMC_SMCR_BCM (1 << 3)
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#define EMC_SMCR_BL_BIT 1
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#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
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#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) /* Bus Latency? */
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#define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
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#define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
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#define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
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@ -129,6 +129,9 @@ void panicf( const char *fmt, ...)
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#endif /* CONFIG_KEYPAD */
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#elif defined(CREATIVE_ZVx)
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if(false)
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#elif defined(ONDA_VX747)
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/* check for power button without including any .h file */
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if( (~(*(volatile unsigned int *)(0xB0010300))) & (1 << 29) )
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#endif /* CPU */
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system_reboot();
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#endif /* !SIMULATOR */
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@ -22,6 +22,9 @@
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#include "config.h"
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#include "jz4740.h"
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#include "ata.h"
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#include "nand_id.h"
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#include "system.h"
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#include "panic.h"
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#define NAND_CMD_READ1_00 0x00
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#define NAND_CMD_READ1_01 0x01
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@ -35,21 +38,219 @@
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#define NAND_CMD_BLOCK_ERASE_CONFIRM 0xD0
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#define NAND_CMD_READ_STATUS 0x70
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#define NANDFLASH_CLE 0x00008000 //PA[15]
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#define NANDFLASH_ALE 0x00010000 //PA[16]
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#define NANDFLASH_CLE 0x00008000 //PA[15]
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#define NANDFLASH_ALE 0x00010000 //PA[16]
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#define NANDFLASH_BASE 0xB8000000
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#define REG_NAND_DATA (*((volatile unsigned char *) NANDFLASH_BASE))
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#define REG_NAND_CMD (*((volatile unsigned char *) (NANDFLASH_BASE + NANDFLASH_CLE)))
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#define REG_NAND_ADDR (*((volatile unsigned char *) (NANDFLASH_BASE + NANDFLASH_ALE)))
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#define NANDFLASH_BASE 0xB8000000
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#define REG_NAND_DATA (*((volatile unsigned char *)NANDFLASH_BASE))
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#define REG_NAND_CMD (*((volatile unsigned char *)(NANDFLASH_BASE + NANDFLASH_CLE)))
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#define REG_NAND_ADDR (*((volatile unsigned char *)(NANDFLASH_BASE + NANDFLASH_ALE)))
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#define JZ_NAND_SET_CLE (NANDFLASH_BASE |= NANDFLASH_CLE)
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#define JZ_NAND_CLR_CLE (NANDFLASH_BASE &= ~NANDFLASH_CLE)
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#define JZ_NAND_SET_ALE (NANDFLASH_BASE |= NANDFLASH_ALE)
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#define JZ_NAND_CLR_ALE (NANDFLASH_BASE &= ~NANDFLASH_ALE)
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#define JZ_NAND_SELECT (REG_EMC_NFCSR |= EMC_NFCSR_NFCE1 )
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#define JZ_NAND_DESELECT (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
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#define JZ_NAND_SELECT (REG_EMC_NFCSR |= EMC_NFCSR_NFCE1 )
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#define JZ_NAND_DESELECT (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
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#define __nand_enable() (REG_EMC_NFCSR |= (EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1))
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#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
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#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
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#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
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#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
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#define __nand_ecc_rs_encoding() \
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(REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING)
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#define __nand_ecc_rs_decoding() \
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(REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING)
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#define my__gpio_as_nand() \
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do { \
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REG_GPIO_PXFUNS(1) = 0x1E018000; \
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REG_GPIO_PXSELC(1) = 0x1E018000; \
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REG_GPIO_PXFUNS(2) = 0x30000000; \
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REG_GPIO_PXSELC(2) = 0x30000000; \
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REG_GPIO_PXFUNC(2) = 0x40000000; \
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REG_GPIO_PXSELC(2) = 0x40000000; \
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REG_GPIO_PXDIRC(2) = 0x40000000; \
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REG_GPIO_PXFUNS(1) = 0x00400000; \
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REG_GPIO_PXSELC(1) = 0x00400000; \
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} while (0)
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static struct nand_info* chip_info = NULL;
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#define NAND_BLOCK_SIZE (chip_info->pages_per_block * chip_info->page_size)
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#define NAND_OOB_SIZE (chip_info->page_size / 32)
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struct nand_page_info_t
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{
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unsigned char block_status;
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unsigned int reserved;
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unsigned short block_addr_field;
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unsigned int lifetime;
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unsigned char ecc_field[50];//[NAND_OOB_SIZE - 11];
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} __attribute__ ((packed));
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static void nand_wait_ready(void)
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{
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int wait = 100;
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while(REG_GPIO_PXPIN(2) & (1 << 30) && wait--);
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while (!(REG_GPIO_PXPIN(2) & 0x40000000));
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}
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static inline void nand_read_memcpy(void *target, void *source, unsigned int len)
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{
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int ch = 2;
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if(((unsigned int)source < 0xa0000000) && len)
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dma_cache_wback_inv((unsigned long)source, len);
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if(((unsigned int)target < 0xa0000000) && len)
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dma_cache_wback_inv((unsigned long)target, len);
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REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long)source);
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REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long)target);
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REG_DMAC_DTCR(ch) = len / 4;
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REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO;
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REG_DMAC_DCMD(ch) = DMAC_DCMD_SAI | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT;
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REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
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while ( REG_DMAC_DTCR(ch) );
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}
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static void rs_correct(unsigned char *buf, int idx, int mask)
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{
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int i, j;
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unsigned short d, d1, dm;
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i = (idx * 9) >> 3;
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j = (idx * 9) & 0x7;
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i = (j == 0) ? (i - 1) : i;
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j = (j == 0) ? 7 : (j - 1);
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if(i >= 512)
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return;
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d = (buf[i] << 8) | buf[i - 1];
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d1 = (d >> j) & 0x1ff;
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d1 ^= mask;
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dm = ~(0x1ff << j);
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d = (d & dm) | (d1 << j);
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buf[i - 1] = d & 0xff;
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buf[i] = (d >> 8) & 0xff;
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}
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static inline int nand_rs_correct(unsigned char *data)
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{
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unsigned int stat = REG_EMC_NFINTS;
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if (stat & EMC_NFINTS_ERR) {
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if (stat & EMC_NFINTS_UNCOR)
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{
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panicf("Uncorrectable ECC error occurred!\n stat = 0x%x", stat);
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return -1;
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}
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else
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{
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unsigned int errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
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switch (errcnt)
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{
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case 4:
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rs_correct(data, (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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break;
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case 3:
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rs_correct(data, (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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break;
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case 2:
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rs_correct(data, (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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break;
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case 1:
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rs_correct(data, (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
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break;
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}
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}
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}
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return 0;
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}
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static inline void nand_send_readaddr(unsigned int pageaddr, unsigned int offset)
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{
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int i;
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/* Read command */
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REG_NAND_CMD = 0x00;
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/* Write column address */
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for (i = 0; i < chip_info->col_cycles; i++)
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{
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REG_NAND_ADDR = offset & 0xFF;
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offset = offset >> 8;
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}
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/* Write row address */
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for (i = 0; i < chip_info->row_cycles; i++)
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{
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REG_NAND_ADDR = pageaddr & 0xFF;
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pageaddr = pageaddr >> 8;
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}
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}
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static inline void nand_send_readcacheaddr(unsigned short offset)
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{
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REG_NAND_CMD = 0x05;
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REG_NAND_ADDR = (unsigned char)((offset & 0x000000FF) >> 0);
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REG_NAND_ADDR = (unsigned char)((offset & 0x0000FF00) >> 8);
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REG_NAND_CMD = 0xe0;
|
||||
}
|
||||
|
||||
static inline int nand_read_oob(int page, unsigned char *data)
|
||||
{
|
||||
unsigned short i;
|
||||
|
||||
nand_send_readaddr(page, chip_info->page_size);
|
||||
|
||||
REG_NAND_CMD = 0x30;
|
||||
|
||||
nand_wait_ready();
|
||||
|
||||
for ( i = 0; i < NAND_OOB_SIZE; i++)
|
||||
*data++ = REG_NAND_ADDR;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nand_read_page_info(int page, struct nand_page_info_t *info)
|
||||
{
|
||||
int ret;
|
||||
|
||||
JZ_NAND_SELECT;
|
||||
ret = nand_read_oob(page, (unsigned char*)info);
|
||||
JZ_NAND_DESELECT;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct nand_page_info_t page_info;
|
||||
|
||||
int jz_nand_read_page (int page, unsigned char *data)
|
||||
{
|
||||
int ret, i;
|
||||
|
||||
JZ_NAND_SELECT;
|
||||
ret = nand_read_oob(page, &page_info);
|
||||
|
||||
nand_send_readcacheaddr(0);
|
||||
|
||||
/* TODO: use information from page_info */
|
||||
|
||||
for ( i = 0; i < chip_info->page_size; i++)
|
||||
*data++ = REG_NAND_ADDR;
|
||||
|
||||
JZ_NAND_DESELECT;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int ata_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf)
|
||||
{
|
||||
|
|
@ -67,26 +268,40 @@ int ata_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const v
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int jz_device_ready(void)
|
||||
{
|
||||
int ready, wait = 10;
|
||||
while (wait--);
|
||||
ready = __gpio_get_pin(32*2+30);
|
||||
return ready;
|
||||
}
|
||||
|
||||
int ata_init(void)
|
||||
{
|
||||
/*
|
||||
* EMC setup
|
||||
*/
|
||||
/* Read/Write timings */
|
||||
#define SET_STANDARD_TIMING(x) x = (((x) & ~0xFF) | 0x4621200)
|
||||
SET_STANDARD_TIMING(REG_EMC_SMCR1);
|
||||
SET_STANDARD_TIMING(REG_EMC_SMCR2);
|
||||
SET_STANDARD_TIMING(REG_EMC_SMCR3);
|
||||
SET_STANDARD_TIMING(REG_EMC_SMCR4);
|
||||
|
||||
/* Set NFE bit */
|
||||
REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
|
||||
/* Set NFE bit */
|
||||
REG_EMC_NFCSR = EMC_NFCSR_NFE1;
|
||||
|
||||
__nand_ecc_disable();
|
||||
|
||||
unsigned char cData[5];
|
||||
JZ_NAND_SELECT;
|
||||
REG_NAND_CMD = NAND_CMD_READ_ID1;
|
||||
REG_NAND_ADDR = NAND_CMD_READ1_00;
|
||||
cData[0] = REG_NAND_DATA;
|
||||
cData[1] = REG_NAND_DATA;
|
||||
cData[2] = REG_NAND_DATA;
|
||||
cData[3] = REG_NAND_DATA;
|
||||
cData[4] = REG_NAND_DATA;
|
||||
JZ_NAND_DESELECT;
|
||||
|
||||
chip_info = nand_identify(cData);
|
||||
if(chip_info == NULL)
|
||||
{
|
||||
panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0],
|
||||
cData[1], cData[2], cData[3], cData[4]);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Set timings */
|
||||
|
||||
/* Read/Write timings */
|
||||
REG_EMC_SMCR1 = (EMC_SMCR_BL_4 | EMC_SMCR_BW_8BIT | 4 << EMC_SMCR_TAS_BIT
|
||||
| 4 << EMC_SMCR_TAH_BIT | 4 << EMC_SMCR_TBP_BIT | 4 << EMC_SMCR_TAW_BIT
|
||||
| 4 << EMC_SMCR_STRV_BIT);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -58,7 +58,6 @@ SECTIONS
|
|||
*(.irodata);
|
||||
*(.idata);
|
||||
*(.data*);
|
||||
*(.scommon*);
|
||||
*(.sdata*);
|
||||
. = ALIGN(0x4);
|
||||
_dataend = . ;
|
||||
|
|
@ -92,6 +91,7 @@ SECTIONS
|
|||
*(.bss*);
|
||||
*(.ibss);
|
||||
*(COMMON)
|
||||
*(.scommon*);
|
||||
_end = .;
|
||||
} > DRAM
|
||||
|
||||
|
|
|
|||
|
|
@ -98,14 +98,15 @@ _init_cache_loop:
|
|||
mtc0 t0, C0_CONFIG
|
||||
nop
|
||||
|
||||
//----------------------------------------------------
|
||||
// clear BSS section
|
||||
//----------------------------------------------------
|
||||
la t0, _edata
|
||||
la t1, _end
|
||||
1: sw zero, 0(t0)
|
||||
bne t0, t1, 1b
|
||||
addiu t0, 4
|
||||
//----------------------------------------------------
|
||||
// clear BSS section
|
||||
//----------------------------------------------------
|
||||
la t0, _edata
|
||||
la t1, _end
|
||||
_init_bss_loop:
|
||||
sw zero, 0(t0)
|
||||
bne t0, t1, _init_bss_loop
|
||||
addiu t0, 4
|
||||
|
||||
//----------------------------------------------------
|
||||
// setup stack, jump to C code
|
||||
|
|
|
|||
119
firmware/target/mips/ingenic_jz47xx/dma_acc-jz4740.c
Normal file
119
firmware/target/mips/ingenic_jz47xx/dma_acc-jz4740.c
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright (C) 2008 by Maurus Cuelenaere
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include "system.h"
|
||||
|
||||
void memset(void *target, unsigned char c, size_t len)
|
||||
{
|
||||
int ch = DMA_CHANNEL;
|
||||
unsigned int d;
|
||||
unsigned char *dp;
|
||||
|
||||
if(len < 32)
|
||||
_memset(target,c,len);
|
||||
else
|
||||
{
|
||||
if(((unsigned int)target < 0xa0000000) && len)
|
||||
dma_cache_wback_inv((unsigned long)target, len);
|
||||
|
||||
dp = (unsigned char *)((unsigned int)(&d) | 0xa0000000);
|
||||
*(dp + 0) = c;
|
||||
*(dp + 1) = c;
|
||||
*(dp + 2) = c;
|
||||
*(dp + 3) = c;
|
||||
REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long)dp);
|
||||
REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long)target);
|
||||
REG_DMAC_DTCR(ch) = len / 32;
|
||||
REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO;
|
||||
REG_DMAC_DCMD(ch) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BYTE;
|
||||
REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
|
||||
|
||||
while (REG_DMAC_DTCR(ch));
|
||||
if(len % 32)
|
||||
{
|
||||
dp = (unsigned char *)((unsigned int)target + (len & (32 - 1)));
|
||||
for(d = 0;d < (len % 32); d++)
|
||||
*dp++ = c;
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void memset16(void *target, unsigned short c, size_t len)
|
||||
{
|
||||
int ch = DMA_CHANNEL;
|
||||
unsigned short d;
|
||||
unsigned short *dp;
|
||||
|
||||
if(len < 32)
|
||||
_memset16(target,c,len);
|
||||
else
|
||||
{
|
||||
if(((unsigned int)target < 0xa0000000) && len)
|
||||
dma_cache_wback_inv((unsigned long)target, len);
|
||||
|
||||
d = c;
|
||||
REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long)&d);
|
||||
REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long)target);
|
||||
REG_DMAC_DTCR(ch) = len / 32;
|
||||
REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO;
|
||||
REG_DMAC_DCMD(ch) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_32BYTE;
|
||||
REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
|
||||
|
||||
while (REG_DMAC_DTCR(ch));
|
||||
if(len % 32)
|
||||
{
|
||||
dp = (unsigned short *)((unsigned int)target + (len & (32 - 1)));
|
||||
for(d = 0; d < (len % 32); d++)
|
||||
*dp++ = c;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void memcpy(void *target, const void *source, size_t len)
|
||||
{
|
||||
int ch = DMA_CHANNEL;
|
||||
unsigned char *dp;
|
||||
|
||||
if(len < 4)
|
||||
_memcpy(target, source, len);
|
||||
|
||||
if(((unsigned int)source < 0xa0000000) && len)
|
||||
dma_cache_wback_inv((unsigned long)source, len);
|
||||
|
||||
if(((unsigned int)target < 0xa0000000) && len)
|
||||
dma_cache_wback_inv((unsigned long)target, len);
|
||||
|
||||
REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long)source);
|
||||
REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long)target);
|
||||
REG_DMAC_DTCR(ch) = len / 4;
|
||||
REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO;
|
||||
REG_DMAC_DCMD(ch) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT;
|
||||
|
||||
REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
|
||||
while (REG_DMAC_DTCR(ch));
|
||||
if(len % 4)
|
||||
{
|
||||
dp = (unsigned char*)((unsigned int)target + (len & (4 - 1)));
|
||||
for(i = 0; i < (len % 4); i++)
|
||||
*dp++ = *source;
|
||||
}
|
||||
}
|
||||
|
|
@ -209,6 +209,28 @@ void __dcache_writeback_all(void)
|
|||
SYNC_WB();
|
||||
}
|
||||
|
||||
void dma_cache_wback_inv(unsigned long addr, unsigned long size)
|
||||
{
|
||||
unsigned long end, a;
|
||||
|
||||
if (size >= CACHE_SIZE)
|
||||
__dcache_writeback_all();
|
||||
else
|
||||
{
|
||||
unsigned long dc_lsize = CACHE_LINE_SIZE;
|
||||
|
||||
a = addr & ~(dc_lsize - 1);
|
||||
end = (addr + size - 1) & ~(dc_lsize - 1);
|
||||
while (1)
|
||||
{
|
||||
__flush_dcache_line(a); /* Hit_Writeback_Inv_D */
|
||||
if (a == end)
|
||||
break;
|
||||
a += dc_lsize;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
extern void (*tick_funcs[MAX_NUM_TICK_TASKS])(void);
|
||||
|
||||
#define USE_RTC_CLOCK 0
|
||||
|
|
@ -251,15 +273,21 @@ extern unsigned int _vectorsend; /* see boot.lds/app.lds */
|
|||
void system_main(void)
|
||||
{
|
||||
cli();
|
||||
write_c0_status(0x10000400);
|
||||
write_c0_status(1 << 28 | 1 << 10); /* Enable CP | Mask interrupt 2 */
|
||||
|
||||
memcpy((void *)A_K0BASE, (void *)&_loadaddress, 0x20);
|
||||
memcpy((void *)A_K0BASE, (void *)&_vectorsstart, 0x20);
|
||||
memcpy((void *)(A_K0BASE + 0x180), (void *)&_vectorsstart, 0x20);
|
||||
memcpy((void *)(A_K0BASE + 0x200), (void *)&_vectorsstart, 0x20);
|
||||
|
||||
__dcache_writeback_all();
|
||||
__icache_invalidate_all();
|
||||
|
||||
(*((unsigned int*)(0x80000200))) = 0x42;
|
||||
(*((unsigned int*)(0x80000204))) = 0x45;
|
||||
(*((unsigned int*)(0x80000208))) = 0x10020;
|
||||
|
||||
set_c0_status(1 << 22); /* Enable Boot Exception Vectors */
|
||||
|
||||
sti();
|
||||
|
||||
detect_clock();
|
||||
|
|
|
|||
|
|
@ -101,11 +101,13 @@ static inline void restore_interrupt(int status)
|
|||
#define swap32(x) (((x) & 0xff) << 24 | ((x) & 0xff00) << 8 | ((x) & 0xff0000) >> 8 | ((x) >> 24) & 0xff)
|
||||
|
||||
#define UNCACHED_ADDRESS(addr) ((unsigned int)(addr) | 0xA0000000)
|
||||
#define PHYSADDR(x) ((x) & 0x1fffffff)
|
||||
|
||||
void __dcache_writeback_all(void);
|
||||
void __dcache_invalidate_all(void);
|
||||
void __icache_invalidate_all(void);
|
||||
void __flush_dcache_line(unsigned long addr);
|
||||
void dma_cache_wback_inv(unsigned long addr, unsigned long size);
|
||||
void sti(void);
|
||||
void cli(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -1128,10 +1128,18 @@ static inline void core_sleep(void)
|
|||
REG_CPM_LCR &= ~CPM_LCR_LPM_MASK;
|
||||
REG_CPM_LCR |= CPM_LCR_LPM_SLEEP;
|
||||
*/
|
||||
asm volatile(".set mips3 \n"
|
||||
"wait \n"
|
||||
".set mips0 \n"
|
||||
#if 0
|
||||
asm volatile(".set mips32 \n"
|
||||
"mfc0 t0, 12 \n"
|
||||
"move t1, t0 \n"
|
||||
"ori t0, t0, 0x8000000 \n" /* Enable reduced power mode */
|
||||
"mtc0 t0, 12 \n"
|
||||
"wait \n"
|
||||
"mtc0 t1, 12 \n"
|
||||
".set mips0 \n"
|
||||
::: "t0", "t1"
|
||||
);
|
||||
#endif
|
||||
/*
|
||||
REG_CPM_LCR &= ~CPM_LCR_LPM_MASK;
|
||||
REG_CPM_LCR |= CPM_LCR_LPM_IDLE;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue