forked from len0rd/rockbox
Gigabeat S (imx31): Begin voltage and frequency scaling code. For now, to avoid overdrive voltage, just lower core voltage to 1.35V since voltage scaling shouldn't be required for frequencies lower than 399 MHz (according to Freescale BSP, which set all working points to 1.35V for those frequencies). Perhaps battery life will improve as well (cross fingers :).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25506 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
48789c5361
commit
87eea33def
7 changed files with 332 additions and 0 deletions
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@ -1410,6 +1410,101 @@
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#define CCM_PDR1_SSI1_PODF (0x3f << 0)
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#define CCM_PDR1_SSI1_PODF_POS (0)
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/* RCSR */
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#define CCM_RCSR_NF16B (1 << 31)
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#define CCM_RCSR_NFMS (1 << 30)
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#define CCM_RCSR_BTP4 (1 << 27)
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#define CCM_RCSR_BTP3 (1 << 26)
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#define CCM_RCSR_BTP2 (1 << 25)
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#define CCM_RCSR_BTP1 (1 << 24)
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#define CCM_RCSR_BTP0 (1 << 23)
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#define CCM_RCSR_OSCNT (0x7f << 16)
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#define CCM_RCSR_OSCNT_POS (16)
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#define CCM_RCSR_PERES (1 << 15)
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#define CCM_RCSR_SDM (0x3 << 12)
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#define CCM_RCSR_SDM_POS (12)
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#define CCM_RCSR_GPF (0x7 << 5)
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#define CCM_RCSR_GPF_POS (5)
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#define CCM_RCSR_WFIS (1 << 4)
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#define CCM_RCSR_REST (0x7 << 0)
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#define CCM_RCSR_REST_POS (0)
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#define CCM_RCSR_REST_POR_EXT (0x0)
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#define CCM_RCSR_REST_QUALIFIED_EXT (0x1)
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#define CCM_RCSR_REST_WATCHDOG_TMO (0x2)
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/* 0x3 - 0x5: reserved */
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#define CCM_RCSR_REST_JTAG (0x6)
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#define CCM_RCSR_REST_ARM11P_GATING (0x7)
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/* MPCTL */
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#define CCM_MPCTL_BRM (1 << 31)
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#define CCM_MPCTL_PD (0xf << 26)
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#define CCM_MPCTL_PD_POS (26)
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#define CCM_MPCTL_MFD (0x3ff << 16)
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#define CCM_MPCTL_MFD_POS (16)
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#define CCM_MPCTL_MFI (0xf << 10)
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#define CCM_MPCTL_MFI_POS (10)
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#define CCM_MPCTL_MFN (0x3ff << 0)
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#define CCM_MPCTL_MFN_POS (0)
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/* UPCTL */
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#define CCM_UPCTL_BRM (1 << 31)
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#define CCM_UPCTL_PD (0xf << 26)
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#define CCM_UPCTL_PD_POS (26)
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#define CCM_UPCTL_MFD (0x3ff << 16)
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#define CCM_UPCTL_MFD_POS (16)
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#define CCM_UPCTL_MFI (0xf << 10)
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#define CCM_UPCTL_MFI_POS (10)
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#define CCM_UPCTL_MFN (0x3ff << 0)
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#define CCM_UPCTL_MFN_POS (0)
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/* SPCTL */
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#define CCM_SPCTL_BRM (1 << 31)
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#define CCM_SPCTL_PD (0xf << 26)
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#define CCM_SPCTL_PD_POS (26)
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#define CCM_SPCTL_MFD (0x3ff << 16)
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#define CCM_SPCTL_MFD_POS (16)
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#define CCM_SPCTL_MFI (0xf << 10)
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#define CCM_SPCTL_MFI_POS (10)
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#define CCM_SPCTL_MFN (0x3ff << 0)
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#define CCM_SPCTL_MFN_POS (0)
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/* COSR */
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#define CCM_COSR_CLKOEN (1 << 9)
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#define CCM_COSR_CLKOUTDIV (0x7 << 6)
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#define CCM_COSR_CLKOUTDIV_POS (6)
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#define CCM_COSR_CLKOSEL (0xf << 0)
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#define CCM_COSR_CLKOSEL_POS (0)
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#define CCM_COSR_CLKOSEL_MPL_DPDGCK_CLK (0x0)
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#define CCM_COSR_CLKOSEL_IPG_CLK_CCM (0x1)
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#define CCM_COSR_CLKOSEL_UPL_DPDGCK_CLK (0x2)
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#define CCM_COSR_CLKOSEL_PLL_REF_CLK (0x3)
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#define CCM_COSR_CLKOSEL_FPM_CKIL512_CLK (0x4)
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#define CCM_COSR_CLKOSEL_IPG_CLK_AHB_ARM (0x5)
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#define CCM_COSR_CLKOSEL_IPG_CLK_ARM (0x6)
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#define CCM_COSR_CLKOSEL_SPL_DPDGCK_CLK (0x7)
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#define CCM_COSR_CLKOSEL_CKIH (0x8)
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#define CCM_COSR_CLKOSEL_IPG_CLK_AHB_EMI_CLK (0x9)
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#define CCM_COSR_CLKOSEL_IPG_CLK_IPU_HSP (0x9)
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#define CCM_COSR_CLKOSEL_IPG_CLK_NFC_20M (0xa)
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#define CCM_COSR_CLKOSEL_IPG_CLK_PERCLK_UART1 (0xb)
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#define CCM_COSR_CLKOSEL_IPG_REF_CIR1 (0xc) /* ref_cir_gateload */
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#define CCM_COSR_CLKOSEL_IPG_REF_CIR2 (0xc) /* ref_cir_intrcload */
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#define CCM_COSR_CLKOSEL_IPG_REF_CIR3 (0xc) /* ref_cir_path */
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/* CGR0 */
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/* CGR1 */
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/* CGR2 */
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/* Handled in ccm-imx31.h and ccm-imx31.c */
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#define CCM_WIMR0_GPIO3 (1 << 0)
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#define CCM_WIMR0_GPIO2 (1 << 1)
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#define CCM_WIMR0_GPIO1 (1 << 2)
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@ -1443,6 +1538,114 @@
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#define CCM_WIMR0_RESERVED30 (1 << 30)
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#define CCM_WIMR0_RESERVED31 (1 << 31)
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/* LDC */
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/* 32 bits specify value */
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/* DCVR0-DCVR3 */
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#define CCM_DCVR_ULV (0x3ff << 22) /* Upper limit */
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#define CCM_DCVR_ULV_POS (22)
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#define CCM_DCVR_LLV (0x3ff << 12) /* Lower limit */
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#define CCM_DCVR_LLV_POS (12)
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#define CCM_DCVR_ELV (0x3ff << 2) /* Emergency limit */
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#define CCM_DCVR_ELV_POS (2)
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#if 0
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enum DVFS_W_SIGS
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{
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DVFS_W_SIGS_M3IF_M0_BUF = 0, /* Hready signal of M3IF's master #0
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(L2 Cache) */
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DVFS_W_SIGS_M3IF_M1 = 1, /* Hready signal of M3IF's master #1
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(L2 Cache) */
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DVFS_W_SIGS_MBX_MBXCLKGATE = 2, /* Hready signal of M3IF's master #2
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(MBX) */
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DVFS_W_SIGS_M3IF_M3 = 3, /* Hready signal of M3IF's master #3
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(MAX) */
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DVFS_W_SIGS_M3IF_M4 = 4, /* Hready signal of M3IF's master #4
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(SDMA) */
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DVFS_W_SIGS_M3IF_M5 = 5, /* Hready signal of M3IF's master #5
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(mpeg4_vga_encoder) */
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DVFS_W_SIGS_M3IF_M6 = 6, /* Hready signal of M3IF's master #6
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(IPU) */
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DVFS_W_SIGS_M3IF_M7 = 7, /* Hready signal of M3IF's master #7
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(IPU) */
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DVFS_W_SIGS_ARM11_P_IRQ_B_RBT_GATE = 8, /* ARM normal interrupt */
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DVFS_W_SIGS_ARM11_P_FIQ_B_RBT_GATE = 9, /* ARM fast interrupt */
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DVFS_W_SIGS_IPI_GPIO1_INT0 = 10, /* Interrupt line from GPIO */
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DVFS_W_SIGS_IPI_INT_IPU_FUNC = 11, /* Interrupt line from IPU */
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DVFS_W_SIGS_DVGP0 = 12, /* Software-controllable general-purpose
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bits from the CCM */
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DVFS_W_SIGS_DVGP1 = 13, /* Software-controllable general-purpose
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bits from the CCM */
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DVFS_W_SIGS_DVGP2 = 14, /* Software-controllable general-purpose
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bits from the CCM */
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DVFS_W_SIGS_DVGP3 = 15, /* Software-controllable general-purpose
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bits from the CCM */
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};
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#endif
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/* LTR0 */
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#define CCM_LTR0_UPTHR (0x3f << 22)
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#define CCM_LTR0_UPTHR_POS (22)
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#define CCM_LTR0_DNTHR (0x3f << 16)
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#define CCM_LTR0_DNTHR_POS (16)
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/* for div_3_clk */
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#define CCM_LTR0_DIV3CK (0x3 << 1)
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#define CCM_LTR0_DIV3CK_POS (1)
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#define CCM_LTR0_DIV3CK_2048 (0x0 << 1) /* 1/2048 ARM clock */
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#define CCM_LTR0_DIV3CK_8192 (0x1 << 1) /* 1/8192 ARM clock */
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#define CCM_LTR0_DIV3CK_32768 (0x2 << 1) /* 1/32768 ARM clock */
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#define CCM_LTR0_DIV3CK_131072 (0x3 << 1) /* 1/131072 ARM clock */
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/* PMCR0 */
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#define CCM_PMCR0_DVSUP_MCUPLL (1 << 31)
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#define CCM_PMCR0_DVSUP_POST_DIVIDERS (1 << 30)
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#define CCM_PMCR0_DVSUP_DVS (0x3 << 28)
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#define CCM_PMCR0_DVS1_0_DVS0_0 (0x0 << 28) /* Highest frequency/voltage */
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#define CCM_PMCR0_DVS1_0_DVS0_1 (0x1 << 28) /* ... */
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#define CCM_PMCR0_DVS1_1_DVS0_0 (0x2 << 28) /* ... */
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#define CCM_PMCR0_DVS1_1_DVS0_1 (0x3 << 28) /* Lowest frequency/voltage */
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#define CCM_PMCR0_DVS_POS (28)
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#define CCM_PMCR0_UDSC (1 << 27)
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#define CCM_PMCR0_VSCNT (0x7 << 24)
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#define CCM_PMCR0_VSCNT_POS (24)
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#define CCM_PMCR0_DVFEV (1 << 23)
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#define CCM_PMCR0_DVFIS (1 << 22)
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#define CCM_PMCR0_LBMI (1 << 21)
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#define CCM_PMCR0_LBFL (1 << 20)
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#define CCM_PMCR0_LBCF (0x3 << 18)
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#define CCM_PMCR0_LBCF_4 (0x0 << 18)
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#define CCM_PMCR0_LBCF_8 (0x1 << 18)
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#define CCM_PMCR0_LBCF_12 (0x2 << 18)
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#define CCM_PMCR0_LBCF_16 (0x3 << 18)
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#define CCM_PMCR0_PTVIS (1 << 17)
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#define CCM_PMCR0_UPDTEN (1 << 16)
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#define CCM_PMCR0_FSVAIM (1 << 15)
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#define CCM_PMCR0_FSVAI (0x3 << 13)
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#define CCM_PMCR0_FSVAI_NO_INT (0x0 << 13)
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#define CCM_PMCR0_FSVAI_INCREASE (0x1 << 13)
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#define CCM_PMCR0_FSVAI_DECREASE (0x2 << 13)
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#define CCM_PMCR0_FSVAI_INCREASE_NOW (0x3 << 13)
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#define CCM_PMCR0_FSVAI_POS (13)
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#define CCM_PMCR0_DPVCR (1 << 12)
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#define CCM_PMCR0_DPVV (1 << 11)
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#define CCM_PMCR0_WFIM (1 << 10)
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#define CCM_PMCR0_DRCE3 (1 << 9)
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#define CCM_PMCR0_DRCE2 (1 << 8)
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#define CCM_PMCR0_DRCE1 (1 << 7)
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#define CCM_PMCR0_DRCE0 (1 << 6)
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#define CCM_PMCR0_DCR (1 << 5) /* 512 vs 256 count */
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#define CCM_PMCR0_DVFEN (1 << 4)
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#define CCM_PMCR0_PTVAIM (1 << 3)
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#define CCM_PMCR0_PTVAI (0x3 << 1)
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#define CCM_PMCR0_PTVAI_NO_INT (0x0 << 1)
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#define CCM_PMCR0_PTVAI_DECREASE (0x1 << 1)
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#define CCM_PMCR0_PTVAI_INCREASE (0x2 << 1)
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#define CCM_PMCR0_PTVAI_INCREASE_NOW (0x3 << 1)
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#define CCM_PMCR0_DPTEN (1 << 0)
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/* WEIM - CS0 */
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#define CSCRU 0x00
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#define CSCRL 0x04
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