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iPod G3: Clock setup register display and CPU clock estimation in debug menu. * Fix clock being set to only half of what it should be (introduced with clock setup changes for PP502x).

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13844 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2007-07-10 20:47:01 +00:00
parent 696432a2fd
commit 85568d6040
3 changed files with 37 additions and 5 deletions
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29
apps/debug_menu.c
View file

@ -405,7 +405,7 @@ static bool dbg_flash_id(unsigned* p_manufacturer, unsigned* p_device,
#endif /* (CONFIG_CPU == SH7034 || CPU_COLDFIRE) */
#ifndef SIMULATOR
#ifdef CPU_PP502x
#ifdef CPU_PP
static int perfcheck(void)
{
int result;
@ -427,7 +427,13 @@ static int perfcheck(void)
[res]"=&r"(result)
:
[timr]"r"(&USEC_TIMER),
[tmo]"r"(10226)
[tmo]"r"(
#if CONFIG_CPU == PP5002
16000
#else /* PP5020/5022/5024 */
10226
#endif
)
:
"r0", "r1", "r2"
);
@ -586,7 +592,7 @@ static bool dbg_hw_info(void)
snprintf(buf, sizeof(buf), "Est. clock (kHz): %d", perfcheck());
lcd_puts(0, 3, buf);
lcd_update();
while(1)
@ -1181,6 +1187,23 @@ bool dbg_ports(void)
snprintf(buf, sizeof(buf), "GPIO_C: %02x GPIO_D: %02x", gpio_c, gpio_d);
lcd_puts(0, line++, buf);
snprintf(buf, sizeof(buf), "CLOCK_ENABLE: %08lx", CLOCK_ENABLE);
lcd_puts(0, line++, buf);
snprintf(buf, sizeof(buf), "CLOCK_SOURCE: %08lx", CLOCK_SOURCE);
lcd_puts(0, line++, buf);
snprintf(buf, sizeof(buf), "CLOCK_DIV: %08lx", CLOCK_DIV);
lcd_puts(0, line++, buf);
snprintf(buf, sizeof(buf), "PLL_DIV: %08lx", PLL_DIV);
lcd_puts(0, line++, buf);
snprintf(buf, sizeof(buf), "PLL_MULT: %08lx", PLL_MULT);
lcd_puts(0, line++, buf);
snprintf(buf, sizeof(buf), "TIMING1_CTL: %08lx", TIMING1_CTL);
lcd_puts(0, line++, buf);
snprintf(buf, sizeof(buf), "TIMING2_CTL: %08lx", TIMING2_CTL);
lcd_puts(0, line++, buf);
snprintf(buf, sizeof(buf), "Est. clock (kHz): %d", perfcheck());
lcd_puts(0, line++, buf);
lcd_update();
if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL))
return false;

9
firmware/export/pp5002.h
View file

@ -116,6 +116,15 @@
#define SER1_MASK (1 << SER1_IRQ)
#define DMA_OUT_MASK (1 << DMA_OUT_IRQ)
#define TIMING1_CTL (*(volatile unsigned long*)(0xcf004000))
#define TIMING2_CTL (*(volatile unsigned long*)(0xcf004008))
#define CLOCK_ENABLE (*(volatile unsigned long*)(0xcf005008))
#define CLOCK_SOURCE (*(volatile unsigned long*)(0xcf00500c))
#define CLOCK_DIV (*(volatile unsigned long*)(0xcf005010))
#define PLL_DIV (*(volatile unsigned long*)(0xcf005018))
#define PLL_MULT (*(volatile unsigned long*)(0xcf00501c))
#define MMAP0_LOGICAL (*(volatile unsigned long*)(0xf000f000))
#define MMAP0_PHYSICAL (*(volatile unsigned long*)(0xf000f004))
#define MMAP1_LOGICAL (*(volatile unsigned long*)(0xf000f008))

4
firmware/target/arm/system-pp5002.c
View file

@ -100,8 +100,8 @@ void set_cpu_frequency(long frequency)
outl(0x55, 0xcf00500c);
outl(0x6000, 0xcf005010);
/* Clock frequency = (24/8)*postmult */
outl(8, 0xcf005018);
/* Clock frequency = (24/4)*postmult */
outl(4, 0xcf005018);
outl(postmult, 0xcf00501c);
outl(0xe000, 0xcf005010);