forked from len0rd/rockbox
H300: (1) Use DMA for LCD updates, with auto-aligned line reads. Speeds up LCD updates by ~ 75% at 11MHz and 45MHz. Only ~ 11% speedup at 124MHz due to (2). (2) Less aggressive LCD transfer timing at 124MHz. With the previous timing, slightly corrupted display contents was reported, and with DMA transfers at least 4 waitstates are needed to make updates work at all. * A table in system-iriver.c shows settings for all integer multiples of the base clock frequency (info for developers, not yet complete).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11418 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
d86350c9fa
commit
83aded979f
4 changed files with 59 additions and 110 deletions
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@ -368,7 +368,16 @@ void lcd_update(void)
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/* Copy display bitmap to hardware */
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/* Copy display bitmap to hardware */
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lcd_write_reg(R_RAM_ADDR_SET, xoffset << 8);
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lcd_write_reg(R_RAM_ADDR_SET, xoffset << 8);
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lcd_begin_write_gram();
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lcd_begin_write_gram();
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lcd_write_data((unsigned short *)lcd_framebuffer, LCD_WIDTH*LCD_HEIGHT);
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DAR3 = 0xf0000002;
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SAR3 = (unsigned long)lcd_framebuffer;
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BCR3 = LCD_WIDTH*LCD_HEIGHT*2;
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DCR3 = DMA_AA | DMA_BWC(1)
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| DMA_SINC | DMA_SSIZE(DMA_SIZE_LINE)
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| DMA_DSIZE(DMA_SIZE_WORD) | DMA_START;
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while (!(DSR3 & 1));
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DSR3 = 1;
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}
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}
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}
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}
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@ -376,26 +385,39 @@ void lcd_update(void)
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void lcd_update_rect(int, int, int, int) ICODE_ATTR;
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void lcd_update_rect(int, int, int, int) ICODE_ATTR;
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void lcd_update_rect(int x, int y, int width, int height)
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void lcd_update_rect(int x, int y, int width, int height)
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{
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{
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unsigned long dma_addr;
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if(display_on) {
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if(display_on) {
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int ymax = y + height - 1;
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if(x + width > LCD_WIDTH)
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if(x + width > LCD_WIDTH)
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width = LCD_WIDTH - x;
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width = LCD_WIDTH - x;
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if (width <= 0)
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if(width <= 0) /* nothing to do */
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return; /* nothing left to do, 0 is harmful to lcd_write_data() */
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return;
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if(ymax >= LCD_HEIGHT)
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if(y + height > LCD_HEIGHT)
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ymax = LCD_HEIGHT-1;
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height = LCD_HEIGHT - y;
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/* set update window */
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/* set update window */
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lcd_write_reg(R_VERT_RAM_ADDR_POS,((x+xoffset+width-1) << 8) | (x+xoffset));
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lcd_write_reg(R_VERT_RAM_ADDR_POS,((x+xoffset+width-1) << 8) | (x+xoffset));
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lcd_write_reg(R_RAM_ADDR_SET, ((x+xoffset) << 8) | y);
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lcd_write_reg(R_RAM_ADDR_SET, ((x+xoffset) << 8) | y);
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lcd_begin_write_gram();
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lcd_begin_write_gram();
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DAR3 = 0xf0000002;
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dma_addr = (unsigned long)&lcd_framebuffer[y][x];
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width *= 2;
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/* Copy specified rectangle bitmap to hardware */
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for (; height > 0; height--)
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for (; y <= ymax; y++)
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{
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{
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SAR3 = dma_addr;
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lcd_write_data ((unsigned short *)&lcd_framebuffer[y][x], width);
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BCR3 = width;
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}
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DCR3 = DMA_AA | DMA_BWC(1)
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| DMA_SINC | DMA_SSIZE(DMA_SIZE_LINE)
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| DMA_DSIZE(DMA_SIZE_WORD) | DMA_START;
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dma_addr += LCD_WIDTH*2;
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while (!(DSR3 & 1));
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DSR3 = 1;
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}
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}
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}
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}
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}
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@ -251,6 +251,7 @@
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#define DMA_EEXT (1 << 30) /* Enable peripherial request */
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#define DMA_EEXT (1 << 30) /* Enable peripherial request */
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#define DMA_CS (1 << 29) /* Cycle Steal */
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#define DMA_CS (1 << 29) /* Cycle Steal */
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#define DMA_AA (1 << 28) /* Auto-Align */
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#define DMA_AA (1 << 28) /* Auto-Align */
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#define DMA_BWC(x) (((x)&7) << 25) /* Bandwidth control */
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#define DMA_SINC (1 << 22) /* Source Increment */
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#define DMA_SINC (1 << 22) /* Source Increment */
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#define DMA_SSIZE(x) (((x)&3) << 20) /* Size of source data */
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#define DMA_SSIZE(x) (((x)&3) << 20) /* Size of source data */
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#define DMA_DINC (1 << 19) /* Destination Increment */
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#define DMA_DINC (1 << 19) /* Destination Increment */
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@ -22,102 +22,6 @@
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.section .icode, "ax", @progbits
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.section .icode, "ax", @progbits
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.align 2
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.global lcd_write_data
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.type lcd_write_data, @function
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lcd_write_data:
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move.l (4, %sp), %a0 /* data pointer */
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move.l (8, %sp), %d0 /* length in words */
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add.l %d0, %d0 /* words -> bytes */
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add.l %a0, %d0 /* -> end address */
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lea.l 0xf0000002, %a1 /* LCD data port */
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move.l %a0, %d1
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btst.l #1, %d1 /* already longword aligned? */
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beq.s .word1_end /* yes: skip initial word copy */
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move.w (%a0)+, (%a1) /* transfer initial word */
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.word1_end: /* now longword aligned */
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moveq.l #28, %d1
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add.l %a0, %d1
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and.l #0xFFFFFFF0,%d1 /* %d1 = first line bound + 16 */
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cmp.l %d1, %d0 /* at least one full line to send? */
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blo.s .long2_start /* no: skip to trailing longword handling */
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lea.l (-16, %sp), %sp /* free up some registers */
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movem.l %d2-%d4/%a2, (%sp)
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subq.l #8, %d1
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subq.l #8, %d1 /* %d1 = first line bound */
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cmp.l %a0, %d1 /* any leading longwords? */
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bls.s .long1_end /* no: skip leading long loop */
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.long1_loop:
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move.l (%a0)+, %d2 /* read longword */
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swap %d2 /* send data to LCD in correct order...*/
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move.w %d2, (%a1)
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swap %d2
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move.w %d2, (%a1)
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cmp.l %a0, %d1 /* run %a0 up to first line bound */
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bhi.s .long1_loop
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.long1_end:
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move.l %d0, %a2
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lea.l (-14, %a2), %a2 /* %a2 = end address - 14 (one line/pass) */
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/* burst-optimised line transfers */
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.line_loop:
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movem.l (%a0), %d1-%d4 /* burst-read line */
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lea.l (16, %a0), %a0 /* increment address */
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swap %d1 /* send data to LCD in correct order... */
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move.w %d1, (%a1)
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swap %d1
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move.w %d1, (%a1)
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swap %d2
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move.w %d2, (%a1)
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swap %d2
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move.w %d2, (%a1)
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swap %d3
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move.w %d3, (%a1)
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swap %d3
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move.w %d3, (%a1)
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swap %d4
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move.w %d4, (%a1)
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swap %d4
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move.w %d4, (%a1)
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cmp.l %a0, %a2 /* run %a0 up to last line bound */
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bhi.s .line_loop
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movem.l (%sp), %d2-%d4/%a2
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lea.l (16, %sp), %sp /* restore registers */
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.long2_start:
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subq.l #2, %d0 /* account for handling 2 words per loop */
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cmp.l %a0, %d0 /* any (trailing longwords? */
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bls.s .long2_end /* no: skip trailing longword loop */
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.long2_loop:
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move.l (%a0)+, %d1 /* read longword */
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swap %d1 /* send data to LCD in correct order */
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move.w %d1, (%a1)
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swap %d1
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move.w %d1, (%a1)
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cmp.l %a0, %d0 /* run %a0 up to last long bound */
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bhi.s .long2_loop
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.long2_end:
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blo.s .word2_end /* no final word: skip */
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move.w (%a0)+, (%a1) /* transfer final word */
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.word2_end:
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rts
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.lcd_write_data_end:
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.size lcd_write_data, .lcd_write_data_end - lcd_write_data
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/* lcd_write_yuv420_lines(), based on lcd-as-x5.S
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/* lcd_write_yuv420_lines(), based on lcd-as-x5.S
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*
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*
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* See http://en.wikipedia.org/wiki/YCbCr
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* See http://en.wikipedia.org/wiki/YCbCr
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@ -24,6 +24,28 @@
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#include "timer.h"
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#include "timer.h"
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#include "pcf50606.h"
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#include "pcf50606.h"
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/* Settings for all possible clock frequencies (with properly working timers)
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*
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* xxx_REFRESH_TIMER below
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* system.h, CPUFREQ_xxx_MULT |
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* | |
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* V V
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* Refreshtim. IDECONFIG1/IDECONFIG2
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* CPUCLK/Hz MULT PLLCR 16MB 32MB CSCR0 CSCR1 CSCR3 CS2Pre CS2Post CS2Wait
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* ---------------------------------------------------------------------------------------
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* 11289600 1 0x10c00200 4 1 0x0180 0x0180 0x0180 1 0 0
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* 22579200 2 0x15c4e005 10 4 0x0180 0x0180 0x0180 1 0 0
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* 33868800 3 0x13c46005 15 7 0x0180 0x0180 0x0180 1 0 0
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* 45158400 4 0x15c4e001 21 10 0x0580 0x0180 0x0580 1 0 0
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* 56448000 5 0x12c4e005 26 12 0x0580 0x0980
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* 67737600 6 0x13c46001 32 15 0x0980 0x0d80
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* 79027200 7 0x13c52001 37 18 0x0980 0x1180
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* 90316800 8 0x13c5e001 43 21 0x0d80 0x1580
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* 101606400 9 0x11c48005 48 23 0x0d80 0x1980
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* 112896000 10 0x11c4e005 54 26 0x1180 0x1d80
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* 124185600 11 0x11c56005 59 29 0x1180 0x1180 0x2180 2 1 2
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*/
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#if MEM < 32
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#if MEM < 32
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#define MAX_REFRESH_TIMER 59
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#define MAX_REFRESH_TIMER 59
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#define NORMAL_REFRESH_TIMER 21
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#define NORMAL_REFRESH_TIMER 21
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@ -61,7 +83,7 @@ void set_cpu_frequency(long frequency)
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RECALC_DELAYS(CPUFREQ_MAX);
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RECALC_DELAYS(CPUFREQ_MAX);
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PLLCR = 0x11c56005;
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PLLCR = 0x11c56005;
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CSCR0 = 0x00001180; /* Flash: 4 wait states */
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CSCR0 = 0x00001180; /* Flash: 4 wait states */
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CSCR1 = 0x00000980; /* LCD: 2 wait states */
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CSCR1 = 0x00001580; /* LCD: 5 wait states */
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#if CONFIG_USBOTG == USBOTG_ISP1362
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#if CONFIG_USBOTG == USBOTG_ISP1362
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CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
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CSCR3 = 0x00002180; /* USBOTG: 8 wait states */
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#endif
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#endif
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