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Gigabeat F/X: Let us clear up confusion about just what the core frequency is. Fix frequency display in buffering screen.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25953 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2010-05-11 14:09:26 +00:00
parent aaa07970ee
commit 8261051b37
2 changed files with 8 additions and 6 deletions
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2
firmware/export/config/gigabeatfx.h
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@ -169,7 +169,7 @@
#define FLASH_SIZE 0x400000 #define FLASH_SIZE 0x400000
/* Define this to the CPU frequency */ /* Define this to the CPU frequency */
#define CPU_FREQ 16934400 #define CPU_FREQ 294940800
/* Define this if you have ATA power-off control */ /* Define this if you have ATA power-off control */
#define HAVE_ATA_POWER_OFF #define HAVE_ATA_POWER_OFF

12
firmware/target/arm/s3c2440/system-target.h
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@ -27,14 +27,16 @@
/* NB: These values must match the register settings in s3c2440/crt0.S */ /* NB: These values must match the register settings in s3c2440/crt0.S */
#ifdef GIGABEAT_F #ifdef GIGABEAT_F
#define CPUFREQ_DEFAULT 98784000 /* MPLLCON = 0x000C9042, 16.9344 MHz refclk, therefore:
#define CPUFREQ_NORMAL 98784000 * MPLL = 294940800 = 2*(201 + 8)*16934400 / ((4 + 2) * 2^2) */
#define CPUFREQ_MAX 296352000 #define CPUFREQ_DEFAULT 98313600
#define CPUFREQ_NORMAL 98313600
#define CPUFREQ_MAX 294940800
/* Uses 1:3:6 */ /* Uses 1:3:6 */
#define FCLK CPUFREQ_MAX #define FCLK CPUFREQ_MAX
#define HCLK (FCLK/3) /* = 98,784,000 */ #define HCLK (FCLK/3) /* = 98,313,600 */
#define PCLK (HCLK/2) /* = 49,392,000 */ #define PCLK (HCLK/2) /* = 49,156,800 */
#ifdef BOOTLOADER #ifdef BOOTLOADER
/* All addresses within rockbox are in IRAM in the bootloader so /* All addresses within rockbox are in IRAM in the bootloader so