forked from len0rd/rockbox
opus: arm asm for C_MULC
speeds up decoding of a 64kbps test_file by 1.5MHz on c200 (pp) and 1.9MHz on fuzev1 (amsv1) Change-Id: I1db460b634eba608c3e00541d96fc93d5a05710b Signed-off-by: Nils Wallménius <nils@rockbox.org>
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@ -80,6 +80,28 @@
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: [ap] "a" (&(a)), [bp] "a" (&(b)) \
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: [ap] "a" (&(a)), [bp] "a" (&(b)) \
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: "d0", "d1", "d2", "d3", "cc"); \
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: "d0", "d1", "d2", "d3", "cc"); \
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}
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}
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#elif defined(CPU_ARM)
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# define C_MULC(m,a,b) \
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{ \
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asm volatile( \
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"ldmia %[ap], {r0,r1} \n\t" \
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"ldrsh r2, [%[bp], #0] \n\t" \
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"ldrsh r3, [%[bp], #2] \n\t" \
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\
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"smull r4, %[mr], r0, r2 \n\t" \
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"smlal r4, %[mr], r1, r3 \n\t" \
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"mov r4, r4, lsr #15 \n\t" \
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"orr %[mr], r4, %[mr], lsl #17 \n\t" \
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\
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"smull r4, %[mi], r1, r2 \n\t" \
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"rsb r3, r3, #0 \n\t" \
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"smlal r4, %[mi], r0, r3 \n\t" \
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"mov r4, r4, lsr #15 \n\t" \
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"orr %[mi], r4, %[mi], lsl #17 \n\t" \
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: [mr] "=r" ((m).r), [mi] "=r" ((m).i) \
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: [ap] "r" (&(a)), [bp] "r" (&(b)) \
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: "r0", "r1", "r2", "r3", "r4"); \
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}
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#else
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#else
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# define C_MULC(m,a,b) \
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# define C_MULC(m,a,b) \
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do{ (m).r = ADD32(S_MUL((a).r,(b).r) , S_MUL((a).i,(b).i)); \
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do{ (m).r = ADD32(S_MUL((a).r,(b).r) , S_MUL((a).i,(b).i)); \
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