From 81f76f21d6ec2e49cd4d3e942d72fcab52947185 Mon Sep 17 00:00:00 2001 From: Jens Arnold Date: Sat, 9 Dec 2006 11:36:40 +0000 Subject: [PATCH] Fix some comments, and make code consistent with comments (CSMR2 was set to 1M instead of 64K). git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11698 a1c6a512-1295-4272-9138-f99709370657 --- firmware/target/coldfire/crt0.S | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/firmware/target/coldfire/crt0.S b/firmware/target/coldfire/crt0.S index a0e948486e..7fc389c23d 100644 --- a/firmware/target/coldfire/crt0.S +++ b/firmware/target/coldfire/crt0.S @@ -72,12 +72,11 @@ start: /* Chip select 2 - ATA controller */ move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */ move.l %d0,(0x098,%a0) - move.l #0x000f0001,%d0 /* CSMR2 - 64K, Only data access */ + moveq.l #0x1,%d0 /* CSMR2 - 64K */ move.l %d0,(0x09c,%a0) move.l #0x00000080,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */ - move.l %d0,(0x0a0,%a0) /* NOTE: I'm not sure about the wait states. - We have to be careful with the access times, - since IORDY isn't connected to the HDD. */ + move.l %d0,(0x0a0,%a0) /* wait states are handled by the coldfire + * IDE interface logic. */ #if CONFIG_USBOTG == USBOTG_ISP1362 /* Chip select 3 - USBOTG controller */