forked from len0rd/rockbox
libdemac: ARMv7 assembler optimisation for the filters, tested on Nokia N900. Speedup is 2.1x for -c5000 compared to the ARMv6 asm. Note that actually compiling it on device requires hand-assembling the 'vadd' and 'vsub' instructions due to a bug in binutils 2.18.50, and making the standalone decoder use it requires Makefile and demac_config.h hacks.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27944 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
dd5e3eb542
commit
811877e5b3
2 changed files with 216 additions and 0 deletions
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@ -41,6 +41,8 @@ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
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#ifdef CPU_COLDFIRE
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#ifdef CPU_COLDFIRE
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#include "vector_math16_cf.h"
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#include "vector_math16_cf.h"
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#elif defined(CPU_ARM) && (ARM_ARCH >= 7)
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#include "vector_math16_armv7.h"
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#elif defined(CPU_ARM) && (ARM_ARCH >= 6)
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#elif defined(CPU_ARM) && (ARM_ARCH >= 6)
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#include "vector_math16_armv6.h"
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#include "vector_math16_armv6.h"
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#elif defined(CPU_ARM) && (ARM_ARCH >= 5)
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#elif defined(CPU_ARM) && (ARM_ARCH >= 5)
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214
apps/codecs/demac/libdemac/vector_math16_armv7.h
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214
apps/codecs/demac/libdemac/vector_math16_armv7.h
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@ -0,0 +1,214 @@
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/*
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libdemac - A Monkey's Audio decoder
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$Id$
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Copyright (C) Dave Chapman 2007
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ARMv7 neon vector math copyright (C) 2010 Jens Arnold
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
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*/
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#define FUSED_VECTOR_MATH
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#if ORDER > 32
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#define REPEAT_BLOCK(x) x x x
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#elif ORDER > 16
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#define REPEAT_BLOCK(x) x
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#else
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#define REPEAT_BLOCK(x)
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#endif
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/* Calculate scalarproduct, then add a 2nd vector (fused for performance) */
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static inline int32_t vector_sp_add(int16_t* v1, int16_t* f2, int16_t* s2)
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{
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int res;
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#if ORDER > 64
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int cnt = ORDER>>6;
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#endif
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asm volatile (
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#if ORDER > 64
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"vmov.i16 q0, #0 \n"
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"1: \n"
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"subs %[cnt], %[cnt], #1 \n"
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#endif
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"vld1.16 {d6-d9}, [%[f2]]! \n"
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"vld1.16 {d2-d5}, [%[v1]] \n"
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"vld1.16 {d10-d13}, [%[s2]]! \n"
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#if ORDER > 64
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"vmlal.s16 q0, d2, d6 \n"
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#else
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"vmull.s16 q0, d2, d6 \n"
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#endif
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"vmlal.s16 q0, d3, d7 \n"
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"vmlal.s16 q0, d4, d8 \n"
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"vmlal.s16 q0, d5, d9 \n"
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"vadd.i16 q1, q1, q5 \n"
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"vadd.i16 q2, q2, q6 \n"
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"vst1.16 {d2-d5}, [%[v1]]! \n"
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REPEAT_BLOCK(
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"vld1.16 {d6-d9}, [%[f2]]! \n"
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"vld1.16 {d2-d5}, [%[v1]] \n"
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"vld1.16 {d10-d13}, [%[s2]]! \n"
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"vmlal.s16 q0, d2, d6 \n"
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"vmlal.s16 q0, d3, d7 \n"
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"vmlal.s16 q0, d4, d8 \n"
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"vmlal.s16 q0, d5, d9 \n"
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"vadd.i16 q1, q1, q5 \n"
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"vadd.i16 q2, q2, q6 \n"
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"vst1.16 {d2-d5}, [%[v1]]! \n"
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)
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#if ORDER > 64
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"bne 1b \n"
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#endif
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"vpadd.i32 d0, d0, d1 \n"
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"vpaddl.s32 d0, d0 \n"
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"vmov.32 %[res], d0[0] \n"
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: /* outputs */
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#if ORDER > 64
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[cnt]"+r"(cnt),
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#endif
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[v1] "+r"(v1),
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[f2] "+r"(f2),
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[s2] "+r"(s2),
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[res]"=r"(res)
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: /* inputs */
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: /* clobbers */
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"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
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"d8", "d9", "d10", "d11", "d12", "d13", "memory"
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);
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return res;
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}
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/* Calculate scalarproduct, then subtract a 2nd vector (fused for performance) */
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static inline int32_t vector_sp_sub(int16_t* v1, int16_t* f2, int16_t* s2)
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{
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int res;
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#if ORDER > 64
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int cnt = ORDER>>6;
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#endif
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asm volatile (
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#if ORDER > 64
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"vmov.i16 q0, #0 \n"
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"1: \n"
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"subs %[cnt], %[cnt], #1 \n"
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#endif
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"vld1.16 {d6-d9}, [%[f2]]! \n"
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"vld1.16 {d2-d5}, [%[v1]] \n"
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"vld1.16 {d10-d13}, [%[s2]]! \n"
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#if ORDER > 64
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"vmlal.s16 q0, d2, d6 \n"
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#else
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"vmull.s16 q0, d2, d6 \n"
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#endif
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"vmlal.s16 q0, d3, d7 \n"
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"vmlal.s16 q0, d4, d8 \n"
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"vmlal.s16 q0, d5, d9 \n"
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"vsub.i16 q1, q1, q5 \n"
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"vsub.i16 q2, q2, q6 \n"
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"vst1.16 {d2-d5}, [%[v1]]! \n"
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REPEAT_BLOCK(
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"vld1.16 {d6-d9}, [%[f2]]! \n"
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"vld1.16 {d2-d5}, [%[v1]] \n"
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"vld1.16 {d10-d13}, [%[s2]]! \n"
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"vmlal.s16 q0, d2, d6 \n"
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"vmlal.s16 q0, d3, d7 \n"
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"vmlal.s16 q0, d4, d8 \n"
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"vmlal.s16 q0, d5, d9 \n"
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"vsub.i16 q1, q1, q5 \n"
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"vsub.i16 q2, q2, q6 \n"
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"vst1.16 {d2-d5}, [%[v1]]! \n"
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)
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#if ORDER > 64
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"bne 1b \n"
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#endif
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"vpadd.i32 d0, d0, d1 \n"
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"vpaddl.s32 d0, d0 \n"
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"vmov.32 %[res], d0[0] \n"
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: /* outputs */
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#if ORDER > 64
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[cnt]"+r"(cnt),
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#endif
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[v1] "+r"(v1),
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[f2] "+r"(f2),
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[s2] "+r"(s2),
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[res]"=r"(res)
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: /* inputs */
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: /* clobbers */
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"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
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"d8", "d9", "d10", "d11", "d12", "d13", "memory"
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);
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return res;
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}
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static inline int32_t scalarproduct(int16_t* v1, int16_t* v2)
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{
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int res;
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#if ORDER > 64
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int cnt = ORDER>>6;
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#endif
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asm volatile (
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#if ORDER > 64
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"vmov.i16 q0, #0 \n"
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"1: \n"
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"subs %[cnt], %[cnt], #1 \n"
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#endif
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"vld1.16 {d2-d5}, [%[v1]]! \n"
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"vld1.16 {d6-d9}, [%[v2]]! \n"
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#if ORDER > 64
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"vmlal.s16 q0, d2, d6 \n"
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#else
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"vmull.s16 q0, d2, d6 \n"
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#endif
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"vmlal.s16 q0, d3, d7 \n"
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"vmlal.s16 q0, d4, d8 \n"
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"vmlal.s16 q0, d5, d9 \n"
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REPEAT_BLOCK(
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"vld1.16 {d2-d5}, [%[v1]]! \n"
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"vld1.16 {d6-d9}, [%[v2]]! \n"
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"vmlal.s16 q0, d2, d6 \n"
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"vmlal.s16 q0, d3, d7 \n"
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"vmlal.s16 q0, d4, d8 \n"
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"vmlal.s16 q0, d5, d9 \n"
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)
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#if ORDER > 64
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"bne 1b \n"
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#endif
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"vpadd.i32 d0, d0, d1 \n"
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"vpaddl.s32 d0, d0 \n"
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"vmov.32 %[res], d0[0] \n"
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: /* outputs */
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#if ORDER > 64
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[cnt]"+r"(cnt),
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#endif
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[v1] "+r"(v1),
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[v2] "+r"(v2),
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[res]"=r"(res)
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: /* inputs */
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: /* clobbers */
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"d0", "d1", "d2", "d3", "d4",
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"d5", "d6", "d7", "d8", "d9"
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);
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return res;
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}
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