forked from len0rd/rockbox
imx233: rewrite power using new registers
Change-Id: Ifbee91161220419f4d1750672b5c4ae3537cefca
This commit is contained in:
Amaury Pouly
parent
b73fda3a05
commit
7c5b65b9d2
7 changed files with 138 additions and 250 deletions
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@ -150,7 +150,7 @@ void main(uint32_t arg, uint32_t addr)
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printf("Boot version: %s", RBVERSION);
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printf("arg=%x addr=%x", arg, addr);
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printf("power up source: %x", __XTRACT(HW_POWER_STS, PWRUP_SOURCE));
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printf("power up source: %x", BF_RD(POWER_STS, PWRUP_SOURCE));
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if(arg == 0xfee1dead)
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{
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@ -176,7 +176,7 @@ int button_read_device(void)
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res |= BUTTON_VOL_DOWN;
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if(!(mask & 0x100))
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res |= BUTTON_VOL_UP;
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if(__XTRACT(HW_POWER_STS, PSWITCH) != 0 && power_ignore_counter == 0)
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if(BF_RD(POWER_STS, PSWITCH) != 0 && power_ignore_counter == 0)
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res |= BUTTON_POWER;
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return res | touchpad_btns;
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}
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@ -38,76 +38,76 @@ struct current_step_bit_t
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/* in decreasing order */
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static struct current_step_bit_t g_charger_current_bits[] =
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{
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{ 400, HW_POWER_CHARGE__BATTCHRG_I__400mA },
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{ 200, HW_POWER_CHARGE__BATTCHRG_I__200mA },
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{ 100, HW_POWER_CHARGE__BATTCHRG_I__100mA },
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{ 50, HW_POWER_CHARGE__BATTCHRG_I__50mA },
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{ 20, HW_POWER_CHARGE__BATTCHRG_I__20mA },
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{ 10, HW_POWER_CHARGE__BATTCHRG_I__10mA }
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{ 400, BV_POWER_CHARGE_BATTCHRG_I__400mA },
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{ 200, BV_POWER_CHARGE_BATTCHRG_I__200mA },
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{ 100, BV_POWER_CHARGE_BATTCHRG_I__100mA },
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{ 50, BV_POWER_CHARGE_BATTCHRG_I__50mA },
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{ 20, BV_POWER_CHARGE_BATTCHRG_I__20mA },
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{ 10, BV_POWER_CHARGE_BATTCHRG_I__10mA }
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};
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/* in decreasing order */
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static struct current_step_bit_t g_charger_stop_current_bits[] =
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{
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{ 100, HW_POWER_CHARGE__STOP_ILIMIT__100mA },
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{ 50, HW_POWER_CHARGE__STOP_ILIMIT__50mA },
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{ 20, HW_POWER_CHARGE__STOP_ILIMIT__20mA },
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{ 10, HW_POWER_CHARGE__STOP_ILIMIT__10mA }
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{ 100, BV_POWER_CHARGE_STOP_ILIMIT__100mA },
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{ 50, BV_POWER_CHARGE_STOP_ILIMIT__50mA },
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{ 20, BV_POWER_CHARGE_STOP_ILIMIT__20mA },
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{ 10, BV_POWER_CHARGE_STOP_ILIMIT__10mA }
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};
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/* in decreasing order */
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static struct current_step_bit_t g_4p2_charge_limit_bits[] =
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{
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{ 400, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__400mA },
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{ 200, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__200mA },
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{ 100, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__100mA },
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{ 50, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__50mA },
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{ 20, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__20mA },
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{ 10, HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__10mA }
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{ 400, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__400mA },
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{ 200, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__200mA },
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{ 100, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__100mA },
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{ 50, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__50mA },
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{ 20, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__20mA },
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{ 10, BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__10mA }
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};
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void INT_VDD5V(void)
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{
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if(HW_POWER_CTRL & HW_POWER_CTRL__VBUSVALID_IRQ)
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if(BF_RD(POWER_CTRL, VBUSVALID_IRQ))
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{
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if(HW_POWER_STS & HW_POWER_STS__VBUSVALID)
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if(BF_RD(POWER_STS, VBUSVALID))
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usb_insert_int();
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else
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usb_remove_int();
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/* reverse polarity */
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__REG_TOG(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID;
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BF_TOG(POWER_CTRL, POLARITY_VBUSVALID);
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/* enable int */
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__REG_CLR(HW_POWER_CTRL) = HW_POWER_CTRL__VBUSVALID_IRQ;
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BF_CLR(POWER_CTRL, VBUSVALID_IRQ);
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}
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}
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void imx233_power_init(void)
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{
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/* setup vbusvalid parameters: set threshold to 4v and power up comparators */
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__REG_CLR(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__VBUSVALID_TRSH_BM;
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__REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__VBUSVALID_TRSH_4V |
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HW_POWER_5VCTRL__PWRUP_VBUS_CMPS;
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BF_CLR(POWER_5VCTRL, VBUSVALID_TRSH);
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BF_SETV(POWER_5VCTRL, VBUSVALID_TRSH, 1);
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BF_SET(POWER_5VCTRL, PWRUP_VBUS_CMPS);
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/* enable vbusvalid detection method for the dcdc (improves efficiency) */
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__REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__VBUSVALID_5VDETECT;
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/* clear vbusvalid irq and set correct polarity */
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__REG_CLR(HW_POWER_CTRL) = HW_POWER_CTRL__VBUSVALID_IRQ;
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if(HW_POWER_STS & HW_POWER_STS__VBUSVALID)
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__REG_CLR(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID;
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BF_SET(POWER_5VCTRL, VBUSVALID_5VDETECT);
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BF_CLR(POWER_CTRL, VBUSVALID_IRQ);
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if(BF_RD(POWER_STS, VBUSVALID))
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BF_CLR(POWER_CTRL, POLARITY_VBUSVALID);
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else
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__REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID;
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__REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__ENIRQ_VBUS_VALID;
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BF_SET(POWER_CTRL, POLARITY_VBUSVALID);
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BF_SET(POWER_CTRL, ENIRQ_VBUS_VALID);
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imx233_icoll_enable_interrupt(INT_SRC_VDD5V, true);
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/* setup linear regulator offsets to 25 mV below to prevent contention between
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* linear regulators and DCDC */
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__FIELD_SET(HW_POWER_VDDDCTRL, LINREG_OFFSET, 2);
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__FIELD_SET(HW_POWER_VDDACTRL, LINREG_OFFSET, 2);
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__FIELD_SET(HW_POWER_VDDIOCTRL, LINREG_OFFSET, 2);
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BF_WR(POWER_VDDDCTRL, LINREG_OFFSET, 2);
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BF_WR(POWER_VDDACTRL, LINREG_OFFSET, 2);
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BF_WR(POWER_VDDIOCTRL, LINREG_OFFSET, 2);
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/* enable DCDC (more efficient) */
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__REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__ENABLE_DCDC;
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BF_SET(POWER_5VCTRL, ENABLE_DCDC);
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/* enable a few bits controlling the DC-DC as recommended by Freescale */
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__REG_SET(HW_POWER_LOOPCTRL) = HW_POWER_LOOPCTRL__TOGGLE_DIF |
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HW_POWER_LOOPCTRL__EN_CM_HYST;
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__FIELD_SET(HW_POWER_LOOPCTRL, EN_RCSCALE, HW_POWER_LOOPCTRL__EN_RCSCALE__2X);
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BF_SET(POWER_LOOPCTRL, TOGGLE_DIF);
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BF_SET(POWER_LOOPCTRL, EN_CM_HYST);
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BF_CLR(POWER_LOOPCTRL, EN_RCSCALE);
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BF_SETV(POWER_LOOPCTRL, EN_RCSCALE, 1);
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}
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void power_init(void)
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@ -126,7 +126,7 @@ void power_off(void)
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imx233_set_gpio_output(0, 9, true);
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#endif
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/* power down */
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HW_POWER_RESET = HW_POWER_RESET__UNLOCK | HW_POWER_RESET__PWD;
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HW_POWER_RESET = BM_OR2(POWER_RESET, UNLOCK, PWD);
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while(1);
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}
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@ -138,24 +138,24 @@ unsigned int power_input_status(void)
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bool charging_state(void)
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{
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return HW_POWER_STS & HW_POWER_STS__CHRGSTS;
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return BF_RD(POWER_STS, CHRGSTS);
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}
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void imx233_power_set_charge_current(unsigned current)
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{
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__REG_CLR(HW_POWER_CHARGE) = HW_POWER_CHARGE__BATTCHRG_I_BM;
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BF_CLR(POWER_CHARGE, BATTCHRG_I);
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/* find closest current LOWER THAN OR EQUAL TO the expected current */
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for(unsigned i = 0; i < ARRAYLEN(g_charger_current_bits); i++)
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if(current >= g_charger_current_bits[i].current)
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{
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current -= g_charger_current_bits[i].current;
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__REG_SET(HW_POWER_CHARGE) = g_charger_current_bits[i].bit;
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BF_SETV(POWER_CHARGE, BATTCHRG_I, g_charger_current_bits[i].bit);
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}
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}
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void imx233_power_set_stop_current(unsigned current)
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{
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__REG_CLR(HW_POWER_CHARGE) = HW_POWER_CHARGE__STOP_ILIMIT_BM;
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BF_CLR(POWER_CHARGE, STOP_ILIMIT);
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/* find closest current GREATHER THAN OR EQUAL TO the expected current */
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unsigned sum = 0;
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for(unsigned i = 0; i < ARRAYLEN(g_charger_stop_current_bits); i++)
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@ -166,7 +166,7 @@ void imx233_power_set_stop_current(unsigned current)
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if(current > sum)
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{
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current -= g_charger_stop_current_bits[i].current;
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__REG_SET(HW_POWER_CHARGE) = g_charger_stop_current_bits[i].bit;
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BF_SETV(POWER_CHARGE, STOP_ILIMIT, g_charger_stop_current_bits[i].bit);
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}
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}
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}
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@ -191,17 +191,17 @@ static struct
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.min = HW_POWER_##name##CTRL__TRG_MIN, \
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.step = HW_POWER_##name##CTRL__TRG_STEP, \
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.reg = &HW_POWER_##name##CTRL, \
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.trg_bm = HW_POWER_##name##CTRL__TRG_BM, \
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.trg_bp = HW_POWER_##name##CTRL__TRG_BP, \
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.trg_bm = BM_POWER_##name##CTRL_TRG, \
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.trg_bp = BP_POWER_##name##CTRL_TRG, \
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.flags = mask
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#define ADD_REGULATOR_BO(name) \
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.bo_bm = HW_POWER_##name##CTRL__BO_OFFSET_BM, \
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.bo_bp = HW_POWER_##name##CTRL__BO_OFFSET_BP
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.bo_bm = BM_POWER_##name##CTRL_BO_OFFSET, \
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.bo_bp = BP_POWER_##name##CTRL_BO_OFFSET
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#define ADD_REGULATOR_LINREG(name) \
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.linreg_bm = HW_POWER_##name##CTRL__ENABLE_LINREG
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.linreg_bm = BM_POWER_##name##CTRL_ENABLE_LINREG
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#define ADD_REGULATOR_LINREG_OFFSET(name) \
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.linreg_offset_bm = HW_POWER_##name##CTRL__LINREG_OFFSET_BM, \
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.linreg_offset_bp = HW_POWER_##name##CTRL__LINREG_OFFSET_BP
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.linreg_offset_bm = BM_POWER_##name##CTRL_LINREG_OFFSET, \
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.linreg_offset_bp = BP_POWER_##name##CTRL_LINREG_OFFSET
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[REGULATOR_VDDD] =
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{
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ADD_REGULATOR(VDDD, HAS_BO|HAS_LINREG|HAS_LINREG_OFFSET),
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@ -257,7 +257,7 @@ void imx233_power_set_regulator(enum imx233_regulator_t reg, unsigned value_mv,
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unsigned raw_val = (value_mv - regulator_info[reg].min) / regulator_info[reg].step;
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unsigned raw_bo_offset = (value_mv - brownout_mv) / regulator_info[reg].step;
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// clear dc-dc ok flag
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__REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__DC_OK_IRQ;
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BF_SET(POWER_CTRL, DC_OK_IRQ);
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// update
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uint32_t reg_val = (*regulator_info[reg].reg) & ~regulator_info[reg].trg_bm;
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reg_val |= raw_val << regulator_info[reg].trg_bp;
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@ -271,12 +271,12 @@ void imx233_power_set_regulator(enum imx233_regulator_t reg, unsigned value_mv,
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* If DC-DC is used, we can use the DCDC_OK irq
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* Otherwise it is unreliable (doesn't work when lowering voltage on linregs)
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* It usually takes between 0.5ms and 2.5ms */
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if(!(HW_POWER_5VCTRL & HW_POWER_5VCTRL__ENABLE_DCDC))
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if(!BF_RD(POWER_5VCTRL, ENABLE_DCDC))
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panicf("regulator %d: wait for voltage stabilize in linreg mode !", reg);
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unsigned timeout = current_tick + (HZ * 20) / 1000;
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while(!(HW_POWER_CTRL & HW_POWER_CTRL__DC_OK_IRQ) || !TIME_AFTER(current_tick, timeout))
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while(!BF_RD(POWER_CTRL, DC_OK_IRQ) || !TIME_AFTER(current_tick, timeout))
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yield();
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if(!(HW_POWER_CTRL & HW_POWER_CTRL__DC_OK_IRQ))
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if(!BF_RD(POWER_CTRL, DC_OK_IRQ))
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panicf("regulator %d: failed to stabilize", reg);
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}
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@ -311,55 +311,57 @@ void imx233_power_set_regulator_linreg(enum imx233_regulator_t reg,
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struct imx233_power_info_t imx233_power_get_info(unsigned flags)
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{
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static int dcdc_freqsel[8] = {
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[HW_POWER_MISC__FREQSEL__RES] = 0,
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[HW_POWER_MISC__FREQSEL__20MHz] = 20000,
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[HW_POWER_MISC__FREQSEL__24MHz] = 24000,
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[HW_POWER_MISC__FREQSEL__19p2MHz] = 19200,
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[HW_POWER_MISC__FREQSEL__14p4MHz] = 14200,
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[HW_POWER_MISC__FREQSEL__18MHz] = 18000,
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[HW_POWER_MISC__FREQSEL__21p6MHz] = 21600,
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[HW_POWER_MISC__FREQSEL__17p28MHz] = 17280,
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[BV_POWER_MISC_FREQSEL__RES] = 0,
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[BV_POWER_MISC_FREQSEL__20MHz] = 20000,
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[BV_POWER_MISC_FREQSEL__24MHz] = 24000,
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[BV_POWER_MISC_FREQSEL__19p2MHz] = 19200,
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[BV_POWER_MISC_FREQSEL__14p4MHz] = 14200,
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[BV_POWER_MISC_FREQSEL__18MHz] = 18000,
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[BV_POWER_MISC_FREQSEL__21p6MHz] = 21600,
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[BV_POWER_MISC_FREQSEL__17p28MHz] = 17280,
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};
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struct imx233_power_info_t s;
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memset(&s, 0, sizeof(s));
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if(flags & POWER_INFO_DCDC)
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{
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s.dcdc_sel_pllclk = HW_POWER_MISC & HW_POWER_MISC__SEL_PLLCLK;
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s.dcdc_freqsel = dcdc_freqsel[__XTRACT(HW_POWER_MISC, FREQSEL)];
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s.dcdc_sel_pllclk = BF_RD(POWER_MISC, SEL_PLLCLK);
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s.dcdc_freqsel = dcdc_freqsel[BF_RD(POWER_MISC, FREQSEL)];
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}
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if(flags & POWER_INFO_CHARGE)
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{
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uint32_t current = BF_RD(POWER_CHARGE, BATTCHRG_I);
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uint32_t stop_current = BF_RD(POWER_CHARGE, STOP_ILIMIT);
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for(unsigned i = 0; i < ARRAYLEN(g_charger_current_bits); i++)
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if(HW_POWER_CHARGE & g_charger_current_bits[i].bit)
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if(current & g_charger_current_bits[i].bit)
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s.charge_current += g_charger_current_bits[i].current;
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for(unsigned i = 0; i < ARRAYLEN(g_charger_stop_current_bits); i++)
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if(HW_POWER_CHARGE & g_charger_stop_current_bits[i].bit)
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if(stop_current & g_charger_stop_current_bits[i].bit)
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s.stop_current += g_charger_stop_current_bits[i].current;
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s.charging = HW_POWER_STS & HW_POWER_STS__CHRGSTS;
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s.batt_adj = HW_POWER_BATTMONITOR & HW_POWER_BATTMONITOR__ENBATADJ;
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s.charging = BF_RD(POWER_STS, CHRGSTS);
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s.batt_adj = BF_RD(POWER_BATTMONITOR, EN_BATADJ);
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}
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if(flags & POWER_INFO_4P2)
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{
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s._4p2_enable = HW_POWER_DCDC4P2 & HW_POWER_DCDC4P2__ENABLE_4P2;
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s._4p2_dcdc = HW_POWER_DCDC4P2 & HW_POWER_DCDC4P2__ENABLE_DCDC;
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s._4p2_cmptrip = __XTRACT(HW_POWER_DCDC4P2, CMPTRIP);
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s._4p2_dropout = __XTRACT(HW_POWER_DCDC4P2, DROPOUT_CTRL);
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s._4p2_enable = BF_RD(POWER_DCDC4P2, ENABLE_4P2);
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s._4p2_dcdc = BF_RD(POWER_DCDC4P2, ENABLE_DCDC);
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s._4p2_cmptrip = BF_RD(POWER_DCDC4P2, CMPTRIP);
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s._4p2_dropout = BF_RD(POWER_DCDC4P2, DROPOUT_CTRL);
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}
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if(flags & POWER_INFO_5V)
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{
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s._5v_pwd_charge_4p2 = HW_POWER_5VCTRL & HW_POWER_5VCTRL__PWD_CHARGE_4P2;
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s._5v_dcdc_xfer = HW_POWER_5VCTRL & HW_POWER_5VCTRL__DCDC_XFER;
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s._5v_enable_dcdc = HW_POWER_5VCTRL & HW_POWER_5VCTRL__ENABLE_DCDC;
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s._5v_pwd_charge_4p2 = BF_RD(POWER_5VCTRL, PWD_CHARGE_4P2);
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s._5v_enable_dcdc = BF_RD(POWER_5VCTRL, ENABLE_DCDC);
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uint32_t charge_4p2_ilimit = BF_RD(POWER_5VCTRL, CHARGE_4P2_ILIMIT);
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for(unsigned i = 0; i < ARRAYLEN(g_4p2_charge_limit_bits); i++)
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if(HW_POWER_5VCTRL & g_4p2_charge_limit_bits[i].bit)
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if(charge_4p2_ilimit & g_4p2_charge_limit_bits[i].bit)
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s._5v_charge_4p2_limit += g_4p2_charge_limit_bits[i].current;
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s._5v_vbusvalid_detect = HW_POWER_5VCTRL & HW_POWER_5VCTRL__VBUSVALID_5VDETECT;
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s._5v_vbus_cmps = HW_POWER_5VCTRL & HW_POWER_5VCTRL__PWRUP_VBUS_CMPS;
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s._5v_vbusvalid_detect = BF_RD(POWER_5VCTRL, VBUSVALID_5VDETECT);
|
||||
s._5v_vbus_cmps = BF_RD(POWER_5VCTRL, PWRUP_VBUS_CMPS);
|
||||
s._5v_vbusvalid_thr =
|
||||
__XTRACT(HW_POWER_5VCTRL, VBUSVALID_TRSH) == 0 ?
|
||||
BF_RD(POWER_5VCTRL, VBUSVALID_TRSH) == 0 ?
|
||||
2900
|
||||
: 3900 + __XTRACT(HW_POWER_5VCTRL, VBUSVALID_TRSH) * 100;
|
||||
: 3900 + BF_RD(POWER_5VCTRL, VBUSVALID_TRSH) * 100;
|
||||
}
|
||||
return s;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -25,157 +25,47 @@
|
|||
#include "system-target.h"
|
||||
#include "cpu.h"
|
||||
|
||||
#define HW_POWER_BASE 0x80044000
|
||||
#include "regs/regs-power.h"
|
||||
|
||||
#define HW_POWER_CTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x0))
|
||||
#define HW_POWER_CTRL__ENIRQ_VBUS_VALID (1 << 3)
|
||||
#define HW_POWER_CTRL__VBUSVALID_IRQ (1 << 4)
|
||||
#define HW_POWER_CTRL__POLARITY_VBUSVALID (1 << 5)
|
||||
#define HW_POWER_CTRL__ENIRQ_DC_OK (1 << 14)
|
||||
#define HW_POWER_CTRL__DC_OK_IRQ (1 << 15)
|
||||
#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__10mA (1 << 0)
|
||||
#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__20mA (1 << 1)
|
||||
#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__50mA (1 << 2)
|
||||
#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__100mA (1 << 3)
|
||||
#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__200mA (1 << 4)
|
||||
#define BV_POWER_5VCTRL_CHARGE_4P2_ILIMIT__400mA (1 << 5)
|
||||
|
||||
#define HW_POWER_5VCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x10))
|
||||
#define HW_POWER_5VCTRL__ENABLE_DCDC (1 << 0)
|
||||
#define HW_POWER_5VCTRL__PWRUP_VBUS_CMPS (1 << 1)
|
||||
#define HW_POWER_5VCTRL__VBUSVALID_5VDETECT (1 << 4)
|
||||
#define HW_POWER_5VCTRL__DCDC_XFER (1 << 5)
|
||||
#define HW_POWER_5VCTRL__VBUSVALID_TRSH_BP 8
|
||||
#define HW_POWER_5VCTRL__VBUSVALID_TRSH_BM (0x7 << 8)
|
||||
#define HW_POWER_5VCTRL__VBUSVALID_TRSH_2p9 (0 << 8)
|
||||
#define HW_POWER_5VCTRL__VBUSVALID_TRSH_4V (1 << 8)
|
||||
#define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT_BP 12
|
||||
#define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT_BM (0x3f << 12)
|
||||
#define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__10mA (1 << 12)
|
||||
#define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__20mA (1 << 13)
|
||||
#define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__50mA (1 << 14)
|
||||
#define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__100mA (1 << 15)
|
||||
#define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__200mA (1 << 16)
|
||||
#define HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT__400mA (1 << 17)
|
||||
#define HW_POWER_5VCTRL__PWD_CHARGE_4P2 (1 << 20)
|
||||
#define BV_POWER_CHARGE_BATTCHRG_I__10mA (1 << 0)
|
||||
#define BV_POWER_CHARGE_BATTCHRG_I__20mA (1 << 1)
|
||||
#define BV_POWER_CHARGE_BATTCHRG_I__50mA (1 << 2)
|
||||
#define BV_POWER_CHARGE_BATTCHRG_I__100mA (1 << 3)
|
||||
#define BV_POWER_CHARGE_BATTCHRG_I__200mA (1 << 4)
|
||||
#define BV_POWER_CHARGE_BATTCHRG_I__400mA (1 << 5)
|
||||
|
||||
#define HW_POWER_MINPWR (*(volatile uint32_t *)(HW_POWER_BASE + 0x20))
|
||||
#define HW_POWER_MINPWR__HALF_FETS (1 << 5)
|
||||
#define HW_POWER_MINPWR__DOUBLE_FETS (1 << 6)
|
||||
#define BV_POWER_CHARGE_STOP_ILIMIT__10mA (1 << 0)
|
||||
#define BV_POWER_CHARGE_STOP_ILIMIT__20mA (1 << 1)
|
||||
#define BV_POWER_CHARGE_STOP_ILIMIT__50mA (1 << 2)
|
||||
#define BV_POWER_CHARGE_STOP_ILIMIT__100mA (1 << 3)
|
||||
|
||||
#define HW_POWER_CHARGE (*(volatile uint32_t *)(HW_POWER_BASE + 0x30))
|
||||
#define HW_POWER_CHARGE__BATTCHRG_I_BP 0
|
||||
#define HW_POWER_CHARGE__BATTCHRG_I_BM 0x3f
|
||||
#define HW_POWER_CHARGE__BATTCHRG_I__10mA (1 << 0)
|
||||
#define HW_POWER_CHARGE__BATTCHRG_I__20mA (1 << 1)
|
||||
#define HW_POWER_CHARGE__BATTCHRG_I__50mA (1 << 2)
|
||||
#define HW_POWER_CHARGE__BATTCHRG_I__100mA (1 << 3)
|
||||
#define HW_POWER_CHARGE__BATTCHRG_I__200mA (1 << 4)
|
||||
#define HW_POWER_CHARGE__BATTCHRG_I__400mA (1 << 5)
|
||||
#define HW_POWER_CHARGE__STOP_ILIMIT_BP 8
|
||||
#define HW_POWER_CHARGE__STOP_ILIMIT_BM 0xf00
|
||||
#define HW_POWER_CHARGE__STOP_ILIMIT__10mA (1 << 8)
|
||||
#define HW_POWER_CHARGE__STOP_ILIMIT__20mA (1 << 9)
|
||||
#define HW_POWER_CHARGE__STOP_ILIMIT__50mA (1 << 10)
|
||||
#define HW_POWER_CHARGE__STOP_ILIMIT__100mA (1 << 11)
|
||||
#define HW_POWER_CHARGE__PWD_BATTCHRG (1 << 16)
|
||||
#define HW_POWER_CHARGE__CHRG_STS_OFF (1 << 19)
|
||||
#define HW_POWER_CHARGE__ENABLE_LOAD (1 << 22)
|
||||
|
||||
#define HW_POWER_VDDDCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x40))
|
||||
#define HW_POWER_VDDDCTRL__TRG_BP 0
|
||||
#define HW_POWER_VDDDCTRL__TRG_BM 0x1f
|
||||
#define HW_POWER_VDDDCTRL__BO_OFFSET_BP 8
|
||||
#define HW_POWER_VDDDCTRL__BO_OFFSET_BM (0x7 << 8)
|
||||
#define HW_POWER_VDDDCTRL__TRG_STEP 25 /* mV */
|
||||
#define HW_POWER_VDDDCTRL__TRG_MIN 800 /* mV */
|
||||
#define HW_POWER_VDDDCTRL__LINREG_OFFSET_BP 16
|
||||
#define HW_POWER_VDDDCTRL__LINREG_OFFSET_BM (0x3 << 16)
|
||||
#define HW_POWER_VDDDCTRL__ENABLE_LINREG (1 << 21)
|
||||
|
||||
#define HW_POWER_VDDACTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x50))
|
||||
#define HW_POWER_VDDACTRL__TRG_BP 0
|
||||
#define HW_POWER_VDDACTRL__TRG_BM 0x1f
|
||||
#define HW_POWER_VDDACTRL__BO_OFFSET_BP 8
|
||||
#define HW_POWER_VDDACTRL__BO_OFFSET_BM (0x7 << 8)
|
||||
#define HW_POWER_VDDACTRL__TRG_STEP 25 /* mV */
|
||||
#define HW_POWER_VDDACTRL__TRG_MIN 1500 /* mV */
|
||||
#define HW_POWER_VDDACTRL__LINREG_OFFSET_BP 12
|
||||
#define HW_POWER_VDDACTRL__LINREG_OFFSET_BM (0x3 << 12)
|
||||
#define HW_POWER_VDDACTRL__ENABLE_LINREG (1 << 17)
|
||||
|
||||
#define HW_POWER_VDDIOCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x60))
|
||||
#define HW_POWER_VDDIOCTRL__TRG_BP 0
|
||||
#define HW_POWER_VDDIOCTRL__TRG_BM 0x1f
|
||||
#define HW_POWER_VDDIOCTRL__BO_OFFSET_BP 8
|
||||
#define HW_POWER_VDDIOCTRL__BO_OFFSET_BM (0x7 << 8)
|
||||
#define HW_POWER_VDDIOCTRL__TRG_STEP 25 /* mV */
|
||||
#define HW_POWER_VDDIOCTRL__TRG_MIN 2800 /* mV */
|
||||
#define HW_POWER_VDDIOCTRL__LINREG_OFFSET_BP 12
|
||||
#define HW_POWER_VDDIOCTRL__LINREG_OFFSET_BM (0x3 << 12)
|
||||
|
||||
#define HW_POWER_VDDMEMCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0x70))
|
||||
#define HW_POWER_VDDMEMCTRL__TRG_BP 0
|
||||
#define HW_POWER_VDDMEMCTRL__TRG_BM 0x1f
|
||||
#define HW_POWER_VDDMEMCTRL__TRG_STEP 50 /* mV */
|
||||
#define HW_POWER_VDDMEMCTRL__TRG_MIN 1700 /* mV */
|
||||
#define HW_POWER_VDDMEMCTRL__ENABLE_LINREG (1 << 8)
|
||||
|
||||
#define HW_POWER_DCDC4P2 (*(volatile uint32_t *)(HW_POWER_BASE + 0x80))
|
||||
#define HW_POWER_DCDC4P2__CMPTRIP_BP 0
|
||||
#define HW_POWER_DCDC4P2__CMPTRIP_BM 0x1f
|
||||
#define HW_POWER_DCDC4P2__CMPTRIP__0p85 0
|
||||
#define HW_POWER_DCDC4P2__ENABLE_DCDC (1 << 22)
|
||||
#define HW_POWER_DCDC4P2__ENABLE_4P2 (1 << 23)
|
||||
#define HW_POWER_DCDC4P2__DROPOUT_CTRL_BP 28
|
||||
#define HW_POWER_DCDC4P2__DROPOUT_CTRL_BM (0xf << 28)
|
||||
#define HW_POWER_DCDC4P2__DROPOUT_CTRL__200mV (3 << 30)
|
||||
#define HW_POWER_DCDC4P2__DROPOUT_CTRL__HIGHER (2 << 28)
|
||||
|
||||
#define HW_POWER_MISC (*(volatile uint32_t *)(HW_POWER_BASE + 0x90))
|
||||
#define HW_POWER_MISC__SEL_PLLCLK 1
|
||||
#define HW_POWER_MISC__FREQSEL_BP 4
|
||||
#define HW_POWER_MISC__FREQSEL_BM (0x7 << 4)
|
||||
#define HW_POWER_MISC__FREQSEL__RES 0
|
||||
#define HW_POWER_MISC__FREQSEL__20MHz 1
|
||||
#define HW_POWER_MISC__FREQSEL__24MHz 2
|
||||
#define HW_POWER_MISC__FREQSEL__19p2MHz 3
|
||||
#define HW_POWER_MISC__FREQSEL__14p4MHz 4
|
||||
#define HW_POWER_MISC__FREQSEL__18MHz 5
|
||||
#define HW_POWER_MISC__FREQSEL__21p6MHz 6
|
||||
#define HW_POWER_MISC__FREQSEL__17p28MHz 7
|
||||
|
||||
#define HW_POWER_LOOPCTRL (*(volatile uint32_t *)(HW_POWER_BASE + 0xb0))
|
||||
#define HW_POWER_LOOPCTRL__DC_C_BP 0
|
||||
#define HW_POWER_LOOPCTRL__DC_C_BM 0x3
|
||||
#define HW_POWER_LOOPCTRL__DC_R_BP 4
|
||||
#define HW_POWER_LOOPCTRL__DC_R_BM 0xf0
|
||||
#define HW_POWER_LOOPCTRL__DC_FF_BP 8
|
||||
#define HW_POWER_LOOPCTRL__DC_FF_BM (0x7 << 8)
|
||||
#define HW_POWER_LOOPCTRL__EN_RCSCALE_BP 12
|
||||
#define HW_POWER_LOOPCTRL__EN_RCSCALE_BM (0x3 << 12)
|
||||
#define HW_POWER_LOOPCTRL__EN_RCSCALE__DISABLED 0
|
||||
#define HW_POWER_LOOPCTRL__EN_RCSCALE__2X 1
|
||||
#define HW_POWER_LOOPCTRL__EN_RCSCALE__4X 2
|
||||
#define HW_POWER_LOOPCTRL__EN_RCSCALE__8X 3
|
||||
#define HW_POWER_LOOPCTRL__RCSCALE_THRESH (1 << 14)
|
||||
#define HW_POWER_LOOPCTRL__DF_HYST_THRESH (1 << 15)
|
||||
#define HW_POWER_LOOPCTRL__CM_HYST_THRESH (1 << 16)
|
||||
#define HW_POWER_LOOPCTRL__EN_DF_HYST (1 << 17)
|
||||
#define HW_POWER_LOOPCTRL__EN_CM_HYST (1 << 18)
|
||||
#define HW_POWER_LOOPCTRL__HYST_SIGN (1 << 19)
|
||||
#define HW_POWER_LOOPCTRL__TOGGLE_DIF (1 << 20)
|
||||
|
||||
#define HW_POWER_STS (*(volatile uint32_t *)(HW_POWER_BASE + 0xc0))
|
||||
#define HW_POWER_STS__VBUSVALID (1 << 1)
|
||||
#define HW_POWER_STS__CHRGSTS (1 << 11)
|
||||
#define HW_POWER_STS__PSWITCH_BP 20
|
||||
#define HW_POWER_STS__PSWITCH_BM (3 << 20)
|
||||
#define HW_POWER_STS__PWRUP_SOURCE_BP 24
|
||||
#define HW_POWER_STS__PWRUP_SOURCE_BM (0x3f << 24)
|
||||
|
||||
#define HW_POWER_BATTMONITOR (*(volatile uint32_t *)(HW_POWER_BASE + 0xe0))
|
||||
#define HW_POWER_BATTMONITOR__ENBATADJ (1 << 10)
|
||||
#define HW_POWER_BATTMONITOR__BATT_VAL_BP 16
|
||||
#define HW_POWER_BATTMONITOR__BATT_VAL_BM (0x3ff << 16)
|
||||
|
||||
#define HW_POWER_RESET (*(volatile uint32_t *)(HW_POWER_BASE + 0x100))
|
||||
#define HW_POWER_RESET__UNLOCK 0x3E770000
|
||||
#define HW_POWER_RESET__PWD 0x1
|
||||
#define BV_POWER_MISC_FREQSEL__RES 0
|
||||
#define BV_POWER_MISC_FREQSEL__20MHz 1
|
||||
#define BV_POWER_MISC_FREQSEL__24MHz 2
|
||||
#define BV_POWER_MISC_FREQSEL__19p2MHz 3
|
||||
#define BV_POWER_MISC_FREQSEL__14p4MHz 4
|
||||
#define BV_POWER_MISC_FREQSEL__18MHz 5
|
||||
#define BV_POWER_MISC_FREQSEL__21p6MHz 6
|
||||
#define BV_POWER_MISC_FREQSEL__17p28MHz 7
|
||||
|
||||
void imx233_power_init(void);
|
||||
|
||||
|
|
@ -209,13 +99,9 @@ void imx233_power_set_regulator_linreg(enum imx233_regulator_t reg,
|
|||
|
||||
static inline void imx233_power_set_dcdc_freq(bool pll, unsigned freq)
|
||||
{
|
||||
HW_POWER_MISC &= ~(HW_POWER_MISC__SEL_PLLCLK | HW_POWER_MISC__FREQSEL_BM);
|
||||
/* WARNING: HW_POWER_MISC does not have a SET/CLR variant ! */
|
||||
if(pll)
|
||||
{
|
||||
HW_POWER_MISC |= freq << HW_POWER_MISC__FREQSEL_BP;
|
||||
HW_POWER_MISC |= HW_POWER_MISC__SEL_PLLCLK;
|
||||
}
|
||||
BF_WR(POWER_MISC, FREQSEL, freq);
|
||||
BF_WR(POWER_MISC, SEL_PLLCLK, pll);
|
||||
}
|
||||
|
||||
struct imx233_power_info_t
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ static int timeout_4p2_ilimit_increase; /* timeout before increasing 4p2 ilimit
|
|||
int _battery_voltage(void)
|
||||
{
|
||||
/* battery value is in 8mV LSB */
|
||||
return __XTRACT(HW_POWER_BATTMONITOR, BATT_VAL) * 8;
|
||||
return BF_RD(POWER_BATTMONITOR, BATT_VAL) * 8;
|
||||
}
|
||||
|
||||
void powermgmt_init_target(void)
|
||||
|
|
@ -49,12 +49,12 @@ void powermgmt_init_target(void)
|
|||
imx233_power_set_charge_current(IMX233_CHARGE_CURRENT);
|
||||
imx233_power_set_stop_current(IMX233_STOP_CURRENT);
|
||||
/* assume that adc_init was called and battery monitoring via LRADC setup */
|
||||
__REG_SET(HW_POWER_BATTMONITOR) = HW_POWER_BATTMONITOR__ENBATADJ;
|
||||
BF_WR(POWER_BATTMONITOR, EN_BATADJ, 1);
|
||||
/* make sure we are in a known state: disable charger and 4p2 */
|
||||
__REG_SET(HW_POWER_CHARGE) = HW_POWER_CHARGE__PWD_BATTCHRG;
|
||||
__REG_CLR(HW_POWER_DCDC4P2) = HW_POWER_DCDC4P2__ENABLE_DCDC |
|
||||
HW_POWER_DCDC4P2__ENABLE_4P2;
|
||||
__REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__PWD_CHARGE_4P2;
|
||||
BF_SET(POWER_CHARGE, PWD_BATTCHRG);
|
||||
BF_WR(POWER_DCDC4P2, ENABLE_DCDC, 0);
|
||||
BF_WR(POWER_DCDC4P2, ENABLE_4P2, 0);
|
||||
BF_SET(POWER_5VCTRL, PWD_CHARGE_4P2);
|
||||
charge_state = DISCHARGING;
|
||||
}
|
||||
|
||||
|
|
@ -68,10 +68,10 @@ void charging_algorithm_step(void)
|
|||
logf("pwrmgmt: * -> discharging");
|
||||
logf("pwrmgmt: disable charger and 4p2");
|
||||
/* 5V has been lost: disable 4p2 power rail */
|
||||
__REG_SET(HW_POWER_CHARGE) = HW_POWER_CHARGE__PWD_BATTCHRG;
|
||||
__REG_CLR(HW_POWER_DCDC4P2) = HW_POWER_DCDC4P2__ENABLE_DCDC |
|
||||
HW_POWER_DCDC4P2__ENABLE_4P2;
|
||||
__REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__PWD_CHARGE_4P2;
|
||||
BF_SET(POWER_CHARGE, PWD_BATTCHRG);
|
||||
BF_WR(POWER_DCDC4P2, ENABLE_DCDC, 0);
|
||||
BF_WR(POWER_DCDC4P2, ENABLE_4P2, 0);
|
||||
BF_SET(POWER_5VCTRL, PWD_CHARGE_4P2);
|
||||
charge_state = DISCHARGING;
|
||||
}
|
||||
/* battery -> 5v transition */
|
||||
|
|
@ -80,11 +80,11 @@ void charging_algorithm_step(void)
|
|||
logf("pwrmgmt: discharging -> trickle");
|
||||
logf("pwrmgmt: begin charging 4p2");
|
||||
/* 5V has been detected: prepare 4.2V power rail for activation */
|
||||
__REG_SET(HW_POWER_DCDC4P2) = HW_POWER_DCDC4P2__ENABLE_4P2;
|
||||
__REG_SET(HW_POWER_CHARGE) = HW_POWER_CHARGE__ENABLE_LOAD;
|
||||
__FIELD_SET(HW_POWER_5VCTRL, CHARGE_4P2_ILIMIT, 1);
|
||||
__REG_CLR(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__PWD_CHARGE_4P2;// FIXME: manual error ?
|
||||
__REG_SET(HW_POWER_DCDC4P2) = HW_POWER_DCDC4P2__ENABLE_DCDC;
|
||||
BF_WR(POWER_DCDC4P2, ENABLE_4P2, 1);
|
||||
BF_SET(POWER_CHARGE, ENABLE_LOAD);
|
||||
BF_WR(POWER_5VCTRL, CHARGE_4P2_ILIMIT, 1);
|
||||
BF_CLR(POWER_5VCTRL, PWD_CHARGE_4P2);// FIXME: manual error ?
|
||||
BF_WR(POWER_DCDC4P2, ENABLE_DCDC, 1);
|
||||
timeout_4p2_ilimit_increase = current_tick + HZ / 100;
|
||||
charge_state = TRICKLE;
|
||||
}
|
||||
|
|
@ -92,10 +92,10 @@ void charging_algorithm_step(void)
|
|||
{
|
||||
/* if 4.2V current limit has not reached 780mA, increase it slowly to
|
||||
* charge the 4.2V capacitance */
|
||||
if(__XTRACT(HW_POWER_5VCTRL, CHARGE_4P2_ILIMIT) != 0x3f)
|
||||
if(BF_RD(POWER_5VCTRL, CHARGE_4P2_ILIMIT) != 0x3f)
|
||||
{
|
||||
//logf("pwrmgmt: incr 4.2 ilimit");
|
||||
HW_POWER_5VCTRL += 1 << HW_POWER_5VCTRL__CHARGE_4P2_ILIMIT_BP;
|
||||
HW_POWER_5VCTRL += BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(1);
|
||||
timeout_4p2_ilimit_increase = current_tick + HZ / 100;
|
||||
}
|
||||
/* we've reached the maximum, take action */
|
||||
|
|
@ -104,12 +104,12 @@ void charging_algorithm_step(void)
|
|||
logf("pwrmgmt: enable dcdc and charger");
|
||||
logf("pwrmgmt: trickle -> charging");
|
||||
/* adjust arbitration between 4.2 and battery */
|
||||
__FIELD_SET(HW_POWER_DCDC4P2, CMPTRIP, 0); /* 85% */
|
||||
__FIELD_SET(HW_POWER_DCDC4P2, DROPOUT_CTRL, 0xe); /* select greater, 200 mV drop */
|
||||
__REG_CLR(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__DCDC_XFER;
|
||||
__REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__ENABLE_DCDC;
|
||||
BF_WR(POWER_DCDC4P2, CMPTRIP, 0); /* 85% */
|
||||
BF_WR(POWER_DCDC4P2, DROPOUT_CTRL, 0xe); /* select greater, 200 mV drop */
|
||||
BF_CLR(POWER_5VCTRL, DCDC_XFER);
|
||||
BF_SET(POWER_5VCTRL, ENABLE_DCDC);
|
||||
/* enable battery charging */
|
||||
__REG_CLR(HW_POWER_CHARGE) = HW_POWER_CHARGE__PWD_BATTCHRG;
|
||||
BF_CLR(POWER_CHARGE, PWD_BATTCHRG);
|
||||
charge_state = CHARGING;
|
||||
timeout_charging = current_tick + IMX233_CHARGING_TIMEOUT;
|
||||
}
|
||||
|
|
@ -120,11 +120,11 @@ void charging_algorithm_step(void)
|
|||
logf("pwrmgmt: charging timeout exceeded!");
|
||||
logf("pwrmgmt: charging -> error");
|
||||
/* stop charging */
|
||||
__REG_SET(HW_POWER_5VCTRL) = HW_POWER_5VCTRL__PWD_CHARGE_4P2;
|
||||
BF_SET(POWER_5VCTRL, PWD_CHARGE_4P2);
|
||||
/* goto error state */
|
||||
charge_state = CHARGE_STATE_ERROR;
|
||||
}
|
||||
else if(charge_state == CHARGING && !(HW_POWER_STS & HW_POWER_STS__CHRGSTS))
|
||||
else if(charge_state == CHARGING && !BF_RD(POWER_STS, CHRGSTS))
|
||||
{
|
||||
logf("pwrmgmt: topping off");
|
||||
logf("pwrmgmt: charging -> topoff");
|
||||
|
|
@ -136,7 +136,7 @@ void charging_algorithm_step(void)
|
|||
logf("pwrmgmt: charging finished");
|
||||
logf("pwrmgmt: topoff -> disabled");
|
||||
/* stop charging */
|
||||
__REG_SET(HW_POWER_CHARGE) = HW_POWER_CHARGE__PWD_BATTCHRG;
|
||||
BF_SET(POWER_CHARGE, PWD_BATTCHRG);
|
||||
charge_state = CHARGE_STATE_DISABLED;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -369,7 +369,7 @@ int button_read_device(void)
|
|||
static int volume_power_lock = 0;
|
||||
if(volume_power_lock > 0)
|
||||
volume_power_lock--;
|
||||
switch(__XTRACT(HW_POWER_STS, PSWITCH))
|
||||
switch(BF_RD(POWER_STS, PSWITCH))
|
||||
{
|
||||
case 1:
|
||||
if(volume_power_lock == 0)
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ void usb_init_device(void)
|
|||
|
||||
int usb_detect(void)
|
||||
{
|
||||
return (HW_POWER_STS & HW_POWER_STS__VBUSVALID) ? USB_INSERTED : USB_EXTRACTED;
|
||||
return BF_RD(POWER_STS, VBUSVALID) ? USB_INSERTED : USB_EXTRACTED;
|
||||
}
|
||||
|
||||
void usb_enable(bool on)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue