forked from len0rd/rockbox
Gigabeat S: Implement a genuine udelay function. Timer is gated to not run in WFI mode to save power and as such time until rollover is variable.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19820 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
da76a34694
commit
7bcfc38b42
4 changed files with 123 additions and 19 deletions
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@ -514,6 +514,92 @@
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#define EPITSR_OCIF (1 << 0)
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/* GPT */
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#define GPTCR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x00))
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#define GPTPR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x04))
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#define GPTSR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x08))
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#define GPTIR (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x0C))
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#define GPTOCR1 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x10))
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#define GPTOCR2 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x14))
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#define GPTOCR3 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x18))
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#define GPTICR1 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x1C))
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#define GPTICR2 (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x20))
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#define GPTCNT (*(REG32_PTR_T)(GPT1_BASE_ADDR+0x24))
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/* GPTCR */
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#define GPTCR_FO3 (0x1 << 31)
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#define GPTCR_FO2 (0x1 << 30)
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#define GPTCR_FO1 (0x1 << 29)
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#define GPTCR_OM3 (0x7 << 26)
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#define GPTCR_OM3_DISCONNECTED (0x0 << 26)
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#define GPTCR_OM3_TOGGLE (0x1 << 26)
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#define GPTCR_OM3_CLEAR (0x2 << 26)
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#define GPTCR_OM3_SET (0x3 << 26)
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#define GPTCR_OM3_SINGLE_COUNT (0x4 << 26)
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/* 0x5-0x7 same as 0x4 */
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#define GPTCR_OM2 (0x7 << 23)
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#define GPTCR_OM2_DISCONNECTED (0x0 << 23)
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#define GPTCR_OM2_TOGGLE (0x1 << 23)
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#define GPTCR_OM2_CLEAR (0x2 << 23)
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#define GPTCR_OM2_SET (0x3 << 23)
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#define GPTCR_OM2_SINGLE_COUNT (0x4 << 23)
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/* 0x5-0x7 same as 0x4 */
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#define GPTCR_OM1 (0x7 << 20)
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#define GPTCR_OM1_DISCONNECTED (0x0 << 20)
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#define GPTCR_OM1_TOGGLE (0x1 << 20)
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#define GPTCR_OM1_CLEAR (0x2 << 20)
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#define GPTCR_OM1_SET (0x3 << 20)
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#define GPTCR_OM1_SINGLE_COUNT (0x4 << 20)
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/* 0x5-0x7 same as 0x4 */
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#define GPTCR_IM2 (0x3 << 18)
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#define GPTCR_IM2_DISABLED (0x0 << 18)
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#define GPTCR_IM2_RISING (0x1 << 18)
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#define GPTCR_IM2_FALLING (0x2 << 18)
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#define GPTCR_IM2_BOTH (0x3 << 18)
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#define GPTCR_IM1 (0x3 << 16)
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#define GPTCR_IM1_DISABLED (0x0 << 16)
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#define GPTCR_IM1_RISING (0x1 << 16)
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#define GPTCR_IM1_FALLING (0x2 << 16)
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#define GPTCR_IM1_BOTH (0x3 << 16)
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#define GPTCR_SWR (0x1 << 15)
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#define GPTCR_FRR (0x1 << 9)
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#define GPTCR_CLKSRC (0x7 << 6)
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#define GPTCR_CLKSRC_NONE (0x0 << 6)
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#define GPTCR_CLKSRC_IPG_CLK (0x1 << 6)
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#define GPTCR_CLKSRC_IPG_CLK_HIGHFREQ (0x2 << 6)
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#define GPTCR_CLKSRC_IPG_CLK_32K (0x4 << 6)
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/* Other values not defined */
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#define GPTCR_STOPEN (0x1 << 5)
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#define GPTCR_DOZEN (0x1 << 4)
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#define GPTCR_WAITEN (0x1 << 3)
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#define GPTCR_DBGEN (0x1 << 2)
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#define GPTCR_ENMODE (0x1 << 1)
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#define GPTCR_EN (0x1 << 0)
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/* GPTSR */
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#define GPTSR_ROV (0x1 << 5)
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#define GPTSR_IF2 (0x1 << 4)
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#define GPTSR_IF1 (0x1 << 3)
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#define GPTSR_OF3 (0x1 << 2)
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#define GPTSR_OF2 (0x1 << 1)
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#define GPTSR_OF1 (0x1 << 0)
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/* GPTIR */
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#define GPTIR_ROV (0x1 << 5)
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#define GPTIR_IF2IE (0x1 << 4)
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#define GPTIR_IF1IE (0x1 << 3)
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#define GPTIR_OF3IE (0x1 << 2)
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#define GPTIR_OF2IE (0x1 << 1)
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#define GPTIR_OF1IE (0x1 << 0)
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/* GPIO */
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#define GPIO1_DR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x00))
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#define GPIO1_GDIR (*(REG32_PTR_T)(GPIO1_BASE_ADDR+0x04))
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@ -68,8 +68,6 @@ static __attribute__((interrupt("IRQ"))) void KPP_HANDLER(void)
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for (col = 0; col < 3; col++) /* Col */
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{
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int i;
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/* 2. Write 1s to KPDR[10:8] setting column data to 1s */
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KPP_KPDR |= (0x7 << 8);
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@ -78,8 +76,7 @@ static __attribute__((interrupt("IRQ"))) void KPP_HANDLER(void)
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KPP_KPCR &= ~(0x7 << 8);
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/* Give the columns time to discharge */
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for (i = 0; i < 128; i++) /* TODO: find minimum safe delay */
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asm volatile ("");
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udelay(2);
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/* 4. Configure columns as open-drain */
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KPP_KPCR |= (0x7 << 8);
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@ -94,8 +91,7 @@ static __attribute__((interrupt("IRQ"))) void KPP_HANDLER(void)
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/* Delay added to avoid propagating the 0 from column to row
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* when scanning. */
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for (i = 0; i < 128; i++) /* TODO: find minimum safe delay */
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asm volatile ("");
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udelay(2);
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/* Read row input */
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button |= (~KPP_KPDR & kms[col].mask) << kms[col].shift;
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@ -32,6 +32,8 @@
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#include "clkctl-imx31.h"
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#include "mc13783.h"
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/** Watchdog timer routines **/
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/* Initialize the watchdog timer */
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void watchdog_init(unsigned int half_seconds)
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{
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@ -57,6 +59,33 @@ void watchdog_service(void)
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WDOG_WSR = 0xaaaa;
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}
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/** GPT timer routines - basis for udelay **/
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/* Start the general-purpose timer (1MHz) */
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void gpt_start(void)
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{
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imx31_clkctl_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT);
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unsigned int ipg_mhz = imx31_clkctl_get_ipg_clk() / 1000000;
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GPTCR &= ~GPTCR_EN; /* Disable counter */
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GPTCR |= GPTCR_SWR; /* Reset module */
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while (GPTCR & GPTCR_SWR);
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/* No output
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* No capture
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* Enable in run mode only (doesn't tick while in WFI)
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* Freerun mode (count to 0xFFFFFFFF and roll-over to 0x00000000)
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*/
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GPTCR = GPTCR_FRR | GPTCR_CLKSRC_IPG_CLK;
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GPTPR = ipg_mhz - 1;
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GPTCR |= GPTCR_EN;
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}
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/* Stop the general-purpose timer */
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void gpt_stop(void)
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{
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GPTCR &= ~GPTCR_EN;
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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@ -84,7 +113,6 @@ void system_init(void)
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/* CGR0 */
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CG_SD_MMC1,
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CG_SD_MMC2,
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CG_GPT,
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CG_IIM,
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CG_SDMA,
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CG_CSPI3,
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@ -140,6 +168,7 @@ void system_init(void)
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imx31_clkctl_module_clock_gating(disable_clocks[i], CGM_OFF);
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avic_init();
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gpt_start();
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gpio_init();
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}
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@ -31,25 +31,18 @@
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#define CPUFREQ_MAX CPU_FREQ
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#endif
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/* For USB driver - no accuracy assurance */
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static inline void udelay(unsigned int usecs)
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{
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unsigned int x;
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for (x = 0; x < 300*usecs; x++)
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asm volatile ("");
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unsigned stop = GPTCNT + usecs;
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while (TIME_BEFORE(GPTCNT, stop));
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}
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#if 0
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static inline void udelay(unsigned int usecs)
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{
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volatile signed int stop = EPITCNT1 - usecs;
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while ((signed int)EPITCNT1 > stop);
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}
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#endif
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void watchdog_init(unsigned int half_seconds);
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void watchdog_service(void);
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void gpt_start(void);
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void gpt_stop(void);
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/* Prepare for transition to firmware */
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void system_prepare_fw_start(void);
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void tick_stop(void);
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