forked from len0rd/rockbox
iPod Nano 2G NAND/ECC driver and FTL improvements (still polling)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22958 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sparmann
parent
112bc15d65
commit
79bf2da1ef
2 changed files with 176 additions and 51 deletions
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@ -26,6 +26,35 @@
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#include <nand-target.h>
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#include <ftl-target.h>
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#include <string.h>
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#include "kernel.h"
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#include "panic.h"
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//#define FTL_FORCEMOUNT
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#ifdef FTL_FORCEMOUNT
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#ifndef FTL_READONLY
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#define FTL_READONLY
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#endif
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#endif
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#ifdef FTL_READONLY
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uint32_t ftl_write(uint32_t sector, uint32_t count, const void* buffer)
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{
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(void)sector;
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(void)count;
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(void)buffer;
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return 1;
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}
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uint32_t ftl_sync(void)
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{
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return 0;
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}
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#endif
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@ -371,6 +400,8 @@ uint8_t ftl_erasectr_dirt[8];
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#endif
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static struct mutex ftl_mtx;
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/* Finds a device info page for the specified bank and returns its number.
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@ -653,6 +684,7 @@ void ftl_vfl_schedule_block_for_remap(uint32_t bank, uint32_t block)
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{
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if (ftl_vfl_check_remap_scheduled(bank, block) == 1)
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return;
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panicf("FTL: Scheduling bank %d block %d for remap!", bank, block);
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if (ftl_vfl_cxt[bank].scheduledstart == ftl_vfl_cxt[bank].spareused)
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return;
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ftl_vfl_cxt[bank].remaptable[--ftl_vfl_cxt[bank].scheduledstart] = block;
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@ -738,6 +770,7 @@ uint32_t ftl_vfl_remap_block(uint32_t bank, uint32_t block)
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{
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uint32_t i;
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uint32_t newblock = 0, newidx;
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panicf("FTL: Remapping bank %d block %d!", bank, block);
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if (bank >= ftl_banks || block >= (*ftl_nand_type).blocks) return 0;
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for (i = 0; i < ftl_vfl_cxt[bank].sparecount; i++)
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if (ftl_vfl_cxt[bank].remaptable[i] == 0)
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@ -949,7 +982,9 @@ uint32_t ftl_open(void)
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else
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{
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/* This will trip if there was an unclean unmount before. */
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#ifndef FTL_FORCEMOUNT
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break;
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#endif
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}
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}
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@ -1030,6 +1065,8 @@ uint32_t ftl_read(uint32_t sector, uint32_t count, void* buffer)
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if (count == 0) return 0;
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mutex_lock(&ftl_mtx);
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for (i = 0; i < count; i++)
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{
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uint32_t block = (sector + i) / ppb;
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@ -1054,6 +1091,9 @@ uint32_t ftl_read(uint32_t sector, uint32_t count, void* buffer)
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memset(&((uint8_t*)buffer)[i << 11], 0, 0x800);
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}
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}
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mutex_unlock(&ftl_mtx);
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return error;
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}
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@ -1609,11 +1649,17 @@ uint32_t ftl_write(uint32_t sector, uint32_t count, const void* buffer)
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if (count == 0) return 0;
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mutex_lock(&ftl_mtx);
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if (ftl_cxt.clean_flag == 1)
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{
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for (i = 0; i < 3; i++)
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{
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if (ftl_next_ctrl_pool_page() != 0) return 1;
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if (ftl_next_ctrl_pool_page() != 0)
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{
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mutex_unlock(&ftl_mtx);
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return 1;
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}
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memset(ftl_buffer, 0xFF, 0x800);
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memset(&ftl_sparebuffer, 0xFF, 0x40);
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ftl_sparebuffer.meta.usn = ftl_cxt.usn;
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@ -1622,7 +1668,11 @@ uint32_t ftl_write(uint32_t sector, uint32_t count, const void* buffer)
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&ftl_sparebuffer) == 0)
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break;
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}
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if (i == 3) return 1;
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if (i == 3)
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{
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mutex_unlock(&ftl_mtx);
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return 1;
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}
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ftl_cxt.clean_flag = 0;
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}
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@ -1632,7 +1682,11 @@ uint32_t ftl_write(uint32_t sector, uint32_t count, const void* buffer)
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uint32_t page = (sector + i) % ppb;
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struct ftl_log_type* logentry = ftl_allocate_log_entry(block);
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if (logentry == (struct ftl_log_type*)0) return 1;
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if (logentry == (struct ftl_log_type*)0)
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{
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mutex_unlock(&ftl_mtx);
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return 1;
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}
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if (page == 0 && count - i >= ppb)
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{
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uint32_t vblock = (*logentry).scatteredvblock;
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@ -1641,7 +1695,11 @@ uint32_t ftl_write(uint32_t sector, uint32_t count, const void* buffer)
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{
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ftl_release_pool_block(vblock);
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vblock = ftl_allocate_pool_block();
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if (vblock == 0) return 1;
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if (vblock == 0)
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{
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mutex_unlock(&ftl_mtx);
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return 1;
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}
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}
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ftl_cxt.nextblockusn++;
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for (j = 0; j < ppb; j++)
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@ -1665,7 +1723,11 @@ uint32_t ftl_write(uint32_t sector, uint32_t count, const void* buffer)
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{
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ftl_remove_scattered_block(logentry);
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logentry = ftl_allocate_log_entry(block);
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if (logentry == (struct ftl_log_type*)0) return 1;
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if (logentry == (struct ftl_log_type*)0)
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{
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mutex_unlock(&ftl_mtx);
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return 1;
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}
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}
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memset(&ftl_sparebuffer, 0xFF, 0x40);
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ftl_sparebuffer.user.lpn = sector + i;
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@ -1699,6 +1761,7 @@ uint32_t ftl_write(uint32_t sector, uint32_t count, const void* buffer)
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ftl_save_erasectr_page(i);
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}
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}
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mutex_unlock(&ftl_mtx);
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return 0;
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}
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#endif
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@ -1745,6 +1808,7 @@ uint32_t ftl_sync(void)
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which will just do nothing if everything was already clean. */
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uint32_t ftl_init(void)
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{
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mutex_init(&ftl_mtx);
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uint32_t i;
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uint32_t result = 0;
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uint32_t foundsignature, founddevinfo, blockwiped, repaired, skip;
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@ -1755,6 +1819,7 @@ uint32_t ftl_init(void)
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ftl_nand_type = nand_get_device_type(0);
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foundsignature = 0;
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blockwiped = 1;
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mutex_unlock(&ftl_mtx);
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for (i = 0; i < (*ftl_nand_type).pagesperblock; i++)
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{
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result = nand_read_page(0, i, ftl_buffer, (uint32_t*)0, 1, 1);
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@ -1772,10 +1837,23 @@ uint32_t ftl_init(void)
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repaired = 0;
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skip = 0;
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if (founddevinfo == 0) return 1;
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if (foundsignature != 0 && (result & 0x11F) != 0) return 1;
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if (founddevinfo == 0)
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{
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mutex_unlock(&ftl_mtx);
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return 1;
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}
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if (foundsignature != 0 && (result & 0x11F) != 0)
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{
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mutex_unlock(&ftl_mtx);
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return 1;
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}
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if (ftl_vfl_open() == 0)
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if (ftl_open() == 0) return 0;
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if (ftl_open() == 0)
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{
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mutex_unlock(&ftl_mtx);
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return 0;
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}
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/* Something went terribly wrong. We may want to allow the user to erase
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block zero in that condition, to make norboot reinitialize the FTL.
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@ -1785,5 +1863,7 @@ uint32_t ftl_init(void)
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nand_block_erase(0, 0);
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*/
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mutex_unlock(&ftl_mtx);
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return 1;
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}
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@ -22,6 +22,7 @@
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#include "config.h"
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#include "system.h"
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#include "kernel.h"
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#include "cpu.h"
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#include "inttypes.h"
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#include "nand-target.h"
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@ -84,6 +85,11 @@ uint8_t nand_tunk2[4];
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uint8_t nand_tunk3[4];
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uint32_t nand_type[4];
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static struct mutex nand_mtx;
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static struct wakeup nand_wakeup;
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static struct mutex ecc_mtx;
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static struct wakeup ecc_wakeup;
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static uint8_t nand_aligned_data[0x800] __attribute__((aligned(32)));
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static uint8_t nand_aligned_ctrl[0x200] __attribute__((aligned(32)));
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static uint8_t nand_aligned_spare[0x40] __attribute__((aligned(32)));
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@ -98,35 +104,60 @@ static uint8_t nand_aligned_ecc[0x28] __attribute__((aligned(32)));
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((uint8_t*)(((uint32_t)nand_aligned_ecc) | 0x40000000))
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uint32_t nand_unlock(uint32_t rc)
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{
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mutex_unlock(&nand_mtx);
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return rc;
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}
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uint32_t ecc_unlock(uint32_t rc)
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{
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mutex_unlock(&ecc_mtx);
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return rc;
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}
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uint32_t nand_timeout(long timeout)
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{
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if (TIME_AFTER(current_tick, timeout)) return 1;
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else
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{
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yield();
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return 0;
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}
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}
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uint32_t nand_wait_rbbdone(void)
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{
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uint32_t timeout = 0x40000;
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while ((FMCSTAT & FMCSTAT_RBBDONE) == 0) if (timeout-- == 0) return 1;
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long timeout = current_tick + HZ / 1;
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while ((FMCSTAT & FMCSTAT_RBBDONE) == 0)
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if (nand_timeout(timeout)) return 1;
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FMCSTAT = FMCSTAT_RBBDONE;
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return 0;
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}
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uint32_t nand_wait_cmddone(void)
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{
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uint32_t timeout = 0x40000;
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while ((FMCSTAT & FMCSTAT_CMDDONE) == 0) if (timeout-- == 0) return 1;
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long timeout = current_tick + HZ / 1;
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while ((FMCSTAT & FMCSTAT_CMDDONE) == 0)
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if (nand_timeout(timeout)) return 1;
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FMCSTAT = FMCSTAT_CMDDONE;
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return 0;
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}
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uint32_t nand_wait_addrdone(void)
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{
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uint32_t timeout = 0x40000;
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while ((FMCSTAT & FMCSTAT_ADDRDONE) == 0) if (timeout-- == 0) return 1;
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long timeout = current_tick + HZ / 1;
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while ((FMCSTAT & FMCSTAT_ADDRDONE) == 0)
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if (nand_timeout(timeout)) return 1;
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FMCSTAT = FMCSTAT_ADDRDONE;
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return 0;
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}
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uint32_t nand_wait_chip_ready(uint32_t bank)
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{
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uint32_t timeout = 0x40000;
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long timeout = current_tick + HZ / 1;
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while ((FMCSTAT & (FMCSTAT_BANK0READY << bank)) == 0)
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if (timeout-- == 0) return 1;
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if (nand_timeout(timeout)) return 1;
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FMCSTAT = (FMCSTAT_BANK0READY << bank);
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return 0;
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}
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@ -163,7 +194,7 @@ uint32_t nand_reset(uint32_t bank)
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uint32_t nand_wait_status_ready(uint32_t bank)
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{
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uint32_t timeout = 0x4000;
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long timeout = current_tick + HZ / 1;
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nand_set_fmctrl0(bank, 0);
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if ((FMCSTAT & (FMCSTAT_BANK0READY << bank)) != 0)
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FMCSTAT = (FMCSTAT_BANK0READY << bank);
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@ -171,7 +202,7 @@ uint32_t nand_wait_status_ready(uint32_t bank)
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if (nand_send_cmd(NAND_CMD_GET_STATUS) != 0) return 1;
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while (1)
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{
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if (timeout-- == 0) return 1;
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if (nand_timeout(timeout)) return 1;
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FMDNUM = 0;
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FMCTRL1 = FMCTRL1_DOREADDATA;
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if (nand_wait_addrdone() != 0) return 1;
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@ -185,7 +216,7 @@ uint32_t nand_wait_status_ready(uint32_t bank)
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uint32_t nand_transfer_data(uint32_t bank, uint32_t direction,
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void* buffer, uint32_t size)
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{
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uint32_t timeout = 0x40000;
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long timeout = current_tick + HZ / 1;
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nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
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FMDNUM = size - 1;
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FMCTRL1 = FMCTRL1_DOREADDATA << direction;
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@ -199,7 +230,7 @@ uint32_t nand_transfer_data(uint32_t bank, uint32_t direction,
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DMATCNT3 = (size >> 4) - 1;
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DMACOM3 = 4;
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while ((DMAALLST & DMAALLST_DMABUSY3) != 0)
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if (timeout-- == 0) return 1;
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if (nand_timeout(timeout)) return 1;
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if (nand_wait_addrdone() != 0) return 1;
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if (direction == 0) FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
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return 0;
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@ -207,32 +238,36 @@ uint32_t nand_transfer_data(uint32_t bank, uint32_t direction,
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uint32_t ecc_decode(uint32_t size, void* databuffer, void* sparebuffer)
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{
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uint32_t timeout = 0x40000;
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mutex_lock(&ecc_mtx);
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long timeout = current_tick + HZ / 1;
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ECC_INT_CLR = 1;
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SRCPND = INTMSK_ECC;
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ECC_UNK1 = size;
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ECC_DATA_PTR = (uint32_t)databuffer;
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ECC_SPARE_PTR = (uint32_t)sparebuffer;
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ECC_CTRL = ECCCTRL_STARTDECODING;
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while ((SRCPND & INTMSK_ECC) == 0) if (timeout-- == 0) return 1;
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while ((SRCPND & INTMSK_ECC) == 0)
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if (nand_timeout(timeout)) return ecc_unlock(1);
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ECC_INT_CLR = 1;
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SRCPND = INTMSK_ECC;
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return ECC_RESULT;
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return ecc_unlock(ECC_RESULT);
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}
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uint32_t ecc_encode(uint32_t size, void* databuffer, void* sparebuffer)
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{
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uint32_t timeout = 0x40000;
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mutex_lock(&ecc_mtx);
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long timeout = current_tick + HZ / 1;
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ECC_INT_CLR = 1;
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SRCPND = INTMSK_ECC;
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ECC_UNK1 = size;
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ECC_DATA_PTR = (uint32_t)databuffer;
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ECC_SPARE_PTR = (uint32_t)sparebuffer;
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ECC_CTRL = ECCCTRL_STARTENCODING;
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while ((SRCPND & INTMSK_ECC) == 0) if (timeout-- == 0) return 1;
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while ((SRCPND & INTMSK_ECC) == 0)
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if (nand_timeout(timeout)) return ecc_unlock(1);
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ECC_INT_CLR = 1;
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SRCPND = INTMSK_ECC;
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return 0;
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return ecc_unlock(0);
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}
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uint32_t nand_check_empty(uint8_t* buffer)
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@ -246,51 +281,53 @@ uint32_t nand_check_empty(uint8_t* buffer)
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uint32_t nand_get_chip_type(uint32_t bank)
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{
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mutex_lock(&nand_mtx);
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uint32_t result;
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if (nand_reset(bank) != 0) return 0xFFFFFFFF;
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if (nand_send_cmd(0x90) != 0) return 0xFFFFFFFF;
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if (nand_reset(bank) != 0) return nand_unlock(0xFFFFFFFF);
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if (nand_send_cmd(0x90) != 0) return nand_unlock(0xFFFFFFFF);
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FMANUM = 0;
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FMADDR0 = 0;
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FMCTRL1 = FMCTRL1_DOTRANSADDR;
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if (nand_wait_cmddone() != 0) return 0xFFFFFFFF;
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if (nand_wait_cmddone() != 0) return nand_unlock(0xFFFFFFFF);
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FMDNUM = 4;
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FMCTRL1 = FMCTRL1_DOREADDATA;
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if (nand_wait_addrdone() != 0) return 0xFFFFFFFF;
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if (nand_wait_addrdone() != 0) return nand_unlock(0xFFFFFFFF);
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result = FMFIFO;
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FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
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return result;
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return nand_unlock(result);
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}
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uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer,
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void* sparebuffer, uint32_t doecc,
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uint32_t checkempty)
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{
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mutex_lock(&nand_mtx);
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uint32_t rc, eccresult;
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||||
nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
|
||||
if (nand_send_cmd(NAND_CMD_READ) != 0) return 1;
|
||||
if (nand_send_cmd(NAND_CMD_READ) != 0) return nand_unlock(1);
|
||||
if (nand_send_address(page, (databuffer == 0) ? 0x800 : 0) != 0)
|
||||
return 1;
|
||||
if (nand_send_cmd(NAND_CMD_READ2) != 0) return 1;
|
||||
if (nand_wait_status_ready(bank) != 0) return 1;
|
||||
return nand_unlock(1);
|
||||
if (nand_send_cmd(NAND_CMD_READ2) != 0) return nand_unlock(1);
|
||||
if (nand_wait_status_ready(bank) != 0) return nand_unlock(1);
|
||||
if (databuffer != 0)
|
||||
if (nand_transfer_data(bank, 0, nand_uncached_data, 0x800) != 0)
|
||||
return 1;
|
||||
return nand_unlock(1);
|
||||
if (doecc == 0)
|
||||
{
|
||||
memcpy(databuffer, nand_uncached_data, 0x800);
|
||||
if (sparebuffer != 0)
|
||||
{
|
||||
if (nand_transfer_data(bank, 0, nand_uncached_spare, 0x40) != 0)
|
||||
return 1;
|
||||
return nand_unlock(1);
|
||||
memcpy(sparebuffer, nand_uncached_spare, 0x800);
|
||||
if (checkempty != 0)
|
||||
return nand_check_empty((uint8_t*)sparebuffer) << 1;
|
||||
}
|
||||
return 0;
|
||||
return nand_unlock(0);
|
||||
}
|
||||
rc = 0;
|
||||
if (nand_transfer_data(bank, 0, nand_uncached_spare, 0x40) != 0)
|
||||
return 1;
|
||||
return nand_unlock(1);
|
||||
memcpy(nand_uncached_ecc, &nand_uncached_spare[0xC], 0x28);
|
||||
rc |= (ecc_decode(3, nand_uncached_data, nand_uncached_ecc) & 0xF) << 4;
|
||||
if (databuffer != 0) memcpy(databuffer, nand_uncached_data, 0x800);
|
||||
|
|
@ -307,51 +344,54 @@ uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer,
|
|||
}
|
||||
if (checkempty != 0) rc |= nand_check_empty(nand_uncached_spare) << 1;
|
||||
|
||||
return rc;
|
||||
return nand_unlock(rc);
|
||||
}
|
||||
|
||||
uint32_t nand_write_page(uint32_t bank, uint32_t page, void* databuffer,
|
||||
void* sparebuffer, uint32_t doecc)
|
||||
{
|
||||
mutex_lock(&nand_mtx);
|
||||
if (sparebuffer != 0) memcpy(nand_uncached_spare, sparebuffer, 0x40);
|
||||
else memset(nand_uncached_spare, 0xFF, 0x40);
|
||||
if (doecc != 0)
|
||||
{
|
||||
memcpy(nand_uncached_data, databuffer, 0x800);
|
||||
if (ecc_encode(3, nand_uncached_data, nand_uncached_ecc) != 0)
|
||||
return 1;
|
||||
return nand_unlock(1);
|
||||
memcpy(&nand_uncached_spare[0xC], nand_uncached_ecc, 0x28);
|
||||
memset(nand_uncached_ctrl, 0xFF, 0x200);
|
||||
memcpy(nand_uncached_ctrl, nand_uncached_spare, 0xC);
|
||||
if (ecc_encode(0, nand_uncached_ctrl, nand_uncached_ecc) != 0)
|
||||
return 1;
|
||||
return nand_unlock(1);
|
||||
memcpy(&nand_uncached_spare[0x34], nand_uncached_ecc, 0xC);
|
||||
}
|
||||
nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
|
||||
if (nand_send_cmd(NAND_CMD_PROGRAM) != 0)
|
||||
return 1;
|
||||
return nand_unlock(1);
|
||||
if (nand_send_address(page, (databuffer == 0) ? 0x800 : 0) != 0)
|
||||
return 1;
|
||||
return nand_unlock(1);
|
||||
if (databuffer != 0)
|
||||
if (nand_transfer_data(bank, 1, nand_uncached_data, 0x800) != 0)
|
||||
return 1;
|
||||
return nand_unlock(1);
|
||||
if (sparebuffer != 0 || doecc != 0)
|
||||
if (nand_transfer_data(bank, 1, nand_uncached_spare, 0x40) != 0)
|
||||
return 1;
|
||||
if (nand_send_cmd(NAND_CMD_PROGCNFRM) != 0) return 1;
|
||||
return nand_unlock(1);
|
||||
if (nand_send_cmd(NAND_CMD_PROGCNFRM) != 0) return nand_unlock(1);
|
||||
return nand_wait_status_ready(bank);
|
||||
}
|
||||
|
||||
uint32_t nand_block_erase(uint32_t bank, uint32_t page)
|
||||
{
|
||||
mutex_lock(&nand_mtx);
|
||||
nand_set_fmctrl0(bank, 0);
|
||||
if (nand_send_cmd(NAND_CMD_BLOCKERASE) != 0) return 1;
|
||||
if (nand_send_cmd(NAND_CMD_BLOCKERASE) != 0) return nand_unlock(1);
|
||||
FMANUM = 2;
|
||||
FMADDR0 = page;
|
||||
FMCTRL1 = FMCTRL1_DOTRANSADDR;
|
||||
if (nand_wait_cmddone() != 0) return 1;
|
||||
if (nand_send_cmd(NAND_CMD_ERASECNFRM) != 0) return 1;
|
||||
return nand_wait_status_ready(bank);
|
||||
if (nand_wait_cmddone() != 0) return nand_unlock(1);
|
||||
if (nand_send_cmd(NAND_CMD_ERASECNFRM) != 0) return nand_unlock(1);
|
||||
if (nand_wait_status_ready(bank) != 0) return nand_unlock(1);
|
||||
return nand_unlock(0);
|
||||
}
|
||||
|
||||
const struct nand_device_info_type* nand_get_device_type(uint32_t bank)
|
||||
|
|
@ -363,6 +403,11 @@ const struct nand_device_info_type* nand_get_device_type(uint32_t bank)
|
|||
|
||||
uint32_t nand_device_init(void)
|
||||
{
|
||||
mutex_init(&nand_mtx);
|
||||
wakeup_init(&nand_wakeup);
|
||||
mutex_init(&ecc_mtx);
|
||||
wakeup_init(&ecc_wakeup);
|
||||
|
||||
uint32_t type;
|
||||
uint32_t i, j;
|
||||
PCON2 = 0x33333333;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue