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Finish the conversion to packed i2s for PP502x. Karl Kurbjun-approved for Mini-1G. Simplify the pcm format selection #ifdefs.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15137 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2007-10-16 04:19:18 +00:00
parent 9b1f1dd0b4
commit 782aae4402
2 changed files with 1 additions and 48 deletions
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8
firmware/target/arm/i2s-pp.c
View file

@ -71,15 +71,7 @@ void i2s_reset(void)
IISDIV = 7; IISDIV = 7;
#endif /* HAVE_AS3514 */ #endif /* HAVE_AS3514 */
#if defined (IRIVER_H10) || defined (IRIVER_H10_5GB) || defined(IPOD_NANO) \
|| defined(IPOD_VIDEO) || defined(IPOD_MINI2G) \
|| defined(IPOD_COLOR) || defined(IPOD_4G) \
|| defined (SANSA_C200) || defined (SANSA_E200)
/* Nano works fine with IIS_FIFO_FORMAT_LE16 as well */
IISCONFIG = ((IISCONFIG & ~IIS_FIFO_FORMAT_MASK) | IIS_FIFO_FORMAT_LE16_2); IISCONFIG = ((IISCONFIG & ~IIS_FIFO_FORMAT_MASK) | IIS_FIFO_FORMAT_LE16_2);
#else
IISCONFIG = ((IISCONFIG & ~IIS_FIFO_FORMAT_MASK) | IIS_FIFO_FORMAT_LE32);
#endif
/* RX_ATN_LVL = when 12 slots full */ /* RX_ATN_LVL = when 12 slots full */
/* TX_ATN_LVL = when 12 slots empty */ /* TX_ATN_LVL = when 12 slots empty */

41
firmware/target/arm/pcm-pp.c
View file

@ -25,25 +25,12 @@
/** DMA **/ /** DMA **/
/* List of transfer settings. Defined by player in order to have an inventory #ifdef CPU_PP502x
of working settings. DMA-compatible settings should be found for here, i2s,
and codec setup using "arithmetic" the hardware supports like halfword
swapping. Try to use 32-bit packed in IIS modes if possible. */
#if defined(SANSA_C200) || defined(SANSA_E200) \
|| defined(IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_NANO) \
|| defined(IPOD_VIDEO) || defined(IPOD_MINI2G) \
|| defined(IPOD_COLOR) || defined(IPOD_4G)
/* 16-bit, L-R packed into 32 bits with left in the least significant halfword */ /* 16-bit, L-R packed into 32 bits with left in the least significant halfword */
#define SAMPLE_SIZE 16 #define SAMPLE_SIZE 16
#define TRANSFER_SIZE 32
#elif 0
/* 16-bit, one left 16-bit sample followed by one right 16-bit sample */
#define SAMPLE_SIZE 16
#define TRANSFER_SIZE 16
#else #else
/* 32-bit, one left 32-bit sample followed by one right 32-bit sample */ /* 32-bit, one left 32-bit sample followed by one right 32-bit sample */
#define SAMPLE_SIZE 32 #define SAMPLE_SIZE 32
#define TRANSFER_SIZE 32
#endif #endif
struct dma_data struct dma_data
@ -51,11 +38,7 @@ struct dma_data
/* NOTE: The order of size and p is important if you use assembler /* NOTE: The order of size and p is important if you use assembler
optimised fiq handler, so don't change it. */ optimised fiq handler, so don't change it. */
#if SAMPLE_SIZE == 16 #if SAMPLE_SIZE == 16
#if TRANSFER_SIZE == 16
uint16_t *p;
#elif TRANSFER_SIZE == 32
uint32_t *p; uint32_t *p;
#endif
#elif SAMPLE_SIZE == 32 #elif SAMPLE_SIZE == 32
uint16_t *p; uint16_t *p;
#endif #endif
@ -140,15 +123,8 @@ void fiq_playback(void)
"ands r12, r12, %[mask] \n" "ands r12, r12, %[mask] \n"
"beq .exit \n" /* FIFO full, exit */ "beq .exit \n" /* FIFO full, exit */
#if SAMPLE_SIZE == 16 #if SAMPLE_SIZE == 16
#if TRANSFER_SIZE == 16
"ldrh r12, [r8], #2 \n" /* Load left channel */
"strh r12, [r10, %[wr]] \n" /* Store it */
"ldrh r12, [r8], #2 \n" /* Load right channel */
"strh r12, [r10, %[wr]] \n" /* Store it */
#elif TRANSFER_SIZE == 32
"ldr r12, [r8], #4 \n" /* load two samples */ "ldr r12, [r8], #4 \n" /* load two samples */
"str r12, [r10, %[wr]] \n" /* write them */ "str r12, [r10, %[wr]] \n" /* write them */
#endif
#elif SAMPLE_SIZE == 32 #elif SAMPLE_SIZE == 32
"ldr r12, [r8], #4 \n" /* load two samples */ "ldr r12, [r8], #4 \n" /* load two samples */
"mov r12, r12, ror #16 \n" /* put left sample at the top bits */ "mov r12, r12, ror #16 \n" /* put left sample at the top bits */
@ -206,12 +182,7 @@ void fiq_playback(void)
return; return;
} }
#if SAMPLE_SIZE == 16 #if SAMPLE_SIZE == 16
#if TRANSFER_SIZE == 16
IISFIFO_WRH = *dma_play_data.p++;
IISFIFO_WRH = *dma_play_data.p++;
#elif TRANSFER_SIZE == 32
IISFIFO_WR = *dma_play_data.p++; IISFIFO_WR = *dma_play_data.p++;
#endif
#elif SAMPLE_SIZE == 32 #elif SAMPLE_SIZE == 32
IISFIFO_WR = *dma_play_data.p++ << 16; IISFIFO_WR = *dma_play_data.p++ << 16;
IISFIFO_WR = *dma_play_data.p++ << 16; IISFIFO_WR = *dma_play_data.p++ << 16;
@ -274,12 +245,7 @@ static void play_start_pcm(void)
} }
#if SAMPLE_SIZE == 16 #if SAMPLE_SIZE == 16
#if TRANSFER_SIZE == 16
IISFIFO_WRH = *dma_play_data.p++;
IISFIFO_WRH = *dma_play_data.p++;
#elif TRANSFER_SIZE == 32
IISFIFO_WR = *dma_play_data.p++; IISFIFO_WR = *dma_play_data.p++;
#endif
#elif SAMPLE_SIZE == 32 #elif SAMPLE_SIZE == 32
IISFIFO_WR = *dma_play_data.p++ << 16; IISFIFO_WR = *dma_play_data.p++ << 16;
IISFIFO_WR = *dma_play_data.p++ << 16; IISFIFO_WR = *dma_play_data.p++ << 16;
@ -496,12 +462,7 @@ void fiq_record(void)
} }
#if SAMPLE_SIZE == 16 #if SAMPLE_SIZE == 16
#if TRANSFER_SIZE == 16
*dma_rec_data.p++ = IISFIFO_RDH;
*dma_rec_data.p++ = IISFIFO_RDH;
#elif TRANSFER_SIZE == 32
*dma_rec_data.p++ = IISFIFO_RD; *dma_rec_data.p++ = IISFIFO_RD;
#endif
#elif SAMPLE_SIZE == 32 #elif SAMPLE_SIZE == 32
*dma_rec_data.p++ = IISFIFO_RD >> 16; *dma_rec_data.p++ = IISFIFO_RD >> 16;
*dma_rec_data.p++ = IISFIFO_RD >> 16; *dma_rec_data.p++ = IISFIFO_RD >> 16;