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I2S buffer level adjustment is not necessary on c200 as there is no memory mapped framebuffer that requires constant cache flushing like on e200.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14974 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold 2007-10-03 22:31:51 +00:00
parent 4ebe69293c
commit 6dd3f449b3
2 changed files with 3 additions and 3 deletions
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2
firmware/target/arm/i2s-pp.c
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@ -142,7 +142,7 @@ void i2s_reset(void)
IISFIFO_CFG |= 0x1100; IISFIFO_CFG |= 0x1100;
} }
#if defined(SANSA_E200) || defined(SANSA_C200) #ifdef SANSA_E200
void i2s_scale_attn_level(long frequency) void i2s_scale_attn_level(long frequency)
{ {
unsigned int iisfifo_cfg = IISFIFO_CFG & ~0xff; unsigned int iisfifo_cfg = IISFIFO_CFG & ~0xff;

4
firmware/target/arm/system-pp502x.c
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@ -142,7 +142,7 @@ static void pp_set_cpu_frequency(long frequency)
while (test_and_set(&boostctrl_mtx.locked, 1)) ; while (test_and_set(&boostctrl_mtx.locked, 1)) ;
#endif #endif
#if defined(SANSA_E200) || defined(SANSA_C200) #ifdef SANSA_E200
i2s_scale_attn_level(CPUFREQ_DEFAULT); i2s_scale_attn_level(CPUFREQ_DEFAULT);
#endif #endif
@ -205,7 +205,7 @@ static void pp_set_cpu_frequency(long frequency)
CLCD_CLOCK_SRC; /* dummy read (to sync the write pipeline??) */ CLCD_CLOCK_SRC; /* dummy read (to sync the write pipeline??) */
CLCD_CLOCK_SRC = clcd_clock_src; /* restore saved value */ CLCD_CLOCK_SRC = clcd_clock_src; /* restore saved value */
#if defined(SANSA_E200) || defined(SANSA_C200) #ifdef SANSA_E200
i2s_scale_attn_level(frequency); i2s_scale_attn_level(frequency);
#endif #endif