forked from len0rd/rockbox
iPod Video: Fix playback after recording (FS #7402). Implement recording gain adjustment. * Enable timeout for zero-crossing detection (SLOWCLK), avoids hanging volume/ gain due to DC offsets.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18509 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
c487c01d46
commit
6938083e4f
5 changed files with 369 additions and 198 deletions
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@ -41,117 +41,113 @@ const struct sound_settings_info audiohw_settings[] = {
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[SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
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[SOUND_CHANNELS] = {"", 0, 1, 0, 5, 0},
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[SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
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[SOUND_STEREO_WIDTH] = {"%", 0, 5, 0, 250, 100},
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#ifdef HAVE_RECORDING
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#ifdef HAVE_RECORDING
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[SOUND_LEFT_GAIN] = {"dB", 1, 1,-128, 96, 0},
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[SOUND_LEFT_GAIN] = {"dB", 1, 1, 0, 63, 16},
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[SOUND_RIGHT_GAIN] = {"dB", 1, 1,-128, 96, 0},
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[SOUND_RIGHT_GAIN] = {"dB", 1, 1, 0, 63, 16},
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[SOUND_MIC_GAIN] = {"dB", 1, 1,-128, 108, 16},
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[SOUND_MIC_GAIN] = {"dB", 1, 1, 0, 63, 16},
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#endif
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#endif
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[SOUND_BASS_CUTOFF] = {"", 0, 1, 1, 4, 1},
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[SOUND_BASS_CUTOFF] = {"", 0, 1, 1, 4, 1},
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[SOUND_TREBLE_CUTOFF] = {"", 0, 1, 1, 4, 1},
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[SOUND_TREBLE_CUTOFF] = {"", 0, 1, 1, 4, 1},
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};
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};
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/* shadow registers */
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/* shadow registers */
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unsigned int eq1_reg;
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static unsigned short eq1_reg = EQ1_EQ3DMODE | EQ_GAIN_VALUE(0);
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unsigned int eq5_reg;
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static unsigned short eq5_reg = EQ_GAIN_VALUE(0);
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/* convert tenth of dB volume (-57..6) to master volume register value */
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/* convert tenth of dB volume (-57..6) to master volume register value */
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int tenthdb2master(int db)
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int tenthdb2master(int db)
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{
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{
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/* +6 to -57dB in 1dB steps == 64 levels = 6 bits */
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/* 0111111 == +6dB (0x3f) = 63) */
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/* 0111001 == 0dB (0x39) = 57) */
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/* 0000001 == -56dB (0x01) = */
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/* 0000000 == -57dB (0x00) */
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/* 1000000 == Mute (0x40) */
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if (db < VOLUME_MIN) {
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if (db < VOLUME_MIN) {
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return 0x40;
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return 0x40;
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} else {
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} else {
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return((db/10)+57);
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return (db/10)+57;
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}
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}
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}
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}
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/* convert tenth of dB volume (-780..0) to mixer volume register value */
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int sound_val2phys(int setting, int value)
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int tenthdb2mixer(int db)
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{
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{
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if (db < -660) /* 1.5 dB steps */
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int result;
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return (2640 - db) / 15;
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else if (db < -600) /* 0.75 dB steps */
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return (990 - db) * 2 / 15;
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else if (db < -460) /* 0.5 dB steps */
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return (460 - db) / 5;
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else /* 0.25 dB steps */
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return -db * 2 / 5;
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}
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#define IPOD_PCM_LEVEL 0x65 /* -6dB */
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switch(setting)
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//#define BASSCTRL 0x
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//#define TREBCTRL 0x0b
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/* Silently enable / disable audio output */
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void audiohw_enable_output(bool enable)
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{
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if (enable)
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{
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{
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/* reset the I2S controller into known state */
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#ifdef HAVE_RECORDING
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i2s_reset();
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case SOUND_LEFT_GAIN:
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case SOUND_RIGHT_GAIN:
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/* TODO: Review the power-up sequence to prevent pops */
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case SOUND_MIC_GAIN:
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result = ((value - 16) * 15) / 2;
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wmcodec_write(RESET, 0x1ff); /*Reset*/
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break;
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#endif
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wmcodec_write(PWRMGMT1, 0x2b);
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default:
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wmcodec_write(PWRMGMT2, 0x180);
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result = value;
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wmcodec_write(PWRMGMT3, 0x6f);
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break;
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wmcodec_write(AINTFCE, 0x10);
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wmcodec_write(CLKCTRL, 0x49);
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wmcodec_write(OUTCTRL, 1);
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/* The iPod can handle multiple frequencies, but fix at 44.1KHz
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for now */
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audiohw_set_sample_rate(WM8758_44100HZ);
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wmcodec_write(LOUTMIX,0x1); /* Enable mixer */
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wmcodec_write(ROUTMIX,0x1); /* Enable mixer */
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audiohw_mute(0);
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} else {
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audiohw_mute(1);
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}
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}
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return result;
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}
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void audiohw_mute(bool mute)
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{
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if (mute) {
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wmcodec_write(DACCTRL, DACCTRL_SOFTMUTE);
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} else {
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wmcodec_write(DACCTRL, 0);
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}
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}
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void audiohw_preinit(void)
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{
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i2s_reset();
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wmcodec_write(RESET, RESET_RESET);
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wmcodec_write(PWRMGMT1, PWRMGMT1_PLLEN | PWRMGMT1_BIASEN
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| PWRMGMT1_VMIDSEL_5K);
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wmcodec_write(PWRMGMT2, PWRMGMT2_ROUT1EN | PWRMGMT2_LOUT1EN);
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wmcodec_write(PWRMGMT3, PWRMGMT3_LOUT2EN | PWRMGMT3_ROUT2EN
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| PWRMGMT3_RMIXEN | PWRMGMT3_LMIXEN
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| PWRMGMT3_DACENR | PWRMGMT3_DACENL);
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wmcodec_write(AINTFCE, AINTFCE_IWL_16BIT | AINTFCE_FORMAT_I2S);
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wmcodec_write(OUTCTRL, OUTCTRL_VROI);
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wmcodec_write(CLKCTRL, CLKCTRL_MS); /* WM8758 is clock master */
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audiohw_set_sample_rate(WM8758_44100HZ);
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wmcodec_write(LOUTMIX, LOUTMIX_DACL2LMIX);
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wmcodec_write(ROUTMIX, ROUTMIX_DACR2RMIX);
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}
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void audiohw_postinit(void)
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{
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wmcodec_write(PWRMGMT1, PWRMGMT1_PLLEN | PWRMGMT1_BIASEN
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| PWRMGMT1_VMIDSEL_75K);
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/* lower the VMID power consumption */
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audiohw_mute(false);
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}
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}
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void audiohw_set_master_vol(int vol_l, int vol_r)
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void audiohw_set_master_vol(int vol_l, int vol_r)
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{
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{
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/* OUT1 */
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/* OUT1 */
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wmcodec_write(LOUT1VOL, 0x080 | vol_l);
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wmcodec_write(LOUT1VOL, LOUT1VOL_LOUT1ZC | vol_l);
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wmcodec_write(ROUT1VOL, 0x180 | vol_r);
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wmcodec_write(ROUT1VOL, ROUT1VOL_OUT1VU | ROUT1VOL_ROUT1ZC | vol_r);
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}
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}
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void audiohw_set_lineout_vol(int vol_l, int vol_r)
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void audiohw_set_lineout_vol(int vol_l, int vol_r)
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{
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{
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/* OUT2 */
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/* OUT2 */
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wmcodec_write(LOUT2VOL, vol_l);
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wmcodec_write(LOUT2VOL, LOUT2VOL_LOUT2ZC | vol_l);
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wmcodec_write(ROUT2VOL, 0x100 | vol_r);
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wmcodec_write(ROUT2VOL, ROUT2VOL_OUT2VU | ROUT2VOL_ROUT2ZC | vol_r);
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}
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void audiohw_set_mixer_vol(int channel1, int channel2)
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{
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(void)channel1;
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(void)channel2;
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}
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}
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void audiohw_set_bass(int value)
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void audiohw_set_bass(int value)
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{
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{
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eq1_reg = (eq1_reg & ~EQ_GAIN_MASK) | EQ_GAIN_VALUE(value);
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eq1_reg = (eq1_reg & ~EQ_GAIN_MASK) | EQ_GAIN_VALUE(value);
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wmcodec_write(EQ1, 0x100 | eq1_reg);
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wmcodec_write(EQ1, eq1_reg);
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}
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}
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void audiohw_set_bass_cutoff(int value)
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void audiohw_set_bass_cutoff(int value)
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{
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{
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eq1_reg = (eq1_reg & ~EQ_CUTOFF_MASK) | EQ_CUTOFF_VALUE(value);
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eq1_reg = (eq1_reg & ~EQ_CUTOFF_MASK) | EQ_CUTOFF_VALUE(value);
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wmcodec_write(EQ1, 0x100 | eq1_reg);
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wmcodec_write(EQ1, eq1_reg);
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}
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}
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void audiohw_set_treble(int value)
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void audiohw_set_treble(int value)
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@ -166,31 +162,16 @@ void audiohw_set_treble_cutoff(int value)
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wmcodec_write(EQ5, eq5_reg);
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wmcodec_write(EQ5, eq5_reg);
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}
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}
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void audiohw_mute(bool mute)
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{
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if (mute)
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{
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/* Set DACMU = 1 to soft-mute the audio DACs. */
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wmcodec_write(DACCTRL, 0x40);
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} else {
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/* Set DACMU = 0 to soft-un-mute the audio DACs. */
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wmcodec_write(DACCTRL, 0x0);
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}
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}
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/* Nice shutdown of WM8758 codec */
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/* Nice shutdown of WM8758 codec */
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void audiohw_close(void)
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void audiohw_close(void)
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{
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{
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audiohw_mute(1);
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audiohw_mute(true);
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wmcodec_write(PWRMGMT3, 0x0);
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wmcodec_write(PWRMGMT3, 0);
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wmcodec_write(PWRMGMT1, 0);
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wmcodec_write(PWRMGMT1, 0x0);
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wmcodec_write(PWRMGMT2, PWRMGMT2_SLEEP);
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wmcodec_write(PWRMGMT2, 0x40);
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}
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}
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/* Change the order of the noise shaper, 5th order is recommended above 32kHz */
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void audiohw_set_nsorder(int order)
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void audiohw_set_nsorder(int order)
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{
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{
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(void)order;
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(void)order;
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@ -202,89 +183,68 @@ void audiohw_set_sample_rate(int sampling_control)
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/**** We force 44.1KHz for now. ****/
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/**** We force 44.1KHz for now. ****/
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(void)sampling_control;
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(void)sampling_control;
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/* set clock div */
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wmcodec_write(CLKCTRL, 1 | (0 << 2) | (2 << 5));
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/* setup PLL for MHZ=11.2896 */
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/* setup PLL for MHZ=11.2896 */
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wmcodec_write(PLLN, (1 << 4) | 0x7);
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wmcodec_write(PLLN, PLLN_PLLPRESCALE | 0x7);
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wmcodec_write(PLLK1, 0x21);
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wmcodec_write(PLLK1, 0x21);
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wmcodec_write(PLLK2, 0x161);
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wmcodec_write(PLLK2, 0x161);
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wmcodec_write(PLLK3, 0x26);
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wmcodec_write(PLLK3, 0x26);
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/* set clock div */
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/* set clock div */
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wmcodec_write(CLKCTRL, 1 | (1 << 2) | (2 << 5) | (1 << 8));
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wmcodec_write(CLKCTRL, CLKCTRL_CLKSEL | CLKCTRL_MCLKDIV_2
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| CLKCTRL_BCLKDIV_2 | CLKCTRL_MS);
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/* set srate */
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wmcodec_write(ADDCTRL, ADDCTRL_SR_48kHz | ADDCTRL_SLOWCLKEN);
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wmcodec_write(SRATECTRL, (0 << 1));
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/* SLOWCLK enabled for zero cross timeout to work */
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}
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}
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void audiohw_enable_recording(bool source_mic)
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void audiohw_enable_recording(bool source_mic)
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{
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{
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(void)source_mic; /* We only have a line-in (I think) */
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(void)source_mic; /* We only have a line-in (I think) */
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/* reset the I2S controller into known state */
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wmcodec_write(PWRMGMT2, PWRMGMT2_ROUT1EN | PWRMGMT2_LOUT1EN
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i2s_reset();
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| PWRMGMT2_INPGAENR | PWRMGMT2_INPGAENL
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| PWRMGMT2_ADCENR | PWRMGMT2_ADCENL);
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wmcodec_write(RESET, 0x1ff); /*Reset*/
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wmcodec_write(INCTRL, INCTRL_R2_2INPGA | INCTRL_L2_2INPGA);
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wmcodec_write(PWRMGMT1, 0x2b);
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wmcodec_write(LADCBOOST, LADCBOOST_L2_2BOOST(5));
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wmcodec_write(PWRMGMT2, 0x18f); /* Enable ADC - 0x0c enables left/right PGA input, and 0x03 turns on power to the ADCs */
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wmcodec_write(RADCBOOST, RADCBOOST_R2_2BOOST(5));
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wmcodec_write(PWRMGMT3, 0x6f);
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wmcodec_write(AINTFCE, 0x10);
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wmcodec_write(CLKCTRL, 0x49);
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wmcodec_write(OUTCTRL, 1);
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/* The iPod can handle multiple frequencies, but fix at 44.1KHz
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for now */
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audiohw_set_sample_rate(WM8758_44100HZ);
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wmcodec_write(INCTRL,0x44); /* Connect L2 and R2 inputs */
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/* Set L2/R2_2BOOSTVOL to 0db (bits 4-6) */
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/* 000 = disabled
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001 = -12dB
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010 = -9dB
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011 = -6dB
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100 = -3dB
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101 = 0dB
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110 = 3dB
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111 = 6dB
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*/
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wmcodec_write(LADCBOOST,0x50);
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wmcodec_write(RADCBOOST,0x50);
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/* Set L/R input PGA Volume to 0db */
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// wm8758_write(LINPGAVOL,0x3f);
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// wm8758_write(RINPGAVOL,0x13f);
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/* Enable monitoring */
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/* Enable monitoring */
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wmcodec_write(LOUTMIX,0x17); /* Enable output mixer - BYPL2LMIX @ 0db*/
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wmcodec_write(LOUTMIX, LOUTMIX_BYP2LMIXVOL(5)
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wmcodec_write(ROUTMIX,0x17); /* Enable output mixer - BYPR2RMIX @ 0db*/
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| LOUTMIX_BYPL2LMIX | LOUTMIX_DACL2LMIX);
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wmcodec_write(ROUTMIX, ROUTMIX_BYP2RMIXVOL(5)
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audiohw_mute(0);
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| ROUTMIX_BYPR2RMIX | ROUTMIX_DACR2RMIX);
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}
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}
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void audiohw_disable_recording(void) {
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void audiohw_disable_recording(void)
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audiohw_mute(1);
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{
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wmcodec_write(LOUTMIX, LOUTMIX_DACL2LMIX);
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wmcodec_write(ROUTMIX, ROUTMIX_DACR2RMIX);
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wmcodec_write(PWRMGMT3, 0x0);
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wmcodec_write(PWRMGMT2, PWRMGMT2_ROUT1EN | PWRMGMT2_LOUT1EN);
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wmcodec_write(PWRMGMT1, 0x0);
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wmcodec_write(PWRMGMT2, 0x40);
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}
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}
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void audiohw_set_recvol(int left, int right, int type) {
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void audiohw_set_recvol(int left, int right, int type)
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{
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(void)left;
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switch (type)
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(void)right;
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{
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(void)type;
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case AUDIO_GAIN_MIC:
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right = left;
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/* fall through */
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case AUDIO_GAIN_LINEIN:
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wmcodec_write(LINPGAVOL, LINPGAVOL_INPGAZCL
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| (left & LINPGAVOL_INPGAVOL_MASK));
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wmcodec_write(RINPGAVOL, RINPGAVOL_INPGAVU | RINPGAVOL_INPGAZCR
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| (right & RINPGAVOL_INPGAVOL_MASK));
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break;
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default:
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return;
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}
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}
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}
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void audiohw_set_monitor(bool enable) {
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void audiohw_set_monitor(bool enable)
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{
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(void)enable;
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(void)enable;
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}
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}
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@ -37,53 +37,261 @@ extern void audiohw_set_mixer_vol(int channel1, int channel2);
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extern void audiohw_set_nsorder(int order);
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extern void audiohw_set_nsorder(int order);
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extern void audiohw_set_sample_rate(int sampling_control);
|
extern void audiohw_set_sample_rate(int sampling_control);
|
||||||
|
|
||||||
#define RESET 0x00
|
#define RESET 0x00
|
||||||
#define PWRMGMT1 0x01
|
#define RESET_RESET 0x0
|
||||||
#define PWRMGMT2 0x02
|
|
||||||
#define PWRMGMT3 0x03
|
|
||||||
#define AINTFCE 0x04
|
|
||||||
#define CLKCTRL 0x06
|
|
||||||
#define SRATECTRL 0x07
|
|
||||||
#define DACCTRL 0x0a
|
|
||||||
#define INCTRL 0x2c
|
|
||||||
#define LINPGAVOL 0x2d
|
|
||||||
#define RINPGAVOL 0x2e
|
|
||||||
#define LADCBOOST 0x2f
|
|
||||||
#define RADCBOOST 0x30
|
|
||||||
#define OUTCTRL 0x31
|
|
||||||
#define LOUTMIX 0x32
|
|
||||||
#define ROUTMIX 0x33
|
|
||||||
|
|
||||||
#define LOUT1VOL 0x34
|
#define PWRMGMT1 0x01
|
||||||
#define ROUT1VOL 0x35
|
#define PWRMGMT1_VMIDSEL_OFF (0 << 0)
|
||||||
#define LOUT2VOL 0x36
|
#define PWRMGMT1_VMIDSEL_75K (1 << 0)
|
||||||
#define ROUT2VOL 0x37
|
#define PWRMGMT1_VMIDSEL_300K (2 << 0)
|
||||||
|
#define PWRMGMT1_VMIDSEL_5K (3 << 0)
|
||||||
|
#define PWRMGMT1_BUFIOEN (1 << 2)
|
||||||
|
#define PWRMGMT1_BIASEN (1 << 3)
|
||||||
|
#define PWRMGMT1_MICBEN (1 << 4)
|
||||||
|
#define PWRMGMT1_PLLEN (1 << 5)
|
||||||
|
#define PWRMGMT1_OUT3MIXEN (1 << 6)
|
||||||
|
#define PWRMGMT1_OUT4MIXEN (1 << 7)
|
||||||
|
#define PWRMGMT1_BUFDCOPEN (1 << 8)
|
||||||
|
|
||||||
#define PLLN 0x24
|
#define PWRMGMT2 0x02
|
||||||
#define PLLK1 0x25
|
#define PWRMGMT2_ADCENL (1 << 0)
|
||||||
#define PLLK2 0x26
|
#define PWRMGMT2_ADCENR (1 << 1)
|
||||||
#define PLLK3 0x27
|
#define PWRMGMT2_INPGAENL (1 << 2)
|
||||||
|
#define PWRMGMT2_INPGAENR (1 << 3)
|
||||||
|
#define PWRMGMT2_BOOSTENL (1 << 4)
|
||||||
|
#define PWRMGMT2_BOOSTENR (1 << 5)
|
||||||
|
#define PWRMGMT2_SLEEP (1 << 6)
|
||||||
|
#define PWRMGMT2_LOUT1EN (1 << 7)
|
||||||
|
#define PWRMGMT2_ROUT1EN (1 << 8)
|
||||||
|
|
||||||
#define EQ1 0x12
|
#define PWRMGMT3 0x03
|
||||||
#define EQ2 0x13
|
#define PWRMGMT3_DACENL (1 << 0)
|
||||||
#define EQ3 0x14
|
#define PWRMGMT3_DACENR (1 << 1)
|
||||||
#define EQ4 0x15
|
#define PWRMGMT3_LMIXEN (1 << 2)
|
||||||
#define EQ5 0x16
|
#define PWRMGMT3_RMIXEN (1 << 3)
|
||||||
#define EQ_GAIN_MASK 0x001f
|
#define PWRMGMT3_ROUT2EN (1 << 5)
|
||||||
#define EQ_CUTOFF_MASK 0x0060
|
#define PWRMGMT3_LOUT2EN (1 << 6)
|
||||||
#define EQ_GAIN_VALUE(x) (((-x) + 12) & 0x1f)
|
#define PWRMGMT3_OUT3EN (1 << 7)
|
||||||
#define EQ_CUTOFF_VALUE(x) ((((x) - 1) & 0x03) << 5)
|
#define PWRMGMT3_OUT4EN (1 << 8)
|
||||||
|
|
||||||
/* Register settings for the supported samplerates: */
|
#define AINTFCE 0x04
|
||||||
#define WM8758_8000HZ 0x4d
|
#define AINTFCE_MONO (1 << 0)
|
||||||
#define WM8758_12000HZ 0x61
|
#define AINTFCE_ALRSWAP (1 << 1)
|
||||||
#define WM8758_16000HZ 0x55
|
#define AINTFCE_DLRSWAP (1 << 2)
|
||||||
#define WM8758_22050HZ 0x77
|
#define AINTFCE_FORMAT_MSB_RJUST (0 << 3)
|
||||||
#define WM8758_24000HZ 0x79
|
#define AINTFCE_FORMAT_MSB_LJUST (1 << 3)
|
||||||
#define WM8758_32000HZ 0x59
|
#define AINTFCE_FORMAT_I2S (2 << 3)
|
||||||
#define WM8758_44100HZ 0x63
|
#define AINTFCE_FORMAT_DSP (3 << 3)
|
||||||
#define WM8758_48000HZ 0x41
|
#define AINTFCE_FORMAT_MASK (3 << 3)
|
||||||
#define WM8758_88200HZ 0x7f
|
#define AINTFCE_IWL_16BIT (0 << 5)
|
||||||
#define WM8758_96000HZ 0x5d
|
#define AINTFCE_IWL_20BIT (1 << 5)
|
||||||
|
#define AINTFCE_IWL_24BIT (2 << 5)
|
||||||
|
#define AINTFCE_IWL_32BIT (3 << 5)
|
||||||
|
#define AINTFCE_IWL_MASK (3 << 5)
|
||||||
|
#define AINTFCE_LRP (1 << 7)
|
||||||
|
#define AINTFCE_BCP (1 << 8)
|
||||||
|
|
||||||
|
#define COMPCTRL 0x05 /* unused */
|
||||||
|
|
||||||
|
#define CLKCTRL 0x06
|
||||||
|
#define CLKCTRL_MS (1 << 0)
|
||||||
|
#define CLKCTRL_BCLKDIV_1 (0 << 2)
|
||||||
|
#define CLKCTRL_BCLKDIV_2 (1 << 2)
|
||||||
|
#define CLKCTRL_BCLKDIV_4 (2 << 2)
|
||||||
|
#define CLKCTRL_BCLKDIV_8 (3 << 2)
|
||||||
|
#define CLKCTRL_BCLKDIV_16 (4 << 2)
|
||||||
|
#define CLKCTRL_BCLKDIV_32 (5 << 2)
|
||||||
|
#define CLKCTRL_MCLKDIV_1 (0 << 5)
|
||||||
|
#define CLKCTRL_MCLKDIV_1_5 (1 << 5)
|
||||||
|
#define CLKCTRL_MCLKDIV_2 (2 << 5)
|
||||||
|
#define CLKCTRL_MCLKDIV_3 (3 << 5)
|
||||||
|
#define CLKCTRL_MCLKDIV_4 (4 << 5)
|
||||||
|
#define CLKCTRL_MCLKDIV_6 (5 << 5)
|
||||||
|
#define CLKCTRL_MCLKDIV_8 (6 << 5)
|
||||||
|
#define CLKCTRL_MCLKDIV_12 (7 << 5)
|
||||||
|
#define CLKCTRL_CLKSEL (1 << 8)
|
||||||
|
|
||||||
|
#define ADDCTRL 0x07
|
||||||
|
#define ADDCTRL_SLOWCLKEN (1 << 0)
|
||||||
|
#define ADDCTRL_SR_48kHz (0 << 1)
|
||||||
|
#define ADDCTRL_SR_32kHz (1 << 1)
|
||||||
|
#define ADDCTRL_SR_24kHz (2 << 1)
|
||||||
|
#define ADDCTRL_SR_16kHz (3 << 1)
|
||||||
|
#define ADDCTRL_SR_12kHz (4 << 1)
|
||||||
|
#define ADDCTRL_SR_8kHz (5 << 1)
|
||||||
|
#define ADDCTRL_SR_MASK (7 << 1)
|
||||||
|
|
||||||
|
/* unused */
|
||||||
|
#define GPIOCTRL 0x08
|
||||||
|
#define JACKDETECTCTRL1 0x09
|
||||||
|
|
||||||
|
#define DACCTRL 0x0a
|
||||||
|
#define DACCTRL_DACLPOL (1 << 0)
|
||||||
|
#define DACCTRL_DACRPOL (1 << 1)
|
||||||
|
#define DACCTRL_AMUTE (1 << 2)
|
||||||
|
#define DACCTRL_DACOSR128 (1 << 3)
|
||||||
|
#define DACCTRL_SOFTMUTE (1 << 6)
|
||||||
|
|
||||||
|
#define LDACVOL 0x0b
|
||||||
|
#define LDACVOL_MASK 0xff
|
||||||
|
#define LDACVOL_DACVU (1 << 8)
|
||||||
|
|
||||||
|
#define RDACVOL 0x0c
|
||||||
|
#define RDACVOL_MASK 0xff
|
||||||
|
#define RDACVOL_DACVU (1 << 8)
|
||||||
|
|
||||||
|
#define JACKDETECTCTRL2 0x0d /* unused */
|
||||||
|
|
||||||
|
#define ADCCTRL 0x0e
|
||||||
|
#define ADCCTRL_ADCLPOL (1 << 0)
|
||||||
|
#define ADCCTRL_ADCRPOL (1 << 1)
|
||||||
|
#define ADCCTRL_ADCOSR128 (1 << 3)
|
||||||
|
#define ADCCTRL_HPFCUT_MASK (7 << 4)
|
||||||
|
#define ADCCTRL_HPFAPP (1 << 7)
|
||||||
|
#define ADCCTRL_HPFEN (1 << 8)
|
||||||
|
|
||||||
|
#define LADCVOL 0x0f
|
||||||
|
#define LADCVOL_MASK 0xff
|
||||||
|
#define LADCVOL_ADCVU (1 << 8)
|
||||||
|
|
||||||
|
#define RADCVOL 0x10
|
||||||
|
#define RADCVOL_MASK 0xff
|
||||||
|
#define RADCVOL_ADCVU (1 << 8)
|
||||||
|
|
||||||
|
#define EQ1 0x12
|
||||||
|
#define EQ5 0x16
|
||||||
|
/* note: the WM8983 used for reference has a true 5 band EQ, but the WM8758
|
||||||
|
* does only have low shelf & high shelf (tested). Not sure about 3D mode. */
|
||||||
|
#define EQ1_EQ3DMODE (1 << 8)
|
||||||
|
#define EQ_GAIN_MASK 0x1f
|
||||||
|
#define EQ_CUTOFF_MASK (3 << 5)
|
||||||
|
#define EQ_GAIN_VALUE(x) (((-x) + 12) & 0x1f)
|
||||||
|
#define EQ_CUTOFF_VALUE(x) ((((x) - 1) & 0x03) << 5)
|
||||||
|
|
||||||
|
/* unused */
|
||||||
|
#define DACLIMITER1 0x18
|
||||||
|
#define DACLIMITER2 0x19
|
||||||
|
#define NOTCHFILTER1 0x1b
|
||||||
|
#define NOTCHFILTER2 0x1c
|
||||||
|
#define NOTCHFILTER3 0x1d
|
||||||
|
#define NOTCHFILTER4 0x1e
|
||||||
|
#define ALCCONTROL1 0x20
|
||||||
|
#define ALCCONTROL2 0x21
|
||||||
|
#define ALCCONTROL3 0x22
|
||||||
|
#define NOISEGATE 0x23
|
||||||
|
|
||||||
|
#define PLLN 0x24
|
||||||
|
#define PLLN_PLLN_MASK 0x0f
|
||||||
|
#define PLLN_PLLPRESCALE (1 << 4)
|
||||||
|
|
||||||
|
#define PLLK1 0x25
|
||||||
|
#define PLLK1_MASK 0x3f
|
||||||
|
|
||||||
|
#define PLLK2 0x26
|
||||||
|
#define PLLK3 0x27
|
||||||
|
|
||||||
|
#define THREEDCTRL 0x29
|
||||||
|
#define THREEDCTRL_DEPTH3D_MASK 0x0f
|
||||||
|
|
||||||
|
#define OUT4TOADC 0x2a
|
||||||
|
#define OUT4TOADC_OUT1DEL (1 << 0)
|
||||||
|
#define OUT4TOADC_DELEN (1 << 1)
|
||||||
|
#define OUT4TOADC_POBCTRL (1 << 2)
|
||||||
|
#define OUT4TOADC_OUT4_2LNR (1 << 5)
|
||||||
|
#define OUT4TOADC_OUT4_ADCVOL_MASK (7 << 6)
|
||||||
|
|
||||||
|
#define BEEPCTRL 0x2b
|
||||||
|
#define BEEPCTRL_BEEPEN (1 << 0)
|
||||||
|
#define BEEPCTRL_BEEPVOL_MASK (7 << 1)
|
||||||
|
#define BEEPCTRL_INVROUT2 (1 << 4)
|
||||||
|
#define BEEPCTRL_MUTERPGA2INV (1 << 5)
|
||||||
|
#define BEEPCTRL_BYPR2LMIX (1 << 7)
|
||||||
|
#define BEEPCTRL_BYPL2RMIX (1 << 8)
|
||||||
|
|
||||||
|
#define INCTRL 0x2c
|
||||||
|
#define INCTRL_LIP2INPGA (1 << 0)
|
||||||
|
#define INCTRL_LIN2INPGA (1 << 1)
|
||||||
|
#define INCTRL_L2_2INPGA (1 << 2)
|
||||||
|
#define INCTRL_RIP2INPGA (1 << 4)
|
||||||
|
#define INCTRL_RIN2INPGA (1 << 5)
|
||||||
|
#define INCTRL_R2_2INPGA (1 << 6)
|
||||||
|
#define INCTRL_MBVSEL (1 << 8)
|
||||||
|
|
||||||
|
#define LINPGAVOL 0x2d
|
||||||
|
#define LINPGAVOL_INPGAVOL_MASK 0x3f
|
||||||
|
#define LINPGAVOL_INPGAMUTEL (1 << 6)
|
||||||
|
#define LINPGAVOL_INPGAZCL (1 << 7)
|
||||||
|
#define LINPGAVOL_INPGAVU (1 << 8)
|
||||||
|
|
||||||
|
#define RINPGAVOL 0x2e
|
||||||
|
#define RINPGAVOL_INPGAVOL_MASK 0x3f
|
||||||
|
#define RINPGAVOL_INPGAMUTER (1 << 6)
|
||||||
|
#define RINPGAVOL_INPGAZCR (1 << 7)
|
||||||
|
#define RINPGAVOL_INPGAVU (1 << 8)
|
||||||
|
|
||||||
|
#define LADCBOOST 0x2f
|
||||||
|
#define LADCBOOST_AUXL2BOOST_MASK (7 << 0)
|
||||||
|
#define LADCBOOST_L2_2BOOST_MASK (7 << 4)
|
||||||
|
#define LADCBOOST_L2_2BOOST(x) ((x) << 4)
|
||||||
|
#define LADCBOOST_PGABOOSTL (1 << 8)
|
||||||
|
|
||||||
|
#define RADCBOOST 0x30
|
||||||
|
#define RADCBOOST_AUXR2BOOST_MASK (7 << 0)
|
||||||
|
#define RADCBOOST_R2_2BOOST_MASK (7 << 4)
|
||||||
|
#define RADCBOOST_R2_2BOOST(x) ((x) << 4)
|
||||||
|
#define RADCBOOST_PGABOOSTR (1 << 8)
|
||||||
|
|
||||||
|
#define OUTCTRL 0x31
|
||||||
|
#define OUTCTRL_VROI (1 << 0)
|
||||||
|
#define OUTCTRL_TSDEN (1 << 1)
|
||||||
|
#define OUTCTRL_SPKBOOST (1 << 2)
|
||||||
|
#define OUTCTRL_OUT3BOOST (1 << 3)
|
||||||
|
#define OUTCTRL_OUT4BOOST (1 << 4)
|
||||||
|
#define OUTCTRL_DACR2LMIX (1 << 5)
|
||||||
|
#define OUTCTRL_DACL2RMIX (1 << 6)
|
||||||
|
|
||||||
|
#define LOUTMIX 0x32
|
||||||
|
#define LOUTMIX_DACL2LMIX (1 << 0)
|
||||||
|
#define LOUTMIX_BYPL2LMIX (1 << 1)
|
||||||
|
#define LOUTMIX_BYP2LMIXVOL_MASK (7 << 2)
|
||||||
|
#define LOUTMIX_BYP2LMIXVOL(x) ((x) << 2)
|
||||||
|
#define LOUTMIX_AUXL2LMIX (1 << 5)
|
||||||
|
#define LOUTMIX_AUXLMIXVOL_MASK (7 << 6)
|
||||||
|
|
||||||
|
#define ROUTMIX 0x33
|
||||||
|
#define ROUTMIX_DACR2RMIX (1 << 0)
|
||||||
|
#define ROUTMIX_BYPR2RMIX (1 << 1)
|
||||||
|
#define ROUTMIX_BYP2RMIXVOL_MASK (7 << 2)
|
||||||
|
#define ROUTMIX_BYP2RMIXVOL(x) ((x) << 2)
|
||||||
|
#define ROUTMIX_AUXR2RMIX (1 << 5)
|
||||||
|
#define ROUTMIX_AUXRMIXVOL_MASK (7 << 6)
|
||||||
|
|
||||||
|
#define LOUT1VOL 0x34
|
||||||
|
#define LOUT1VOL_MASK 0x3f
|
||||||
|
#define LOUT1VOL_LOUT1MUTE (1 << 6)
|
||||||
|
#define LOUT1VOL_LOUT1ZC (1 << 7)
|
||||||
|
#define LOUT1VOL_OUT1VU (1 << 8)
|
||||||
|
|
||||||
|
#define ROUT1VOL 0x35
|
||||||
|
#define ROUT1VOL_MASK 0x3f
|
||||||
|
#define ROUT1VOL_ROUT1MUTE (1 << 6)
|
||||||
|
#define ROUT1VOL_ROUT1ZC (1 << 7)
|
||||||
|
#define ROUT1VOL_OUT1VU (1 << 8)
|
||||||
|
|
||||||
|
#define LOUT2VOL 0x36
|
||||||
|
#define LOUT2VOL_MASK 0x3f
|
||||||
|
#define LOUT2VOL_LOUT2MUTE (1 << 6)
|
||||||
|
#define LOUT2VOL_LOUT2ZC (1 << 7)
|
||||||
|
#define LOUT2VOL_OUT2VU (1 << 8)
|
||||||
|
|
||||||
|
#define ROUT2VOL 0x37
|
||||||
|
#define ROUT2VOL_MASK 0x3f
|
||||||
|
#define ROUT2VOL_ROUT2MUTE (1 << 6)
|
||||||
|
#define ROUT2VOL_ROUT2ZC (1 << 7)
|
||||||
|
#define ROUT2VOL_OUT2VU (1 << 8)
|
||||||
|
|
||||||
|
|
||||||
|
/* Dummy definition, to be removed when the audio driver API gets reworked. */
|
||||||
|
#define WM8758_44100HZ 0
|
||||||
|
|
||||||
#endif /* _WM8758_H */
|
#endif /* _WM8758_H */
|
||||||
|
|
|
||||||
|
|
@ -625,8 +625,8 @@ void sound_set(int setting, int value)
|
||||||
sound_set_val(value);
|
sound_set_val(value);
|
||||||
}
|
}
|
||||||
|
|
||||||
#if (!defined(HAVE_AS3514) && !defined (HAVE_WM8731) && !defined (HAVE_WM8975) \
|
#if (!defined(HAVE_AS3514) && !defined (HAVE_WM8731) && !defined(HAVE_WM8975) \
|
||||||
&& !defined(HAVE_TSC2100)) || defined(SIMULATOR)
|
&& !defined(HAVE_WM8758) && !defined(HAVE_TSC2100)) || defined(SIMULATOR)
|
||||||
int sound_val2phys(int setting, int value)
|
int sound_val2phys(int setting, int value)
|
||||||
{
|
{
|
||||||
#if CONFIG_CODEC == MAS3587F
|
#if CONFIG_CODEC == MAS3587F
|
||||||
|
|
|
||||||
|
|
@ -365,7 +365,8 @@ void pcm_play_dma_init(void)
|
||||||
/* Initialize default register values. */
|
/* Initialize default register values. */
|
||||||
audiohw_init();
|
audiohw_init();
|
||||||
|
|
||||||
#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751) && !defined(HAVE_WM8975)
|
#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751) && !defined(HAVE_WM8975) \
|
||||||
|
&& !defined(HAVE_WM8758)
|
||||||
/* Power on */
|
/* Power on */
|
||||||
audiohw_enable_output(true);
|
audiohw_enable_output(true);
|
||||||
/* Unmute the master channel (DAC should be at zero point now). */
|
/* Unmute the master channel (DAC should be at zero point now). */
|
||||||
|
|
|
||||||
|
|
@ -96,13 +96,15 @@ void audiohw_init(void) {
|
||||||
#endif /* IPOD_1G2G/3G */
|
#endif /* IPOD_1G2G/3G */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(HAVE_WM8731) || defined(HAVE_WM8751) || defined(HAVE_WM8975)
|
#if defined(HAVE_WM8731) || defined(HAVE_WM8751) || defined(HAVE_WM8975) \
|
||||||
|
|| defined(HAVE_WM8758)
|
||||||
audiohw_preinit();
|
audiohw_preinit();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751) && !defined(HAVE_WM8975)
|
#if !defined(HAVE_WM8731) && !defined(HAVE_WM8751) && !defined(HAVE_WM8975) \
|
||||||
|
&& !defined(HAVE_WM8758)
|
||||||
void audiohw_postinit(void)
|
void audiohw_postinit(void)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue